Intel 80C196NU User Manual
2-11
ARCHITECTURAL OVERVIEW
2.5
INTERNAL PERIPHERALS
The internal peripheral modules provide special functions for a variety of applications. This sec-
tion provides a brief description of the peripherals; subsequent chapters describe them in detail.
tion provides a brief description of the peripherals; subsequent chapters describe them in detail.
2.5.1
I/O Ports
The 8XC196NP and 80C196NU have five I/O ports, ports 1–4 and the EPORT. Individual port
pins are multiplexed to serve as standard I/O or to carry special-function signals associated with
an on-chip peripheral or an off-chip component. If a particular special-function signal is not used
in an application, the associated pin can be individually configured to serve as a standard I/O pin.
Port 4 has a higher drive capability than the other ports to support pulse-width modulator (PWM)
high-drive outputs.
pins are multiplexed to serve as standard I/O or to carry special-function signals associated with
an on-chip peripheral or an off-chip component. If a particular special-function signal is not used
in an application, the associated pin can be individually configured to serve as a standard I/O pin.
Port 4 has a higher drive capability than the other ports to support pulse-width modulator (PWM)
high-drive outputs.
Ports 1–4 are eight-bit, bidirectional, standard I/O ports. Only the lower nibble of port 4 is imple-
mented in current package offerings. Port 1 provides I/O pins for the four event processor array
(EPA) modules and the two timers. Port 2 is used for the serial I/O (SIO) port, two external inter-
rupts, and bus hold functions. Port 3 is used for chip-select functions and two external interrupts.
Port 4 (functionally only a 4-bit port) provides I/O pins associated with the three on-chip pulse-
width modulators. The EPORT provides address lines A19:16 to support extended addressing.
See Chapter 7, “I/O Ports,” for more information.
mented in current package offerings. Port 1 provides I/O pins for the four event processor array
(EPA) modules and the two timers. Port 2 is used for the serial I/O (SIO) port, two external inter-
rupts, and bus hold functions. Port 3 is used for chip-select functions and two external interrupts.
Port 4 (functionally only a 4-bit port) provides I/O pins associated with the three on-chip pulse-
width modulators. The EPORT provides address lines A19:16 to support extended addressing.
See Chapter 7, “I/O Ports,” for more information.
2.5.2
Serial I/O (SIO) Port
The serial I/O (SIO) port is an asynchronous/synchronous port that includes a universal asynchro-
nous receiver and transmitter (UART). The UART has one synchronous mode (mode 0) and three
asynchronous modes (modes 1, 2, and 3) for both transmission and reception. The asynchronous
modes are full duplex, meaning that they can transmit and receive data simultaneously. The re-
ceiver is buffered, so the reception of a second byte can begin before the first byte is read. The
transmitter is also buffered, allowing continuous transmissions. See Chapter 8, “Serial I/O (SIO)
Port,” for details.
nous receiver and transmitter (UART). The UART has one synchronous mode (mode 0) and three
asynchronous modes (modes 1, 2, and 3) for both transmission and reception. The asynchronous
modes are full duplex, meaning that they can transmit and receive data simultaneously. The re-
ceiver is buffered, so the reception of a second byte can begin before the first byte is read. The
transmitter is also buffered, allowing continuous transmissions. See Chapter 8, “Serial I/O (SIO)
Port,” for details.
2.5.3
Event Processor Array (EPA) and Timer/Counters
The event processor array (EPA) performs high-speed input and output functions associated with
its timer/counters. In the input mode, the EPA monitors an input for signal transitions. When an
event occurs, the EPA records the timer value associated with it. This is a capture event. In the
output mode, the EPA monitors a timer until its value matches that of a stored time value. When
a match occurs, the EPA triggers an output event, which can set, clear, or toggle an output pin.
This is a compare event. Both capture and compare events can initiate interrupts, which can be
serviced by either the interrupt controller or the PTS.
its timer/counters. In the input mode, the EPA monitors an input for signal transitions. When an
event occurs, the EPA records the timer value associated with it. This is a capture event. In the
output mode, the EPA monitors a timer until its value matches that of a stored time value. When
a match occurs, the EPA triggers an output event, which can set, clear, or toggle an output pin.
This is a compare event. Both capture and compare events can initiate interrupts, which can be
serviced by either the interrupt controller or the PTS.