Intel 80C196NU User Manual
8XC196NP, 80C196NU USER’S MANUAL
5-12
Subroutines may be nested. That is, each subroutine may call other subroutines. The CPU PUSH-
es the contents of the program counter onto the stack each time it executes a subroutine call. The
stack grows downward as entries are added. The only limit to the nesting depth is the amount of
available memory. As the CPU returns from each nested subroutine, it POPs the address off the
top of the stack, and the next return address moves to the top of the stack.
es the contents of the program counter onto the stack each time it executes a subroutine call. The
stack grows downward as entries are added. The only limit to the nesting depth is the amount of
available memory. As the CPU returns from each nested subroutine, it POPs the address off the
top of the stack, and the next return address moves to the top of the stack.
Your program must load a word-aligned (even) address into the stack pointer. Select an address
that is two bytes (for 64-Kbyte mode) or four bytes (for 1-Mbyte mode) greater than the desired
starting address because the CPU automatically decrements the stack pointer before it pushes the
first byte of the return address onto the stack. Remember that the stack grows downward, so allow
sufficient room for the maximum number of stack entries. The stack must be located in page 00H,
in either the internal register file or external RAM. The stack can be used most efficiently when
it is located in the upper register file.
that is two bytes (for 64-Kbyte mode) or four bytes (for 1-Mbyte mode) greater than the desired
starting address because the CPU automatically decrements the stack pointer before it pushes the
first byte of the return address onto the stack. Remember that the stack grows downward, so allow
sufficient room for the maximum number of stack entries. The stack must be located in page 00H,
in either the internal register file or external RAM. The stack can be used most efficiently when
it is located in the upper register file.
The following example initializes the top of the upper register file as the stack.
LD
SP, #400H
;Load stack pointer
5.2.4.3
CPU Special-function Registers (SFRs)
Locations 0000–0017H in the lower register file are the CPU SFRs. Table 5-7 lists the CPU SFRs
for the 8XC196NP and the 80C196NU and highlights those that are unique to the 80C196NU.
Appendix C describes the CPU SFRs.
for the 8XC196NP and the 80C196NU and highlights those that are unique to the 80C196NU.
Appendix C describes the CPU SFRs.
Table 5-7. CPU SFRs
8XC196NP CPU SFRs
80C196NU CPU SFRs
Address
High (Odd) Byte
Low (Even) Byte
Address
High (Odd) Byte
Low (Even) Byte
0016H
Reserved
Reserved
0016H
Reserved
Reserved
0014H
Reserved
WSR
0014H
WSR1
†
WSR
0012H
INT_MASK1
INT_PEND1
0012H
INT_MASK1
INT_PEND1
0010H
Reserved
Reserved
0010H
Reserved
Reserved
000EH
Reserved
Reserved
000EH
††
ACC_03
†
ACC_02
†
000CH
Reserved
Reserved
000CH
††
ACC_01
†
ACC_00
†
000AH
Reserved
Reserved
000AH
ACC_STAT
†
Reserved
0008H
INT_PEND
INT_MASK
0008H
INT_PEND
INT_MASK
0006H
PTSSRV (H)
PTSSRV (L)
0006H
PTSSRV (H)
PTSSRV (L)
0004H
PTSSEL (H)
PTSSEL (L)
0004H
PTSSEL (H)
PTSSEL (L)
0002H
ONES_REG (H)
ONES_REG (L)
0002H
ONES_REG (H)
ONES_REG (L)
0000H
ZERO_REG (H)
ZERO_REG (L)
0000H
ZERO_REG (H)
ZERO_REG (L)
†
These SFRs are unique to the 80C196NU.
††
Must be addressed as a word.