Intel 8XC196MH User Manual
8XC196MC, MD, MH USER’S MANUAL
11-24
11.7 DETERMINING EVENT STATUS
In compare mode, an interrupt pending bit is set each time a match occurs on an enabled event
(even if the interrupt is specifically masked in the mask register). In capture mode, an interrupt
pending bit is set each time a programmed event is captured and the event time moves from the
capture buffer to the EPAx_TIME register.
(even if the interrupt is specifically masked in the mask register). In capture mode, an interrupt
pending bit is set each time a programmed event is captured and the event time moves from the
capture buffer to the EPAx_TIME register.
The pending bits are located in the INT_PEND and INT_PEND1 registers (Figure 5-7 on page
5-15 and Figure 5-11 on page 5-22). The pending bits for the multiplexed interrupts (those that
share the PI interrupt) are located in the PI_PEND register (Figure 5-12 on page 5-23). Timer
overflows/underflows also set interrupt pending bits. Even if an interrupt is masked, software can
poll the interrupt pending registers to determine whether an event has occurred.
5-15 and Figure 5-11 on page 5-22). The pending bits for the multiplexed interrupts (those that
share the PI interrupt) are located in the PI_PEND register (Figure 5-12 on page 5-23). Timer
overflows/underflows also set interrupt pending bits. Even if an interrupt is masked, software can
poll the interrupt pending registers to determine whether an event has occurred.