Intel 8XC196MH User Manual
Index-1
#, defined, 1-3, A-1
16-bit data bus
16-bit data bus
read cycles, 15-14
timing diagram, 15-15
write cycles, 15-14
timing diagram, 15-15
write cycles, 15-14
8-bit data bus
read cycles, 15-16
timing diagram, 15-17
write cycles, 15-16
timing diagram, 15-17
write cycles, 15-16
A
A/D command register, 12-8, C-6
A/D converter, 2-11, 12-1–12-18
A/D converter, 2-11, 12-1–12-18
actual characteristic, 12-16
and port 0 reads, 12-13
and PTS, 5-32–5-37
block diagram, 12-1
calculating result, 12-9, 12-13
calculating series resistance, 12-10
characteristics, 12-15–12-18
conversion time, 12-6
determining status, 12-9
errors, 12-13–12-18
hardware considerations, 12-10–12-13
ideal characteristic, 12-15, 12-16
input circuit, suggested, 12-12
input protection devices, 12-12
interfacing with, 12-10–12-13
interpreting results, 12-9
interrupt, 12-8
minimizing input source resistance, 12-11
overview, 12-3–12-4
programming, 12-4–12-8
sample delay, 12-4
sample time, 12-6
sample window, 12-4
SFRs, 12-2
signals, 12-2
starting with PTS, 5-32–5-37
successive approximation
and port 0 reads, 12-13
and PTS, 5-32–5-37
block diagram, 12-1
calculating result, 12-9, 12-13
calculating series resistance, 12-10
characteristics, 12-15–12-18
conversion time, 12-6
determining status, 12-9
errors, 12-13–12-18
hardware considerations, 12-10–12-13
ideal characteristic, 12-15, 12-16
input circuit, suggested, 12-12
input protection devices, 12-12
interfacing with, 12-10–12-13
interpreting results, 12-9
interrupt, 12-8
minimizing input source resistance, 12-11
overview, 12-3–12-4
programming, 12-4–12-8
sample delay, 12-4
sample time, 12-6
sample window, 12-4
SFRs, 12-2
signals, 12-2
starting with PTS, 5-32–5-37
successive approximation
algorithm, 12-4
register (SAR), 12-4
register (SAR), 12-4
terminal-based characteristic, 12-18
threshold-detection modes, 12-5
threshold-detection modes, 12-5
transfer function, 12-15–12-18
zero-offset adjustment, 12-3, 12-5
zero-offset error, 12-16
See also port 0
zero-offset adjustment, 12-3, 12-5
zero-offset error, 12-16
See also port 0
A/D result register (read), 12-9, C-7
A/D result register (write), 12-6, C-8
A/D scan mode‚ See PTS
A/D test register, 12-5, C-9
A/D time register, 12-7, C-10
AC timing
A/D result register (write), 12-6, C-8
A/D scan mode‚ See PTS
A/D test register, 12-5, C-9
A/D time register, 12-7, C-10
AC timing
specifications, 15-31–15-34
symbol explanations, 15-33
symbol explanations, 15-33
Accumulator, RALU, 2-5
ACH13:0, B-13
AD_COMMAND, C-68
AD_RESULT, 12-9, C-68
AD_TEST, C-68
AD_TIME, C-68
AD15:0, B-13
ADD instruction, A-2, A-7, A-41, A-42, A-47,
ACH13:0, B-13
AD_COMMAND, C-68
AD_RESULT, 12-9, C-68
AD_TEST, C-68
AD_TIME, C-68
AD15:0, B-13
ADD instruction, A-2, A-7, A-41, A-42, A-47,
A-52
ADDB instruction, A-2, A-7, A-42, A-43, A-47,
A-52
ADDC instruction, A-2, A-7, A-44, A-47, A-52
ADDCB instruction, A-2, A-8, A-44, A-47, A-52
Address space
ADDCB instruction, A-2, A-8, A-44, A-47, A-52
Address space
map, 4-2
See also memory partitions
See also memory partitions
Address valid strobe mode
ALE/ADV# comparison, 15-27
example system, 15-28, 15-29
signals, 15-27
example system, 15-28, 15-29
signals, 15-27
Address valid with write strobe mode
example system, 15-31
signals, 15-30
signals, 15-30
Address/data bus, 2-6
multiplexing, 15-10–15-17
Addressing modes, 3-5–3-6, A-6
ADV#, B-13
AINC#, 16-12, B-14
ALE, B-14
ADV#, B-13
AINC#, 16-12, B-14
ALE, B-14
idle, powerdown, reset status, B-23, B-25
Analog outputs, generating, 10-10
Analog-to-digital converter‚ See A/D converter
Analog-to-digital converter‚ See A/D converter
INDEX