Acer Intel Core i5-3210M User Manuals

Table of Contents

• Mobile 3rd Generation Intel® Core™ Processor Family

  1
• 1 Introduction

  11
  • 1.1 Processor Feature Details

    13
    • 1.1.1 Supported Technologies

      13
  • 1.2 Interfaces

    13
    • 1.2.1 System Memory Support

      13
    • 1.2.2 PCI Express*

      14
    • 1.2.3 Direct Media Interface (DMI)

      15
    • 1.2.4 Platform Environment Control Interface (PECI)

      16
    • 1.2.5 Processor Graphics

      16
    • 1.2.6 Embedded DisplayPort* (eDP*)

      17
    • 1.2.7 Intel® Flexible Display Interface (Intel® FDI)

      17
  • 1.3 Power Management Support

    17
    • 1.3.1 Processor Core

      17
    • 1.3.2 System

      17
    • 1.3.3 Memory Controller

      17
    • 1.3.4 PCI Express*

      17
    • 1.3.5 DMI

      17
    • 1.3.6 Processor Graphics Controller (GT)

      18
    • 1.3.7 Thermal Management Support

      18
  • 1.4 Mobile 3rd Generation Intel® Core™ Processor Family SKU Definition

    18
  • 1.5 Package

    18
  • 1.6 Processor Compatibility

    19
  • 1.7 Terminology

    20
  • 1.8 Related Documents

    22
• 2 Interfaces

  23
  • 2.1 System Memory Interface

    23
    • 2.1.1 System Memory Technology Supported

      23
    • 2.1.2 System Memory Timing Support

      24
    • 2.1.3 System Memory Organization Modes

      25
      • 2.1.3.1 Single-Channel Mode

        25
      • 2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode

        25
    • 2.1.4 Rules for Populating Memory Slots

      26
    • 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

      27
      • 2.1.5.1 Just-in-Time Command Scheduling

        27
      • 2.1.5.2 Command Overlap

        27
      • 2.1.5.3 Out-of-Order Scheduling

        27
    • 2.1.6 Data Scrambling

      27
    • 2.1.7 DRAM Clock Generation

      27
    • 2.1.8 DDR3 Reference Voltage Generation

      28
  • 2.2 PCI Express* Interface

    28
    • 2.2.1 PCI Express* Architecture

      28
      • 2.2.1.1 Transaction Layer

        29
      • 2.2.1.2 Data Link Layer

        29
      • 2.2.1.3 Physical Layer

        29
    • 2.2.2 PCI Express* Configuration Mechanism

      30
    • 2.2.3 PCI Express* Graphics

      31
      • 2.2.3.1 PCI Express* Lanes Connection

        31
  • 2.3 Direct Media Interface (DMI)

    32
    • 2.3.1 DMI Error Flow

      32
    • 2.3.2 Processor/PCH Compatibility Assumptions

      32
    • 2.3.3 DMI Link Down

      32
  • 2.4 Processor Graphics Controller (GT)

    32
    • 2.4.1 3D and Video Engines for Graphics Processing

      33
      • 2.4.1.1 3D Engine Execution Units

        33
      • 2.4.1.2 3D Pipeline

        34
      • 2.4.1.3 Video Engine

        34
      • 2.4.1.4 2D Engine

        35
    • 2.4.2 Processor Graphics Display

      36
      • 2.4.2.1 Display Planes

        36
      • 2.4.2.2 Display Pipes

        37
      • 2.4.2.3 Display Ports

        37
      • 2.4.2.4 Embedded DisplayPort (eDP)

        37
    • 2.4.3 Intel® Flexible Display Interface

      37
    • 2.4.4 Multi Graphics Controllers Multi-Monitor Support

      38
  • 2.5 Platform Environment Control Interface (PECI)

    38
  • 2.6 Interface Clocking

    38
    • 2.6.1 Internal Clocking Requirements

      38
• 3 Technologies

  39
  • 3.1 Intel® Virtualization Technology

    39
    • 3.1.1 Intel® VT-x Objectives

      39
    • 3.1.2 Intel® VT-x Features

      40
    • 3.1.3 Intel® VT-d Objectives

      40
    • 3.1.4 Intel® VT-d Features

      40
    • 3.1.5 Intel® VT-d Features Not Supported

      41
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    41
  • 3.3 Intel® Hyper-Threading Technology

    42
  • 3.4 Intel® Turbo Boost Technology

    42
    • 3.4.1 Intel®Turbo Boost Technology Frequency

      43
    • 3.4.2 Intel® Turbo Boost Technology Graphics Frequency

      43
  • 3.5 Intel® Advanced Vector Extensions (AVX)

    44
  • 3.6 Security and Cryptography Technologies

    44
    • 3.6.1 Advanced Encryption Standard New Instructions (AES-NI)

      44
    • 3.6.2 PCLMULQDQ Instruction

      44
    • 3.6.3 RDRAND Instruction

      45
  • 3.7 Intel® 64 Architecture x2APIC

    45
  • 3.8 Supervisor Mode Execution Protection (SMEP)

    46
  • 3.9 Power Aware Interrupt Routing (PAIR)

    46
• 4 Power Management

  47
  • 4.1 ACPI States Supported

    48
    • 4.1.1 System States

      48
    • 4.1.2 Processor Core/Package Idle States

      48
    • 4.1.3 Integrated Memory Controller States

      48
    • 4.1.4 PCI Express* Link States

      49
    • 4.1.5 DMI States

      49
    • 4.1.6 Processor Graphics Controller States

      49
    • 4.1.7 Interface State Combinations

      49
  • 4.2 Processor Core Power Management

    50
    • 4.2.1 Enhanced Intel® SpeedStep® Technology

      50
    • 4.2.2 Low-Power Idle States

      51
    • 4.2.3 Requesting Low-Power Idle States

      52
    • 4.2.4 Core C-states

      53
      • 4.2.4.1 Core C0 State

        53
      • 4.2.4.2 Core C1/C1E State

        53
      • 4.2.4.3 Core C3 State

        53
      • 4.2.4.4 Core C6 State

        53
      • 4.2.4.5 Core C7 State

        54
      • 4.2.4.6 C-State Auto-Demotion

        54
    • 4.2.5 Package C-States

      54
      • 4.2.5.1 Package C0

        56
      • 4.2.5.2 Package C1/C1E

        56
      • 4.2.5.3 Package C3 State

        56
      • 4.2.5.4 Package C6 State

        56
      • 4.2.5.5 Package C7 State

        57
      • 4.2.5.6 Dynamic L3 Cache Sizing

        57
  • 4.3 IMC Power Management

    57
    • 4.3.1 Disabling Unused System Memory Outputs

      57
    • 4.3.2 DRAM Power Management and Initialization

      58
      • 4.3.2.1 Initialization Role of CKE

        59
      • 4.3.2.2 Conditional Self-Refresh

        59
      • 4.3.2.3 Dynamic Power Down Operation

        60
      • 4.3.2.4 DRAM I/O Power Management

        60
    • 4.3.3 DDR Electrical Power Gating (EPG)

      60
  • 4.4 PCI Express* Power Management

    61
  • 4.5 DMI Power Management

    61
  • 4.6 Graphics Power Management

    61
    • 4.6.1 Intel® Rapid Memory Power Management (RMPM) (also known as CxSR)

      61
    • 4.6.2 Intel® Graphics Performance Modulation Technology (GPMT)

      61
    • 4.6.3 Graphics Render C-State

      62
    • 4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)

      62
    • 4.6.5 Intel® Graphics Dynamic Frequency

      62
    • 4.6.6 Display Power Savings Technology 6.0 (DPST)

      63
    • 4.6.7 Automatic Display Brightness (ADB)

      63
    • 4.6.8 Seamless Display Refresh Rate Switching Technology (SDRRST)

      63
  • 4.7 Graphics Thermal Power Management

    64
• 5 Thermal Management

  65
  • 5.1 Thermal Considerations

    65
  • 5.2 Intel® Turbo Boost Technology Power Monitoring

    65
  • 5.3 Intel® Turbo Boost Technology Power Control

    66
    • 5.3.1 Package Power Control

      66
    • 5.3.2 Power Plane Control

      68
    • 5.3.3 Turbo Time Parameter

      68
  • 5.4 Configurable TDP and Low Power Mode

    68
    • 5.4.1 Configurable TDP

      68
    • 5.4.2 Low Power Mode

      69
  • 5.5 Thermal and Power Specifications

    70
  • 5.6 Thermal Management Features

    73
    • 5.6.1 Adaptive Thermal Monitor

      73
      • 5.6.1.1 TCC Activation Offset

        74
      • 5.6.1.2 Frequency/Voltage Control

        74
      • 5.6.1.3 Clock Modulation

        76
    • 5.6.2 Digital Thermal Sensor

      76
      • 5.6.2.1 Digital Thermal Sensor Accuracy (Taccuracy)

        77
      • 5.6.2.2 Fan Speed Control with Digital Thermal Sensor

        77
    • 5.6.3 PROCHOT# Signal

      77
      • 5.6.3.1 Bi-Directional PROCHOT#

        77
      • 5.6.3.2 Voltage Regulator Protection versus PROCHOT#

        78
      • 5.6.3.3 Thermal Solution Design and PROCHOT# Behavior

        78
      • 5.6.3.4 Low-Power States and PROCHOT# Behavior

        78
      • 5.6.3.5 THERMTRIP# Signal

        79
      • 5.6.3.6 Critical Temperature Detection

        79
    • 5.6.4 On-Demand Mode

      79
      • 5.6.4.1 MSR Based On-Demand Mode

        79
      • 5.6.4.2 I/O Emulation-Based On-Demand Mode

        79
    • 5.6.5 Memory Thermal Management

      80
    • 5.6.6 Platform Environment Control Interface (PECI)

      80
• 6 Signal Description

  81
  • 6.1 System Memory Interface

    82
  • 6.2 Memory Reference and Compensation

    84
  • 6.3 Reset and Miscellaneous Signals

    84
  • 6.4 PCI Express*-based Interface Signals

    85
  • 6.5 Embedded DisplayPort (eDP)

    85
  • 6.6 Intel® Flexible Display Interface Signals

    85
  • 6.7 Direct Media Interface (DMI)

    86
  • 6.8 Phase Lock Loop (PLL) Signals

    86
  • 6.9 Test Access Points (TAP) Signals

    86
  • 6.10 Error and Thermal Protection

    87
  • 6.11 Power Sequencing

    88
  • 6.12 Processor Power Signals

    89
  • 6.13 Sense Signals

    89
  • 6.14 Ground and NCTF

    90
  • 6.15 Processor Internal Pull-Up / Pull-Down

    90
• 7 Electrical Specifications

  91
  • 7.1 Power and Ground Pins

    91
  • 7.2 Decoupling Guidelines

    91
    • 7.2.1 Voltage Rail Decoupling

      91
    • 7.2.2 PLL Power Supply

      91
  • 7.3 Voltage Identification (VID)

    92
  • 7.4 System Agent (SA) Vcc VID

    95
  • 7.5 Reserved or Unused Signals

    95
  • 7.6 Signal Groups

    96
  • 7.7 Test Access Port (TAP) Connection

    98
  • 7.8 Component Storage Condition Specifications (Prior to Board Attach)

    98
  • 7.9 DC Specifications

    99
    • 7.9.1 Voltage and Current Specifications

      99
  • 7.10 Platform Environmental Control Interface (PECI) DC Specifications

    106
    • 7.10.1 PECI Bus Architecture

      106
    • 7.10.2 PECI DC Characteristics

      107
    • 7.10.3 Input Device Hysteresis

      107
• 8 Processor Pin, Signal, and Package Information

  109
  • 8.1 Processor Pin Assignments

    109
  • 8.2 Package Mechanical Information

    156
• 9 DDR Data Swizzling

  165