User ManualTable of ContentsList of Figures5List of Tables9Overview131.1 General Description131.2 Features14Architecture Overview172.1 GX1 Module172.1.1 Memory Controller172.1.2 Fast-PCI Bus222.1.3 Display222.2 Video Processor Module222.2.1 GX1 Module Interface222.2.2 Video Input Port222.2.3 Core Logic Module Interface222.3 Core Logic Module222.3.1 Other Core Logic Module Interfaces222.4 Super I/O Module232.5 Clock, Timers, and Reset Logic232.5.1 Reset Logic232.5.1.1 Power-On Reset232.5.1.2 System Reset23Signal Definitions253.1 Ball Assignments273.2 Strap Options443.3 Multiplexing Configuration453.4 Signal Descriptions493.4.1 System Interface493.4.2 Memory Interface Signals503.4.3 Video Port Interface Signals513.4.4 TFT Interface Signals523.4.5 ACCESS.bus Interface Signals523.4.6 PCI Bus Interface Signals533.4.7 Sub-ISA Interface Signals573.4.8 Low Pin Count (LPC) Bus Interface Signals583.4.9 IDE Interface Signals583.4.10 Universal Serial Bus (USB) Interface Signals593.4.11 Serial Ports (UARTs) Interface Signals603.4.12 Parallel Port Interface Signals613.4.13 Fast Infrared (IR) Port Interface Signals623.4.14 AC97 Audio Interface Signals633.4.15 Power Management Interface Signals643.4.16 GPIO Interface Signals653.4.17 Debug Monitoring Interface Signals663.4.18 JTAG Interface Signals663.4.19 Test and Measurement Interface Signals673.4.20 Power, Ground and No Connections68General Configuration Block694.1 Configuration Block Addresses694.2 Multiplexing, Interrupt Selection, and Base Address Registers704.3 WATCHDOG774.3.1 Functional Description774.3.1.1 WATCHDOG Timer774.3.2 WATCHDOG Registers784.3.2.1 Usage Hints784.4 High-Resolution Timer794.4.1 Functional Description794.4.2 High-Resolution Timer Registers794.4.2.1 Usage Hints794.5 Clock Generators and PLLs814.5.1 27 MHz Crystal Oscillator824.5.2 GX1 Module Core Clock834.5.3 Internal Fast-PCI Clock834.5.4 SuperI/O Clocks844.5.5 Core Logic Module Clocks844.5.6 Video Processor Clocks844.5.7 Clock Registers85SuperI/O Module875.1 Features885.2 Module Architecture895.3 Configuration Structure / Access905.3.1 Index-Data Register Pair905.3.2 Banked Logical Device Registers905.3.3 Default Configuration Setup915.3.4 Address Decoding915.4 Standard Configuration Registers925.4.1 SIO Control and Configuration Registers955.4.2 Logical Device Control and Configuration965.4.2.1 LDN 00h - Real-Time Clock965.4.2.2 LDN 01h - System Wakeup Control985.4.2.3 LDN 02h - Infrared Communication Port or Serial Port 3995.4.2.4 LDN 03h and 08h - Serial Ports 1 and 21005.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 21015.4.2.6 LDN 07h - Parallel Port1025.5 Real-Time Clock (RTC)1035.5.1 Bus Interface1035.5.2 RTC Clock Generation1035.5.2.1 Internal Oscillator1035.5.2.2 External Oscillator1045.5.2.3 Timing Generation1045.5.2.4 Timekeeping1055.5.2.5 Alarms1055.5.2.6 Power Supply1065.5.2.7 System Power States1075.5.2.8 Oscillator Activity1075.5.2.9 Interrupt Handling1085.5.2.10 Battery-Backed RAMs and Registers1085.5.3 RTC Registers1095.5.3.1 Usage Hints1135.5.4 RTC General-Purpose RAM Map1135.6 System Wakeup Control (SWC)1145.6.1 Event Detection1145.6.1.1 Audio Codec Event1145.6.1.2 CEIR Address1145.6.2 SWC Registers1155.7 ACCESS.bus Interface1195.7.1 Data Transactions1195.7.2 Start and Stop Conditions1195.7.3 Acknowledge (ACK) Cycle1205.7.4 Acknowledge After Every Byte Rule1215.7.5 Addressing Transfer Formats1215.7.6 Arbitration on the Bus1215.7.7 Master Mode1215.7.7.1 Master Stop1225.7.8 Slave Mode1235.7.9 Configuration1235.7.10 ACB Registers1245.8 Legacy Functional Blocks1275.8.1 Parallel Port1275.8.1.1 Parallel Port Register and Bit Maps1275.8.2 UART Functionality (SP1 and SP2)1295.8.2.1 UART Mode Register Bank Overview1295.8.2.2 SP1 and SP2 Register and Bit Maps for UART Functionality1295.8.3 IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality1335.8.3.1 IR/SP3 Mode Register Bank Overview1335.8.3.2 IRCP/SP3 Register and Bit Maps133Core Logic Module1396.1 Feature List1396.2 Module Architecture1406.2.1 Fast-PCI Interface to External PCI Bus1416.2.1.1 Processor Mastered Cycles1416.2.1.2 External PCI Mastered Cycles1416.2.1.3 Core Logic Internal or Sub-ISA Mastered Cycles1416.2.1.4 External PCI Bus1416.2.1.5 Bus Master Request Priority1416.2.2 PSERIAL Interface1416.2.2.1 Video Retrace Interrupt1426.2.3 IDE Controller1426.2.3.1 IDE Configuration Registers1426.2.3.2 PIO Mode1426.2.3.3 Bus Master Mode1436.2.3.4 UltraDMA/33 Mode1446.2.4 Universal Serial Bus1456.2.5 Sub-ISA Bus Interface1456.2.5.1 Sub-ISA Bus Cycles1466.2.5.2 Sub-ISA Support of Delayed PCI Transactions1466.2.5.3 Sub-ISA Bus Data Steering1476.2.5.4 I/O Recovery Delays1476.2.5.5 ISA DMA1486.2.5.6 ROM Interface1496.2.5.7 PCI and Sub-ISA Signal Cycle Multiplexing1496.2.6 AT Compatibility Logic1506.2.6.1 DMA Controller1506.2.6.2 Programmable Interval Timer1526.2.6.3 Programmable Interrupt Controller1536.2.7 I/O Ports 092h and 061h System Control1546.2.7.1 I/O Port 092h System Control1556.2.7.2 I/O Port 061h System Control1556.2.7.3 SMI Generation for NMI1556.2.8 Keyboard Support1556.2.8.1 Fast Keyboard Gate Address 20 and CPU Reset1556.2.9 Power Management Logic1566.2.9.1 CPU States1566.2.9.2 Sleep States1576.2.9.3 Power Planes Control1586.2.9.4 Power Management Events1586.2.9.5 Usage Hints1596.2.10 Power Management Programming1606.2.10.1 APM Support1606.2.10.2 CPU Power Management1606.2.10.3 Peripheral Power Management1626.2.10.4 Power Management Programming Summary1646.2.11 GPIO Interface1656.2.12 Integrated Audio1656.2.12.1 Data Transport Hardware1656.2.12.2 AC97 Codec Interface1686.2.12.3 VSA Technology Support Hardware1696.2.12.4 IRQ Configuration Registers1716.2.12.5 LPC Interface1716.2.12.6 LPC Interface Signal Definitions1726.2.12.7 Cycle Types1726.2.12.8 LPC Interface Support1726.3 Register Descriptions1736.3.1 PCI Configuration Space and Access Methods1736.3.2 Register Summary1746.4 Chipset Register Space1886.4.1 Bridge, GPIO, and LPC Registers - Function 01886.4.1.1 GPIO Support Registers2226.4.1.2 LPC Support Registers2266.4.2 SMI Status and ACPI Registers - Function 12346.4.2.1 SMI Status Support Registers2356.4.2.2 ACPI Support Registers2456.4.3 IDE Controller Registers - Function 22556.4.3.1 IDE Controller Support Registers2596.4.4 Audio Registers - Function 32616.4.4.1 Audio Support Registers2626.4.5 X-Bus Expansion Interface - Function 52766.4.5.1 X-Bus Expansion Support Registers2806.4.6 USB Controller Registers - PCIUSB2826.4.7 ISA Legacy Register Space295Video Processor Module3097.1 Module Architecture3107.2 Functional Description3117.2.1 Video Input Port (VIP)3137.2.1.1 Direct Video Mode3137.2.1.2 Capture Video Mode3147.2.1.3 Capture VBI Mode3167.2.2 Video Block3177.2.2.1 Video Input Formatter3177.2.2.2 Horizontal Downscaler with 4-Tap Filtering3187.2.2.3 Line Buffers3197.2.2.4 Formatter3197.2.2.5 2-Tap Vertical and Horizontal Upscalers3197.2.3 Mixer/Blender Block3207.2.3.1 YUV to RGB CSC in Video Data Path3217.2.3.2 Gamma Correction3217.2.3.3 Color/Chroma Key3217.2.3.4 Color/Chroma Key and Mixer/Blender3227.2.4 TFT Interface3257.2.5 Integrated PLL3267.3 Register Descriptions3277.3.1 Register Summary3277.3.2 Video Processor Registers - Function 43307.3.2.1 Video Processor Support Registers - F4BAR03327.3.2.2 VIP Support Registers - F4BAR2345Debugging and Monitoring3498.1 Testability (JTAG)3498.1.1 Mandatory Instruction Support3498.1.2 Optional Instruction Support3498.1.3 JTAG Chain349Electrical Specifications3519.1 General Specifications3519.1.1 Electro Static Discharge (ESD)3519.1.2 Power/Ground Connections and Decoupling3519.1.3 Absolute Maximum Ratings3519.1.4 Operating Conditions3529.1.5 DC Current3539.1.5.1 Power State Parameter Definitions3539.1.5.2 Definition and Measurement Techniques of SC3200 Current Parameters3539.1.5.3 Definition of System Conditions for Measuring On Parameters3549.1.5.4 DC Current Measurements3549.1.6 Ball Capacitance and Inductance3559.1.7 Pull-Up and Pull-Down Resistors3569.2 DC Characteristics3579.2.1 INAB DC Characteristics3589.2.2 INBTN DC Characteristics3589.2.3 INPCI DC Characteristics3589.2.4 INSTRP DC Characteristics3599.2.5 INT DC Characteristics3599.2.6 INTS DC Characteristics3599.2.7 INTS1 DC Characteristics3599.2.8 INUSB DC Characteristics3609.2.9 OAC97 DC Characteristics3609.2.10 ODn DC Characteristics3609.2.11 ODPCI DC Characteristics3619.2.12 Op/n DC Characteristics3619.2.13 OPCI DC Characteristics3619.2.14 OUSB DC Characteristics3619.2.15 TSp/n DC Characteristics3619.2.15.1 Exceptions3619.3 AC Characteristics3629.3.1 Memory Controller Interface3639.3.2 Video Port3669.3.3 TFT Interface3679.3.4 ACCESS.bus Interface3689.3.5 PCI Bus Interface3719.3.5.1 Measurement and Test Conditions3759.3.6 Sub-ISA Interface3779.3.7 LPC Interface3819.3.8 IDE Interface3829.3.9 Universal Serial Bus (USB) Interface4009.3.10 Serial Port (UART)4049.3.11 Fast IR Port4059.3.12 Parallel Port Interface4069.3.12.1 Extended Capabilities Port (ECP)4089.3.13 Audio Interface (AC97)4109.3.14 Power Management Interface4159.3.15 Power-Up Sequencing4169.3.16 JTAG Interface418Package Specifications42110.1 Thermal Characteristics42110.1.1 Heatsink Considerations42210.2 Physical Dimensions423Support Documentation425A.1 Order Information425A.2 Data Book Revision History426Size: 3.26 MBPages: 428Language: EnglishOpen manual