Analog Devices AD9119 Evaluation Board AD9119-EBZ User Manuals

Table of Contents

• Features

  1
• Applications

  1
• Functional Block Diagram

  1
• General Description

  1
• Product Highlights

  1
• Revision History

  2
• Specifications

  3
  • DC Specifications

    3
  • LVDS Digital Specifications

    4
  • HSTL Digital Specifications

    4
  • Serial Port and CMOS Pin Specifications

    5
  • AC Specifications

    6
• Absolute Maximum Ratings

  7
  • Thermal Resistance

    7
  • ESD Caution

    7
• Pin Configurations and Function Descriptions

  8
• Typical Performance Characteristics

  12
  • AD9119

    12
    • Static Linearity

      12
    • AC (Normal Mode)

      13
    • AC (Mix-Mode)

      16
    • DOCSIS Performance (Normal Mode)

      19
  • AD9129

    22
    • Static Linearity

      22
    • AC (Normal Mode)

      23
    • AC (Mix-Mode)

      27
    • DOCSIS Performance (Normal Mode)

      31
• Terminology

  35
• Serial Communications Port Overview

  36
  • Serial Peripheral Interface (SPI)

    36
  • General Operation of the SPI

    36
  • Instruction Mode (8-Bit Instruction)

    36
  • Serial Peripheral Interface Pin Descriptions

    36
    • SCLK—Serial Clock

      36
    • —Chip Select

      36
    • SDIO—Serial Data I/O

      36
    • SDO—Serial Data Out

      36
  • MSB/LSB Transfers

    37
  • Serial Port Configuration

    37
• Theory of Operation

  38
  • LVDS Data Port Interface

    39
    • Temperature Effects

      41
    • Parity

      41
  • Digital Datapath Description

    42
    • FIFO Description

      43
    • Resetting the FIFO Data Level

      43
    • Monitoring the FIFO Status

      43
    • Multiple DAC Synchronization

      43
    • Data Assembler and Signal Processing Modes

      45
    • 2× Digital Filter

      45
    • Pipeline Delay (Latency)

      46
    • Power-Up Time

      46
  • Interrupt Requests

    47
• Interface Timing Validation

  48
  • Sample Error Detection (SED) Operation

    48
  • SED Example

    48
    • Normal Operation

      48
• Analog Interface Considerations

  49
  • Analog Modes of Operation

    49
  • Clock Input

    50
  • PLL

    50
  • Voltage Reference

    51
  • Analog Outputs

    51
    • Equivalent DAC Output and Transfer Function

      51
    • Peak DAC Output Power Capability

      52
    • Output Stage Configuration

      52
  • Start-Up Sequence

    54
• Device Configuration Registers

  55
  • Device Configuration Register Map

    55
  • Device Configuration Register Descriptions

    56
    • SPI Communications Control Register

      56
    • Power Control Register

      56
    • Interrupt Enable Register 0

      57
    • Interrupt Enable Register 1

      57
    • Interrupt Status Register 0

      57
    • Interrupt Status Register1

      58
    • Frame Pin Usage Register

      58
    • Reserved_0 Register

      58
    • Data Receiver Control 0 Register

      58
    • Data Receiver Control 1 Register

      59
    • Data Receiver Control 2 Register

      59
    • Data Receiver Control 3 Register

      59
    • Data Receiver Status 0 Register

      59
    • FIFO Control Register

      60
    • FIFO Offset Register

      60
    • FIFO Thermometer for Phase 0 Status Register

      60
    • FIFO Thermometer for Phase 1 Status Register

      60
    • FIFO Thermometer for Phase 2 Status Register

      60
    • FIFO Thermometer for Phase 3 Status Register

      60
    • Data Mode Control Register

      61
    • Decoder Control (Program Thermometer Type) Register

      61
    • Sync Control Register

      61
    • Full-Scale Current Adjust (Lower) Register

      61
    • Full-Scale Current Adjust (Upper) Register

      61
    • Analog Control 1 Register

      62
    • Analog Control 2 Register

      62
    • Clock Control 1 Register

      62
    • Retimer Control 0 Register

      62
    • Retimer Control 1 Register

      62
    • Retimer Status 0 Register

      62
    • Sample Error Detection (SED) Control Register

      63
    • Sample Error Detection (SED) Data Port 0 Rising Edge Status Low Register

      63
    • Sample Error Detection (SED) Data Port 0 Rising Edge Status High Register

      63
    • Sample Error Detection (SED) Data Port 1 Rising Edge Status Low Register

      63
    • Sample Error Detection (SED) Data Port 1 Rising Edge Status High Register

      63
    • Sample Error Detection (SED) Data Port 0 Falling Edge Status Low Register

      64
    • Sample Error Detection (SED) Data Port 0 Falling Edge Status High Register

      64
    • Sample Error Detection (SED) Data Port 1 Falling Edge Status Low Register

      64
    • Sample Error Detection (SED) Data Port 1 Falling Edge Status High Register

      64
    • Parity Control Register

      64
    • Parity Rising Edge Count Register

      64
    • Parity Falling Edge Count Register

      64
    • Delay Control Register 0

      65
    • Delay Control Register 1

      65
    • Drive Strength Register

      65
    • Part ID Register

      65
• Outline Dimensions

  66
  • Ordering Guide

    66