Analog Devices AD9637 Evaluation Board AD9637-80EBZ User Manuals

Table of Contents

• Features

  1
• Applications

  1
• General Description

  1
• Functional Block Diagram

  1
• Product Highlights

  1
• Revision History

  2
• Specifications

  3
  • DC Specifications

    3
  • AC Specifications

    4
  • Digital Specifications

    5
  • Switching Specifications

    6
  • Timing Specifications

    6
    • Timing Diagrams

      7
• Absolute Maximum Ratings

  8
  • Thermal Characteristics

    8
  • ESD Caution

    8
• Pin Configuration and Function Descriptions

  9
• Typical Performance Characteristics

  11
  • AD9637-80

    11
  • AD9637-40

    14
• Equivalent Circuits

  17
• Theory of Operation

  18
  • Analog Input Considerations

    18
    • Input Common Mode

      18
    • Differential Input Configurations

      19
  • Voltage Reference

    19
    • Internal Reference Connection

      19
    • External Reference Operation

      20
  • Clock Input Considerations

    20
    • Clock Input Options

      20
    • Input Clock Divider

      21
    • Clock Duty Cycle

      21
    • Jitter Considerations

      22
  • Power Dissipation and Power-Down Mode

    22
  • Digital Outputs and Timing

    23
    • SDIO/DFS Pin

      26
    • SCLK/DTP Pin

      26
    • CSB Pin

      26
    • RBIAS Pin

      26
• Built-In Output Test Modes

  27
  • Output Test Modes

    27
• Serial Port Interface (SPI)

  28
  • Configuration Using the SPI

    28
  • Hardware Interface

    29
  • Configuration Without the SPI

    29
  • SPI Accessible Features

    29
• Memory Map

  30
  • Reading the Memory Map Register Table

    30
    • Open Locations

      30
    • Default Values

      30
    • Logic Levels

      30
    • Channel-Specific Registers

      30
  • Memory Map Register Table

    31
  • Memory Map Register Descriptions

    34
    • Device Index (Register 0x04 and Register 0x05)

      34
    • Transfer (Register 0xFF)

      34
    • Power Modes (Register 0x08)

      34
      • Bits[7:6]—Open

        34
      • Bits[1:0]—Internal Power-Down Mode

        34
    • Enhancement Control (Register 0x0C)

      34
      • Bits[7:3]—Open

        34
      • Bit 2—Chop Mode

        34
      • Bits[1:0]—Open

        34
    • Output Mode (Register 0x14)

      34
      • Bit 7—Open

        34
      • Bit 6—LVDS-ANSI/LVDS-IEEE Option

        34
      • Bits[5:3]—Open

        34
      • Bit 2—Output Invert

        34
      • Bit 1—Open

        34
      • Bit 0—Output Format

        34
    • Output Adjust (Register 0x15)

      34
      • Bits[7:6]—Open

        34
      • Bits[5:4]—Output Driver Termination

        34
      • Bits[3:1]—Open

        34
      • Bit 0—Output Drive

        34
    • Output Phase (Register 0x16)

      35
      • Bit 7—Open

        35
      • Bits[6:4]—Input Clock Phase Adjust

        35
      • Bits[3:0]—Output Clock Phase Adjust

        35
    • Resolution/Sample Rate Override (Register 0x100)

      35
    • User I/O Control 2 (Register 0x101)

      35
      • Bits[7:1]—Open

        35
      • Bit 0—SDIO Pull-Down

        35
    • User I/O Control 3 (Register 0x102)

      35
      • Bits[7:4]—Open

        35
      • Bit 3—VCM Power-Down

        35
      • Bits[2:0]—Open

        35
• Applications Information

  36
  • Design Guidelines

    36
  • Power and Ground Recommendations

    36
  • Clock Stability Considerations

    36
  • Exposed Pad Thermal Heat Slug Recommendations

    36
  • VCM

    36
  • Reference Decoupling

    36
  • SPI Port

    36
• Outline Dimensions

  37
  • Ordering Guide

    37