Analog Devices ADP1046 Evaluation Board ADP1046DC1-EVALZ User Manuals

Table of Contents

• Features

  1
• Reference Design Contents

  1
• Caution

  1
• General Description

  1
• Table of Contents

  2
• Revision History

  2
• Demo Board Specifications

  3
• Topology and Circuit Description

  4
• Advantages of interleaving

  5
• Connectors

  7
• Settings Files and EEPROM

  8
• Evaluation Board

  9
  • Equipment

    9
  • Setup

    9
  • Board Settings

    11
• Theory of Operation

  13
  • During Startup

    13
  • During Steady State

    13
• Configuring Flag Settings

  14
• PWM Settings

  15
  • Fan Control

    16
  • Dynamic Phase Shedding and Standby Power

    16
• Board Evaluation and Test Data

  17
  • Startup

    17
  • Transformer Primary Waveform

    19
  • Primary Current

    19
  • Drain Voltage and Current

    20
  • CS1 Pin Voltage and Current Balancing of Phases

    20
  • Synchronous Rectifier Peak Inverse Voltage (PIV)

    21
  • Output Ripple

    21
  • Transient Voltage

    22
    • Load Step of 0% to 25%

      22
    • Load Step of 25% to 50%

      23
    • Load Step of 50% to 75%

      24
    • Load Step of 75% to 100%

      25
  • Phase Shedding Turn-On/Off Time

    25
  • Primary Current During Load Transient

    26
    • 10 A to 20 A Load Step

      26
    • 20 A to 10 A Load Step

      26
  • Output Overcurrent Protection

    27
  • Digital Current Sharing

    27
  • Closed-Loop Frequency Response

    28
  • Efficiency

    28
  • CS1 Linearity

    28
  • ACSNS Linearity

    29
  • CS2 Linearity

    29
  • No Load Power

    29
  • Thermal Performance

    30
• Evaluation Board Schematics and Artwork

  31
  • Main Board Schematic

    31
  • Interfaces Schematic

    32
  • Daughter Card Schematic

    33
  • Main Board Layout

    34
  • Daughter Card Layout

    37
• Bill of Materials

  39
• Appendix I—Transformer Specifications

  42
• Appendix II—Output Inductor Specifications

  43
• Appendix III—Register File (ADP1046_I2SF_032011.46r)

  44
• Appendix IV—Board File (ADP1046_I2SF_032011.46b)

  47
• Related Links

  48