User ManualTable of ContentsPinout (265)27Memory bus interface28Ethernet interface MAC30General purpose I/O (GPIO)31System clock43System mode45System reset47JTAG Test48ADC49POR and battery-backed logic50Power and ground51I/O Control Module53Control and Status registers53GPIO Configuration registers55GPIO Control registers70GPIO Status registers74Memory Bus Configuration register76Working with the CPU81Instruction sets82System control processor (CP15) registers83R0: ID code and cache type status registers86R1: Control register88R2: Translation Table Base register91R3:Domain Access Control register91R4 register92R5: Fault Status registers92R6: Fault Address register93R7:Cache Operations register94R8:TLB Operations register97R9: Cache Lockdown register98R10:TLB Lockdown register101R11 and R12 registers102R13:Process ID register102R14 register104R15: Test and debug register104Jazelle(Java)104DSP105MemoryManagement Unit (MMU)105MMU faults and CPU aborts119Domain access control121Fault checking sequence122External aborts125Enabling and disabling the MMU125TLB structure126Caches and write buffer127Cache MVA and Set/Way formats130Noncachable instruction fetches133System Control Module137Bus interconnection137System bus arbiter138Address decoding141Programmable timers142General purpose timers/counters143Basic PWM function144Enhanced PWM function145Quadrature decoder function145How the quadrature decoder/counter works146Interrupt controller148Vectored interrupt controller (VIC) flow151Configurable system attributes151PLL configuration151Bootstrap initialization152System configuration registers154General Arbiter Control register158BRC0, BRC1, BRC2, and BRC3 registers158AHB Error Detect Status 1159AHB Error Detect Status 2160AHB Error Monitoring Configuration register161Timer Master Control register162Timer 0-4 Control registers164Timer 5 Control register166Timer 6-9 Control registers168Timer 6-9 High registers170Timer 6-9 Low registers171Timer 6-9 High and Low Step registers172Timer 6-9 Reload Step registers172Timer 0-9 Reload Count and Compare register173Timer 0-9 Read and Capture register174Interrupt Vector Address Register Level 31-0175Int (Interrupt) Config (Configuration) 31-0 registers175ISADDR register176Interrupt Status Active177Interrupt Status Raw178Software Watchdog Configuration178Software Watchdog Timer179Clock Configuration register180Module Reset register182Miscellaneous System Configuration and Status register184PLL Configuration register186Active Interrupt Level ID Status register187Power Management187AHB Bus Activity Status190System Memory Chip Select 0 Dynamic Memory Base and Mask registers190System Memory Chip Select 1 Dynamic Memory Base and Mask registers191System Memory Chip Select 2 Dynamic Memory Base and Mask registers192System Memory Chip Select 3 Dynamic Memory Base and Mask registers193System Memory Chip Select 0 Static Memory Base and Mask registers194System Memory Chip Select 1 Static Memory Base and Mask registers195System Memory Chip Select 2 Static Memory Base and Mask registers196System Memory Chip Select 3 Static Memory Base and Mask registers197Gen ID register198External Interrupt 0-3 Control register199RTC Module Control register200Memory Controller203Low-power operation204Memory map205Static memory controller207Static memory initialization209Static memory read control210Static memory read: Timing and parameters211Asynchronous page mode read214Asynchronous page mode read: Timing and parameters214Static memory write control216Static memory Write: Timing and parameters216Bus turnaround219Bus turnaround: Timing and parameters219Byte lane control221Address connectivity222Dynamic memory controller225SDRAM Initialization225SDRAM address and data bus interconnect228Registers230Control register232Status register234Configuration register234Dynamic Memory Control register235Dynamic Memory Refresh Timer register236Dynamic Memory Read Configuration register237Dynamic Memory Precharge Command Period register238Dynamic Memory Active to Precharge Command Period register239Dynamic Memory Self-refresh Exit Time register240Dynamic Memory Last Data Out to Active Time register240Dynamic Memory Data-in to Active Command Time register241Dynamic Memory Write Recovery Time register242Dynamic Memory Active to Active Command Period register243Dynamic Memory Auto Refresh Period register243Dynamic Memory Exit Self-refresh register244Dynamic Memory Active Bank A to Active Bank B Time register245Dynamic Memory Load Mode register to Active Command Time register246Static Memory Extended Wait register247Dynamic Memory Configuration 0-3 registers247Dynamic Memory RAS and CAS Delay 0-3 registers250StaticMemory Configuration 0-3 registers251StaticMemory Write Enable Delay 0-3 registers254Static Memory Output Enable Delay 0-3 registers255Static Memory Read Delay 0-3 registers256StaticMemory Page Mode Read Delay 0-3 registers256Static Memory Write Delay 0-3 registers257StaticMemory Turn Round Delay 0-3 registers258Ethernet Communication Module261Ethernet MAC262Station address logic (SAL)264Statistics module265Ethernet front-end module266Receive packet processor267Transmit packet processor269Ethernet slave interface273Interrupts273Resets274Multicast address filtering275Clock synchronization276Ethernet Control and Status registers277Ethernet General Control Register #1279Ethernet General Control Register #2282Ethernet General Status register283Ethernet Transmit Status register284Ethernet Receive Status register286MAC Configuration Register #1288MAC Configuration Register #2289Back-to-Back Inter-Packet-Gap register291Non Back-to-Back Inter-Packet-Gap register292Collision Window/Retry register293Maximum Frame register294MII Management Configuration register295MII Management Command register296MII Management Address register297MII Management Write Data register298MII Management Read Data register298MII Management Indicators register299Station Address registers300Station Address Filter register301RegisterHash Tables302Statistics registers303RX_A Buffer Descriptor Pointer register315RX_B Buffer Descriptor Pointer register315RX_C Buffer Descriptor Pointer register316RX_D Buffer Descriptor Pointer register316Ethernet Interrupt Status register317Ethernet Interrupt Enable register319TX Buffer Descriptor Pointer register320Transmit Recover Buffer Descriptor Pointer register321TX Error Buffer Descriptor Pointer register321TX Stall Buffer Descriptor Pointer register322RX_A Buffer Descriptor Pointer Offset register323RX_B Buffer Descriptor Pointer Offset register324RX_C Buffer Descriptor Pointer Offset register324RX_D Buffer Descriptor Pointer Offset register325Transmit Buffer Descriptor Pointer Offset register325RX Free Buffer register326Multicast Address Filter registers327Multicast Address Mask registers329Multicast Address Filter Enable register331TX Buffer Descriptor RAM332RX FIFO RAM333Sample hash table code334External DMA339DMA transfers339DMA buffer descriptor340Descriptor list processing341Peripheral DMA read access342Peripheral DMA write access343Peripheral REQ and DONE signaling344Static RAM chip select configuration345Control and Status registers346DMA Buffer Descriptor Pointer346DMA Control register347DMA Status and Interrupt Enable register350DMA Peripheral Chip Select register352AES Data Encryption/Decryption Module355AES DMA buffer descriptor356Decryption359ECB processing359CBC, CFB, OFB, and CTR processing360CCM mode360I/O Hub Module363DMA controller364Transmit DMA example367Control and status register address maps368[Module] Interrupt and FIFO Status register372[Module] DMA RX Control375[Module] DMA RX Buffer Descriptor Pointer376[Module] RX Interrupt Configuration register377[Module] Direct Mode RX Status FIFO378[Module] Direct Mode RX Data FIFO379[Module] DMA TX Control380[Module] DMA TX Buffer Descriptor Pointer381[Module] TX Interrupt Configuration register381[Module] Direct Mode TX Data FIFO382[Module] Direct Mode TX Data Last FIFO383Serial Control Module: UART385Normal mode operation386Baud rate generator387Hardware-based flow control388Character-based flow control (XON/XOFF)388Forced character transmission388ARM wakeup on character recognition389Wrapper Control and Status registers390Wrapper Configuration register391Interrupt Enable register393Interrupt Status register395Receive Character GAP Control register398Receive Buffer GAP Control register399Receive Character Match Control register399Receive Character-Based Flow Control register400Force Transmit Character Control register402ARM Wakeup Control register403Transmit Byte Count404UART Receive Buffer405UART Transmit Buffer405UART Baud Rate Divisor LSB406UART Baud Rate Divisor MSB406UART Interrupt Enable register407UART Interrupt Identification register408UART FIFO Control register409UART Line Control register409UART Modem Control register411UART Line Status register411UART Modem Status register412Serial Control Module: HDLC415Receive and transmit operations415Clocking416Bits416Data encoding417Digital phase-locked-loop (DPLL) operation: Encoding418DPLL operation: Adjustment ranges and output clocks419Normal mode operation421Wrapper and HDLC Control and Status registers422Wrapper Configuration register422Interrupt Enable register424Interrupt Status register425HDLC Data Register 1427HDLC Data Register 2427HDLC Data register 3428HDLC Control Register 1429HDLC Control Register 2429HDLC Clock Divider Low430HDLC Clock Divider High431Serial Control Module: SPI433SPI controller434SPI clocking modes435SPI clock generation436System boot-over-SPI operation436SPI Control and Status registers439SPI Configuration register439Clock Generation register440Interrupt Enable register441Interrupt Status register442SPI timing characteristics443I2C Master/Slave Interface447Physical I2C bus447I2C external addresses448I2C command interface449I2C registers450Command Transmit Data register450Status Receive Data register451Master Address register452Slave Address register453Configuration register454Interrupt Codes455Software driver456Flow charts457Real Time Clock Module459RTC configuration and status registers460RTC General Control register46012/24 Hour register461Time register462Calendar register463Time Alarm register464Calendar Alarm register465Alarm Enable register465Event Flags register466Interrupt Enable register468Interrupt Disable register469Interrupt Enable Status register470General Status register471Analog-to-Digital Converter (ADC) Module473ADC DMA procedure474ADC control and status registers475ADC Configuration register475ADC Clock Configuration register477ADC Output Registers 0-7477Timing479Electrical characteristics479DC electrical characteristics481Reset and edge sensitive input timing requirements482Memory Timing484Reset and hardware strapping timing509JTAG timing510Clock timing511Packaging513Package513Processor Dimensions514Change log517Revision B517Revision C517Size: 2.21 MBPages: 517Language: EnglishOpen manual
