Freescale Semiconductor Evaluation Kit (EVK) for the i.MX51 Applications Processor MCIMX51EXP User Manuals

Table of Contents

• i.MX51 Applications Processors for Consumer and Industrial Products

  1
• 1 Introduction

  1
  • 1.1 Ordering Information

    3
  • 1.2 Block Diagram

    4
• 2 Features

  5
  • 2.1 Special Signal Considerations

    12
• 3 IOMUX Configuration for Boot Media

  14
  • 3.1 NAND

    15
  • 3.2 SD/MMC IOMUX Pin Configuration

    15
  • 3.3 I2C IOMUX Pin Configuration

    15
  • 3.4 eCSPI/CSPI IOMUX Pin Configuration

    16
  • 3.5 Wireless External Interface Module (WEIM)

    16
  • 3.6 UART IOMUX Pin Configuration

    16
  • 3.7 USB-OTG IOMUX Pin Configuration

    16
• 4 Electrical Characteristics

  17
  • 4.1 Chip-Level Conditions

    17
    • 4.1.1 Supply Current

      21
    • 4.1.2 USB PHY Current Consumption

      23
  • 4.2 Supply Power-Up/Power-Down Requirements and Restrictions

    23
    • 4.2.1 Power-Up Sequence

      24
  • 4.3 I/O DC Parameters

    24
    • 4.3.1 GPIO/HSGPIO DC Parameters

      25
    • 4.3.2 DDR2 I/O DC Parameters

      26
    • 4.3.3 Low Voltage I/O (LVIO) DC Parameters

      26
    • 4.3.4 Ultra-High Voltage I/O (UHVIO) DC Parameters

      27
    • 4.3.5 I2C I/O DC Parameters

      29
    • 4.3.6 USBOTG Electrical DC Parameters

      29
    • 4.3.7 USB Port Electrical DC Characteristics

      30
  • 4.4 Output Buffer Impedance Characteristics

    31
    • 4.4.1 LVIO I/O Output Buffer Impedance

      31
    • 4.4.2 DDR2 Output Buffer Impedance

      32
    • 4.4.3 UHVIO Output Buffer Impedance

      33
  • 4.5 I/O AC Parameters

    35
    • 4.5.1 Slow I/O AC Parameters

      35
    • 4.5.2 Fast I/O AC Parameters

      36
    • 4.5.3 I2C AC Parameters

      36
    • 4.5.4 AC Electrical Characteristics for DDR2

      40
  • 4.6 Module Timing

    47
    • 4.6.1 Reset Timings Parameters

      47
    • 4.6.2 WDOG Reset Timing Parameters

      48
    • 4.6.3 AUDMUX Timing Parameters

      48
    • 4.6.4 Clock Amplifier Parameters (CKIH1, CKIH2)

      48
    • 4.6.5 DPLL Electrical Parameters

      49
    • 4.6.6 NAND Flash Controller (NFC) Parameters

      49
    • 4.6.7 External Interface Module (WEIM)

      54
      • 4.6.7.1 WEIM Signal Cross Reference

        54
      • 4.6.7.2 WEIM Internal Module Multiplexing

        55
      • 4.6.7.3 General WEIM Timing-Synchronous Mode

        56
      • 4.6.7.4 Examples of WEIM Synchronous Accesses

        58
      • 4.6.7.5 General WEIM Timing-Asynchronous Mode

        60
    • 4.6.8 SDRAM Controller Timing Parameters

      66
      • 4.6.8.1 Mobile DDR SDRAM Timing Parameters

        66
    • 4.6.9 DDR2 SDRAM Specific Parameters

      69
  • 4.7 External Peripheral Interfaces

    74
    • 4.7.1 CSPI Timing Parameters

      74
      • 4.7.1.1 CSPI Master Mode Timing

        74
      • 4.7.1.2 CSPI Slave Mode Timing

        75
    • 4.7.2 eCSPI Timing Parameters

      76
      • 4.7.2.1 eCSPI Master Mode Timing

        76
      • 4.7.2.2 eCSPI Slave Mode Timing

        77
    • 4.7.3 eSDHCv2 Timing Parameters

      78
    • 4.7.4 FEC AC Timing Parameters

      79
      • 4.7.4.1 MII Receive Signal Timing

        79
      • 4.7.4.2 MII Transmit Signal Timing

        80
      • 4.7.4.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

        81
      • 4.7.4.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

        81
    • 4.7.5 Frequency Pre-Multiplier (FPM) Electrical Parameters (CKIL)

      82
    • 4.7.6 High-Speed I2C (HS-I2C) Timing Parameters

      82
      • 4.7.6.1 Standard and Fast Mode Timing Parameters

        83
      • 4.7.6.2 High-Speed Mode Timing Parameters

        84
    • 4.7.7 I2C Module Timing Parameters

      85
    • 4.7.8 Image Processing Unit (IPU) Module Parameters

      86
      • 4.7.8.1 Sensor Interface Timings

        86
      • 4.7.8.2 Electrical Characteristics

        87
      • 4.7.8.3 IPU Display Interface Signal Mapping

        88
      • 4.7.8.4 IPU Display Interface Timing

        91
      • 4.7.8.5 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

        91
      • 4.7.8.6 Interface to a TV Encoder

        97
      • 4.7.8.7 Asynchronous Interfaces

        100
      • 4.7.8.8 Standard Serial Interfaces

        109
    • 4.7.9 1-Wire Timing Parameters

      115
    • 4.7.10 Pulse Width Modulator (PWM) Timing Parameters

      116
    • 4.7.11 P-ATA Timing Parameters

      117
      • 4.7.11.1 PIO Mode Read Timing

        120
      • 4.7.11.2 Ultra DMA (UDMA) Input Timing

        123
      • 4.7.11.3 UDMA Output Timing

        125
    • 4.7.12 SIM (Subscriber Identification Module) Timing

      127
      • 4.7.12.1 Reset Sequence

        128
      • 4.7.12.2 Power Down Sequence

        129
    • 4.7.13 SCAN JTAG Controller (SJC) Timing Parameters

      131
    • 4.7.14 SPDIF Timing Parameters

      133
    • 4.7.15 SSI Timing Parameters

      133
      • 4.7.15.1 SSI Transmitter Timing with Internal Clock

        134
      • 4.7.15.2 SSI Receiver Timing with Internal Clock

        136
      • 4.7.15.3 SSI Transmitter Timing with External Clock

        138
      • 4.7.15.4 SSI Receiver Timing with External Clock

        140
    • 4.7.16 UART

      141
      • 4.7.16.1 UART Electrical

        141
    • 4.7.17 USBOH3 Parameters

      144
      • 4.7.17.1 USB Serial Interface

        144
    • 4.7.18 USB Parallel Interface Timing

      151
    • 4.7.19 USB PHY Parameters

      152
      • 4.7.19.1 USB PHY AC Parameters

        152
      • 4.7.19.2 USB PHY Additional Electrical Parameters

        152
      • 4.7.19.3 USB PHY System Clocking (SYSCLK)

        152
      • 4.7.19.4 USB PHY Voltage Thresholds

        153
• 5 Package Information and Contact Assignments

  153
  • 5.1 13 x 13 mm Package Information

    153
    • 5.1.1 BGA-Case 2058 13 x 13 mm, 0.5 mm Pitch

      154
      • 5.1.1.1 13 x 13 mm Package Drawing Notes

        154
    • 5.1.2 13 x 13 mm, 0.5 Pitch Ball Assignment Lists

      155
      • 5.1.2.1 13 x 13 mm Ball Contact Assignments

        155
      • 5.1.2.2 13 x 13 mm Signal Assignments, Power Rails, and I/O

        157
      • 5.1.2.3 13 x 13 mm No Connect Assignments

        169
    • 5.1.3 13 x 13 mm Ball Map

      173
  • 5.2 19 x 19 mm Package Information

    173
    • 5.2.1 BGA-Case 2017, 19 x 19 mm, 0.8 mm Pitch

      174
      • 5.2.1.1 19 x 19 mm Package Drawing Notes

        175
    • 5.2.2 19 x 19 mm Signal Assignments, Power Rails, and I/O

      175
      • 5.2.2.1 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments

        175
      • 5.2.2.2 19 x 19 mm, Signal Assignments, Power Rails, and I/O

        177
      • 5.2.2.3 Fuse Override Considerations

        189
    • 5.2.3 19 x 19 Ball Map

      190
  • 5.3 13 ¥ 13 mm, 0.5 Pitch Ball Map

    191
  • 5.4 19 x 19 mm, 0.8 Pitch Ball Map

    195
• 6 Revision History

  199