User Manual (MC56F8006DEMO)Table of ContentsPreface3Introduction41.1 Cautionary Notes41.2 Terminology41.3 Features5Technical Summary62.1 Options62.1.1 JP1 — IRQ_SW1 Input Select62.1.2 JP2 — IRQ_SW2 Input Select62.1.3 JP3 — +3.3 V Enable62.1.4 JP4 — +Vopt Enable62.1.5 TX_EN and RX_EN Option Jumpers62.2.1 LED1 — 6 Indicators62.2.2 IRQ_SW1 and IRQ_SW2 Push Switches72.2.3 Y2 Crystal Reference72.3.1 J4 — USB port72.3.2 PWR Jack72.3.3 +3.3 V and GND Test Points72.3.4 COM Port72.3.5 JTAG / EOnCE Port82.4 J1 — MC56F8006 I/O Ports92.5 J2 — MC56F8006 I/O Port E9MC56F8006DEMO Schematics10MC56F8006DEMO Bill of Materials11Size: 3.19 MBPages: 13Language: EnglishOpen manual
Data Sheet (MC56F8006DEMO)Table of Contents1 MC56F8006/MC56F8002 Family Configuration32 Block Diagram43 Overview43.1 56F8006/56F8002 Features43.1.1 Core43.1.2 Operation Range53.1.3 Memory53.1.4 Interrupt Controller53.1.5 Peripheral Highlights53.1.6 Power Saving Features83.2 Award-Winning Development Environment83.3 Architecture Block Diagram93.4 Product Documentation114 Signal/Connection Descriptions114.1 Introduction114.2 Pin Assignment134.3 56F8006/56F8002 Signal Pins175 Memory Maps295.1 Introduction295.2 Program Map295.3 Data Map305.4 Interrupt Vector Table and Reset Vector315.5 Peripheral Memory-Mapped Registers325.6 EOnCE Memory Map336 General System Control Information346.1 Overview346.2 Power Pins346.3 Reset346.4 On-chip Clock Synthesis346.4.1 Internal Clock Source356.4.2 Crystal Oscillator/Ceramic Resonator356.4.3 External Clock Input - Crystal Oscillator Option366.4.4 Alternate External Clock Input376.5 Interrupt Controller376.6 System Integration Module (SIM)376.7 PWM, PDB, PGA, and ADC Connections386.8 Joint Test Action Group (JTAG)/Enhanced On-Chip Emulator (EOnCE)397 Security Features397.1 Operation with Security Enabled407.2 Flash Access Lock and Unlock Mechanisms407.2.1 Disabling EOnCE Access407.2.2 Flash Lockout Recovery Using JTAG407.2.3 Flash Lockout Recovery Using CodeWarrior407.2.4 Flash Lockout Recovery without Mass Erase417.2.4.1 Without Presenting Back Door Access Keys to the Flash Unit417.2.4.2 Presenting Back Door Access Key to the Flash Unit417.3 Product Analysis418 Specifications418.1 General Characteristics418.2 Absolute Maximum Ratings428.2.1 ESD Protection and Latch-Up Immunity428.3 Thermal Characteristics438.4 Recommended Operating Conditions458.5 DC Electrical Characteristics468.6 Supply Current Characteristics518.7 Flash Memory Characteristics538.8 External Clock Operation Timing538.9 Phase Locked Loop Timing548.10 Relaxation Oscillator Timing548.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing568.12 External Oscillator (XOSC) Characteristics568.13 AC Electrical Characteristics578.13.1 Serial Peripheral Interface (SPI) Timing588.13.2 Serial Communication Interface (SCI) Timing618.13.3 Inter-Integrated Circuit Interface (I2C) Timing628.13.4 JTAG Timing638.13.5 Dual Timer Timing648.14 COP Specifications658.15 PGA Specifications658.16 ADC Specifications668.17 HSCMP Specifications688.18 Optimize Power Consumption689 Design Considerations709.1 Thermal Design Considerations709.2 Electrical Design Considerations719.3 Ordering Information7210 Package Mechanical Outline Drawings7310.1 28-pin SOIC Package7310.2 32-pin LQFP7610.3 48-pin LQFP7910.4 32-Pin PSDIP8111 Revision History83Appendix A Interrupt Vector Table83Appendix B Peripheral Register Memory Map and Reset Value86MC56F8006/MC56F8002 Digital Signal Controller1Size: 2.03 MBPages: 106Language: EnglishOpen manual
