Fujifilm Xeon DP User Manuals

Table of Contents

• 1.0 Introduction

  9
  • 1.1 Terminology

    10
  • 1.2 References

    12
  • 1.3 State of Data

    12
• 2.0 Electrical Specifications

  13
  • 2.1 Power and Ground Pins

    13
  • 2.2 Decoupling Guidelines

    13
    • 2.2.1 VCC Decoupling

      13
    • 2.2.2 VTT Decoupling

      13
    • 2.2.3 Front Side Bus AGTL+ Decoupling

      14
  • 2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

    14
    • 2.3.1 Front Side Bus Frequency Select Signals (BSEL[1:0])

      14
    • 2.3.2 Phase Lock Loop (PLL) and Filter

      15
  • 2.4 Voltage Identification (VID)

    16
  • 2.5 Reserved or Unused Pins

    18
  • 2.6 Front Side Bus Signal Groups

    19
  • 2.7 GTL+ Asynchronous and AGTL+ Asynchronous Signals

    22
  • 2.8 Test Access Port (TAP) Connection

    22
  • 2.9 Mixing Processors

    22
  • 2.10 Absolute Maximum and Minimum Ratings

    23
  • 2.11 Processor DC Specifications

    24
    • 2.11.1 VCC Overshoot Specification

      30
    • 2.11.2 Die Voltage Validation

      31
• 3.0 Mechanical Specifications

  35
  • 3.1 Package Mechanical Drawings

    35
  • 3.2 Processor Component Keepout Zones

    38
  • 3.3 Package Loading Specifications

    38
  • 3.4 Package Handling Guidelines

    39
  • 3.5 Package Insertion Specifications

    39
  • 3.6 Processor Mass Specifications

    39
  • 3.7 Processor Materials

    39
  • 3.8 Processor Markings

    40
  • 3.9 Processor Pinout Coordinates

    41
• 4.0 Signal Definitions

  43
  • 4.1 Signal Definitions

    43
• 5.0 Pin List

  53
  • 5.1 Low Voltage Intel® Xeon™ Processor with 800 MHz System Bus Pin Assignments

    53
    • 5.1.1 Pin Listing by Pin Name

      54
    • 5.1.2 Pin Listing by Pin Number

      62
• 6.0 Thermal Specifications

  71
  • 6.1 Package Thermal Specifications

    71
    • 6.1.1 Thermal Specifications

      71
    • 6.1.2 Thermal Metrology

      74
  • 6.2 Processor Thermal Features

    74
    • 6.2.1 Thermal Monitor

      74
    • 6.2.2 On-Demand Mode

      75
    • 6.2.3 PROCHOT# Signal Pin

      75
    • 6.2.4 FORCEPR# Signal Pin

      75
    • 6.2.5 THERMTRIP# Signal Pin

      76
    • 6.2.6 TCONTROL and Fan Speed Reduction

      76
    • 6.2.7 Thermal Diode

      76
• 7.0 Features

  79
  • 7.1 Power-On Configuration Options

    79
  • 7.2 Clock Control and Low Power States

    79
    • 7.2.1 Normal State

      80
    • 7.2.2 HALT Power-Down State

      80
    • 7.2.3 Stop-Grant State

      82
    • 7.2.4 HALT Snoop State or Snoop State

      82
    • 7.2.5 Sleep State

      83
• 8.0 Debug Tools Specifications

  85
  • 8.1 Debug Port System Requirements

    85
  • 8.2 Target System Implementation

    85
    • 8.2.1 System Implementation

      85
  • 8.3 Logic Analyzer Interface (LAI)

    85
    • 8.3.1 Mechanical Considerations

      86
    • 8.3.2 Electrical Considerations

      86