HP Intel Xeon W3550 User Manuals

Table of Contents

• 1 Introduction

  11
  • 1.1 Terminology

    11
    • 1.1.1 Processor Terminology

      11
  • 1.2 References

    13
• 2 Register Description

  15
  • 2.1 Register Terminology

    15
  • 2.2 Platform Configuration Structure

    16
  • 2.3 Device Mapping

    17
  • 2.4 Detailed Configuration Space Maps

    18
  • 2.5 PCI Standard Registers

    36
    • 2.5.1 VID - Vendor Identification Register

      36
    • 2.5.2 DID - Device Identification Register

      36
    • 2.5.3 RID - Revision Identification Register

      37
    • 2.5.4 CCR - Class Code Register

      37
    • 2.5.5 HDR - Header Type Register

      38
    • 2.5.6 SID/SVID - Subsystem Identity/Subsystem Vendor Identification Register

      38
    • 2.5.7 PCICMD - Command Register

      39
    • 2.5.8 PCISTS - PCI Status Register

      40
  • 2.6 SAD - System Address Decoder Registers

    41
    • 2.6.1 SAD_PAM0123

      41
    • 2.6.2 SAD_PAM456

      43
    • 2.6.3 SAD_HEN

      44
    • 2.6.4 SAD_SMRAM

      44
    • 2.6.5 SAD_PCIEXBAR

      45
    • 2.6.6 SAD_DRAM_RULE_0, SAD_DRAM_RULE_1, SAD_DRAM_RULE_2, SAD_DRAM_RULE_3 SAD_DRAM_RULE_4, SAD_DRAM_RULE_5 SAD_DRAM_RULE_6, SAD_DRAM_RULE_7

      46
    • 2.6.7 SAD_INTERLEAVE_LIST_0, SAD_INTERLEAVE_LIST_1 SAD_INTERLEAVE_LIST_2, SAD_INTERLEAVE_LIST_3 SAD_INTERLEAVE_LIST_4, SAD_INTERLEAVE_LIST_5 SAD_INTERLEAVE_LIST_6, SAD_INTERLEAVE_LIST_7

      46
  • 2.7 Intel® QuickPath Interconnect Link Registers

    47
    • 2.7.1 QPI_QPILCL_L0, QPI_QPILCL_L1

      47
  • 2.8 Integrated Memory Controller Control Registers

    48
    • 2.8.1 MC_CONTROL

      48
    • 2.8.2 MC_STATUS

      49
    • 2.8.3 MC_SMI_SPARE_DIMM_ERROR_STATUS

      50
    • 2.8.4 MC_SMI_SPARE_CNTRL

      51
    • 2.8.5 MC_RESET_CONTROL

      51
    • 2.8.6 MC_CHANNEL_MAPPER

      52
    • 2.8.7 MC_MAX_DOD

      53
    • 2.8.8 MC_RD_CRDT_INIT

      54
    • 2.8.9 MC_CRDT_WR_THLD

      55
    • 2.8.10 MC_SCRUBADDR_LO

      55
    • 2.8.11 MC_SCRUBADDR_HI

      56
  • 2.9 TAD - Target Address Decoder Registers

    57
    • 2.9.1 TAD_DRAM_RULE_0, TAD_DRAM_RULE_1 TAD_DRAM_RULE_2, TAD_DRAM_RULE_3 TAD_DRAM_RULE_4, TAD_DRAM_RULE_5 TAD_DRAM_RULE_6, TAD_DRAM_RULE_7

      57
    • 2.9.2 TAD_INTERLEAVE_LIST_0, TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6, TAD_INTERLEAVE_LIST_7

      58
  • 2.10 Integrated Memory Controller Channel Control Registers

    59
    • 2.10.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD MC_CHANNEL_2_DIMM_RESET_CMD

      59
    • 2.10.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD MC_CHANNEL_2_DIMM_INIT_CMD

      60
    • 2.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS MC_CHANNEL_2_DIMM_INIT_PARAMS

      61
    • 2.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS MC_CHANNEL_2_DIMM_INIT_STATUS

      62
    • 2.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD MC_CHANNEL_2_DDR3CMD

      63
    • 2.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT

      64
    • 2.10.7 MC_CHANNEL_0_MRS_VALUE_0_1 MC_CHANNEL_1_MRS_VALUE_0_1 MC_CHANNEL_2_MRS_VALUE_0_1

      64
    • 2.10.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2 MC_CHANNEL_2_MRS_VALUE_2

      65
    • 2.10.9 MC_CHANNEL_0_RANK_PRESENT MC_CHANNEL_1_RANK_PRESENT MC_CHANNEL_2_RANK_PRESENT

      65
    • 2.10.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A MC_CHANNEL_2_RANK_TIMING_A

      66
    • 2.10.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B MC_CHANNEL_2_RANK_TIMING_B

      69
    • 2.10.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING MC_CHANNEL_2_BANK_TIMING

      70
    • 2.10.13 MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_1_REFRESH_TIMING MC_CHANNEL_2_REFRESH_TIMING

      70
    • 2.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING

      71
    • 2.10.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING MC_CHANNEL_2_ZQ_TIMING

      71
    • 2.10.16 MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_1_RCOMP_PARAMS MC_CHANNEL_2_RCOMP_PARAMS

      72
    • 2.10.17 MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS1 MC_CHANNEL_2_ODT_PARAMS1

      72
    • 2.10.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2 MC_CHANNEL_2_ODT_PARAMS2

      73
    • 2.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD

      73
    • 2.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD

      74
    • 2.10.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR

      74
    • 2.10.22 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR

      74
    • 2.10.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS MC_CHANNEL_2_WAQ_PARAMS

      75
    • 2.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS

      76
    • 2.10.25 MC_CHANNEL_0_MAINTENANCE_OPS MC_CHANNEL_1_MAINTENANCE_OPS MC_CHANNEL_2_MAINTENANCE_OPS

      76
    • 2.10.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS MC_CHANNEL_2_TX_BG_SETTINGS

      77
    • 2.10.27 MC_CHANNEL_0_RX_BGF_SETTINGS MC_CHANNEL_1_RX_BGF_SETTINGS MC_CHANNEL_2_RX_BGF_SETTINGS

      77
    • 2.10.28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS MC_CHANNEL_2_EW_BGF_SETTINGS

      78
    • 2.10.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS

      78
    • 2.10.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY MC_CHANNEL_1_ROUND_TRIP_LATENCY MC_CHANNEL_2_ROUND_TRIP_LATENCY

      78
    • 2.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS1 MC_CHANNEL_2_PAGETABLE_PARAMS1

      79
    • 2.10.32 MC_CHANNEL_0_PAGETABLE_PARAMS2 MC_CHANNEL_1_PAGETABLE_PARAMS2 MC_CHANNEL_2_PAGETABLE_PARAMS2

      79
    • 2.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH2

      80
    • 2.10.34 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0 MC_TX_BG_CMD_OFFSET_SETTINGS_CH1 MC_TX_BG_CMD_OFFSET_SETTINGS_CH2

      80
    • 2.10.35 MC_TX_BG_DATA_OFFSET_SETTINGS_CH0 MC_TX_BG_DATA_OFFSET_SETTINGS_CH1 MC_TX_BG_DATA_OFFSET_SETTINGS_CH2

      80
    • 2.10.36 MC_CHANNEL_0_ADDR_MATCH MC_CHANNEL_1_ADDR_MATCH MC_CHANNEL_2_ADDR_MATCH

      81
    • 2.10.37 MC_CHANNEL_0_ECC_ERROR_MASK MC_CHANNEL_1_ECC_ERROR_MASK MC_CHANNEL_2_ECC_ERROR_MASK

      82
    • 2.10.38 MC_CHANNEL_0_ECC_ERROR_INJECT MC_CHANNEL_1_ECC_ERROR_INJECT MC_CHANNEL_2_ECC_ERROR_INJECT

      82
    • 2.10.39 Error Injection Implementation

      83
  • 2.11 Integrated Memory Controller Channel Address Registers

    84
    • 2.11.1 MC_DOD_CH0_0, MC_DOD_CH0_1, MC_DOD_CH0_2

      84
    • 2.11.2 MC_DOD_CH1_0, MC_DOD_CH1_1, MC_DOD_CH1_2

      85
    • 2.11.3 MC_DOD_CH2_0, MC_DOD_CH2_1, MC_DOD_CH2_2

      86
    • 2.11.4 MC_SAG_CH0_0, MC_SAG_CH0_1, MC_SAG_CH0_2 MC_SAG_CH0_3, MC_SAG_CH0_4, MC_SAG_CH0_5 MC_SAG_CH0_6, MC_SAG_CH0_7, MC_SAG_CH1_...

      87
  • 2.12 Integrated Memory Controller Channel Rank Registers

    88
    • 2.12.1 MC_RIR_LIMIT_CH0_0, MC_RIR_LIMIT_CH0_1 MC_RIR_LIMIT_CH0_2, MC_RIR_LIMIT_CH0_3 MC_RIR_LIMIT_CH0_4, MC_RIR_LIMIT_CH0_5 MC_R...

      88
    • 2.12.2 MC_RIR_WAY_CH0_0, MC_RIR_WAY_CH0_1 MC_RIR_WAY_CH0_2, MC_RIR_WAY_CH0_3 MC_RIR_WAY_CH0_4, MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6...

      89
    • 2.12.3 MC_RIR_WAY_CH1_0, MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2, MC_RIR_WAY_CH1_3 MC_RIR_WAY_CH1_4, MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6...

      90
    • 2.12.4 MC_RIR_WAY_CH2_0, MC_RIR_WAY_CH2_1 MC_RIR_WAY_CH2_2, MC_RIR_WAY_CH2_3 MC_RIR_WAY_CH2_4, MC_RIR_WAY_CH2_5 MC_RIR_WAY_CH2_6...

      91
  • 2.13 Memory Thermal Control

    92
    • 2.13.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1 MC_THERMAL_CONTROL2

      92
    • 2.13.2 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS2

      92
    • 2.13.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1 MC_THERMAL_DEFEATURE2

      93
    • 2.13.4 MC_THERMAL_PARAMS_A0 MC_THERMAL_PARAMS_A1 MC_THERMAL_PARAMS_A2

      93
    • 2.13.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1 MC_THERMAL_PARAMS_B2

      94
    • 2.13.6 MC_COOLING_COEF0 MC_COOLING_COEF1 MC_COOLING_COEF2

      94
    • 2.13.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1 MC_CLOSED_LOOP2

      95
    • 2.13.8 MC_THROTTLE_OFFSET0 MC_THROTTLE_OFFSET1 MC_THROTTLE_OFFSET2

      95
    • 2.13.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP1 MC_RANK_VIRTUAL_TEMP2

      96
    • 2.13.10 MC_DDR_THERM_COMMAND0 MC_DDR_THERM_COMMAND1 MC_DDR_THERM_COMMAND2

      96
    • 2.13.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS1 MC_DDR_THERM_STATUS2

      97
  • 2.14 Integrated Memory Controller Miscellaneous Registers

    97
    • 2.14.1 MC_DIMM_CLK_RATIO_STATUS

      97
    • 2.14.2 MC_DIMM_CLK_RATIO

      98