IBM Xeon 5140 User Manuals

Table of Contents

• Dual-Core Intel® Xeon® Processor 5100 Series

  1
  • Contents

    3
    • Figures

      4
    • Table

      5
  • Revision History

    7
• Features

  9
• 1 Introduction

  11
  • 1.1 Terminology

    12
  • 1.2 State of Data

    14
  • 1.3 References

    14
• 2 Electrical Specifications

  17
  • 2.1 Front Side Bus and GTLREF

    17
  • 2.2 Power and Ground Lands

    17
  • 2.3 Decoupling Guidelines

    18
    • 2.3.1 VCC Decoupling

      18
    • 2.3.2 VTT Decoupling

      18
    • 2.3.3 Front Side Bus AGTL+ Decoupling

      18
  • 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

    18
    • 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])

      19
    • 2.4.2 PLL Power Supply

      20
  • 2.5 Voltage Identification (VID)

    20
  • 2.6 Reserved or Unused Signals

    23
  • 2.7 Front Side Bus Signal Groups

    24
  • 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals

    25
  • 2.9 Test Access Port (TAP) Connection

    25
  • 2.10 Platform Environmental Control Interface (PECI) DC Specifications

    26
    • 2.10.1 DC Characteristics

      26
    • 2.10.2 Input Device Hysteresis

      27
  • 2.11 Mixing Processors

    27
  • 2.12 Absolute Maximum and Minimum Ratings

    27
  • 2.13 Processor DC Specifications

    29
    • 2.13.1 VCC Overshoot Specification

      35
    • 2.13.2 Die Voltage Validation

      36
• 3 Mechanical Specifications

  37
  • 3.1 Package Mechanical Drawings

    37
  • 3.2 Processor Component Keepout Zones

    41
  • 3.3 Package Loading Specifications

    41
  • 3.4 Package Handling Guidelines

    42
  • 3.5 Package Insertion Specifications

    42
  • 3.6 Processor Mass Specifications

    42
  • 3.7 Processor Materials

    43
  • 3.8 Processor Land Coordinates

    43
• 4 Land Listing

  45
  • 4.1 Dual-Core Intel® Xeon® Processor 5100 Series Pin Assignments

    45
    • 4.1.1 Land Listing by Land Name

      45
    • 4.1.2 Land Listing by Land Number

      55
• 5 Signal Definitions

  65
  • 5.1 Signal Definitions

    65
• 6 Thermal Specifications

  73
  • 6.1 Package Thermal Specifications

    73
    • 6.1.1 Thermal Specifications

      73
    • 6.1.2 Thermal Metrology

      81
  • 6.2 Processor Thermal Features

    82
    • 6.2.1 Thermal Monitor Features

      82
    • 6.2.2 On-Demand Mode

      84
    • 6.2.3 PROCHOT# Signal

      85
    • 6.2.4 FORCEPR# Signal

      85
    • 6.2.5 THERMTRIP# Signal

      86
  • 6.3 Platform Environment Control Interface (PECI)

    86
    • 6.3.1 Introduction

      86
    • 6.3.2 PECI Specifications

      88
• 7 Features

  91
  • 7.1 Power-On Configuration Options

    91
  • 7.2 Clock Control and Low Power States

    91
    • 7.2.1 Normal State

      92
    • 7.2.2 HALT or Extended HALT State

      92
    • 7.2.3 Stop-Grant State

      94
    • 7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State

      95
  • 7.3 Enhanced Intel SpeedStep® Technology

    95
• 8 Boxed Processor Specifications

  97
  • 8.1 Introduction

    97
  • 8.2 Mechanical Specifications

    99
    • 8.2.1 Boxed Processor Heat Sink Dimensions (CEK)

      99
    • 8.2.2 Boxed Processor Heat Sink Weight

      107
    • 8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)

      107
  • 8.3 Electrical Requirements

    107
    • 8.3.1 Fan Power Supply (Active CEK)

      107
    • 8.3.2 Boxed Processor Cooling Requirements

      108
  • 8.4 Boxed Processor Contents

    109
• 9 Debug Tools Specifications

  111
  • 9.1 Debug Port System Requirements

    111
  • 9.2 Target System Implementation

    111
    • 9.2.1 System Implementation

      111
  • 9.3 Logic Analyzer Interface (LAI)

    111
    • 9.3.1 Mechanical Considerations

      112
    • 9.3.2 Electrical Considerations

      112