User ManualTable of ContentsContents3Unpacking and Special Handling Instructions8Revision History9Three Year Limited Warranty101.0 ICP-CM CPU131.01 Interfacing141.02 Peripherals141.03 Software141.04 Graphics141.1 Specifications151.2 Functional Overview17Figure 1.20 ICP-CM Interfacing17Figure 1.21 ICP-CM Board Overview181.3 Software191.31 Windows XP (Professional / Embedded)191.32 Windows 2000 (Professional)191.33 Linux191.34 VentureCom191.35 Windows CE201.36 VxWorks201.37 OS-9 x86201.38 QNX201.39 Jbed201.4 Hardware211.41 Block Diagram21Figure 1.41 Block Diagram211.42 Connector Location22Figure 1.42 Connector Locations221.43 Connector Description22Table 1.43 Connector Description22Table 1.43 Continued231.44 Front-Panel Features23Table 1.44 Front Panels23Figure 1.44 Front-Panel Options241.45 Interface Positions25Figure 1.45 Interfaces251.46 Construction - 4HP Standard CPU26Figure 1.46 Construction of CPU with Heat-Sink Assembly261.47 Construction - 8HP Standard CPU27Figure 1.47 Construction of CPU with Heat-Sink Assembly271.48 Construction - 8HP Standard CPU with AGP28Figure 1.48 Construction of CPU with Heat-Sink Assembly281.49 Power Requirements29Table 1.49 ICP-CM Power Reqirements291.50 Power Consumption30Figure 1.50 ICP-CM Power Consumption301.51 Thermal Considerations31Table 1.51 ICP-CM Airflow Requirements312.0 Memory Map34Figure 2.00 System Architecture342.1 I/O Mapped Peripherals36Table 2.10 Legacy I/O Map (ISA Compatible)36Table 2.10 Legacy I/O Map (ISA Compatible) Contd.372.2 Memory Mapped Peripherals382.3 Interrupt Routing38Table 2.30 PC-AT Interrupt Definitions392.4 DMA Channel Descriptions39Table 2.40 DMA Channel Description392.5 Inova CM SMB Devices40Table 2.50 SMB Devices402.6 Inova CM PCI Device List41Table 2.60 Legacy I/O Map (ISA Compatible)412.7 Interrupt Configuration42Table 2.70 CompactPCI Bus Interrupts422.8 Timer / Counter432.9 Watchdog433.0 CompactPCI J1/J2 Connectors463.01 CompactPCI Connector Naming46Figure 3.01 Naming Convention as per PICMG 2.0 R3.0 Specification463.02 CompactPCI J1 Connector46Figure 3.02 J1- 32-Bit CompactPCI Bus Interface Connector463.03 ICP-PM Connector J1 and J246Table 3.03 32-Bit CompactPCI J1 Pin Assignment47Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. with Rear I/O (D))48Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. - with Rear I/O (D)) - Contd.49Table 3.05 Inova’s ICP-CM Rear I/O J2 (CPU) Integration503.1 CompactPCI Backplane51Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot523.2 Interfaces533.21 J6 & J7 Ethernet53Figure 3.21 RJ45 Pinout53Table 3.21 Ethernet Standards & Connector Signals533.22 J17 VGA Interface543.23 Graphic Features (Chipset)54Table 3.23a highlights just some of the features of the standard integrated video controller.54Figure 3.23 High-Density D-Sub VGA Interface Pinout55Table 3.23b Video Output Connector Signals553.24 J19 USB Interface56Figure 3.24 USB Interface Pinout56Table 3.24 USB Connector Signals563.25 J10 Hot-Swap Interface573.26 SW1 Reset Button573.27 J9 CompactFlash Interface573.28 Connecting the CM to the Inova ICP-HD3(-ND)573.29 Connecting the CM to the Inova IPB-FPE12573.30 Connecting the CM to a Slim-Line Floppy-Disk57A1 ICP-HD-3(-ND) CPU Extension60A1.1 ICP-HD-3(-ND) Front-Panels (8HP or 12HP)60Figure A1.1 ICP-HD-3(-ND) CPU Front-Panels60A1.2 IDE Carrier Board ICP-HD-3(-ND)61Figure A1.2 Interface Location of the ICP-HD-3(-ND) Module61Table A1.2 Interface Description of the ICP-HD-3(-ND) Module62A2 ICP-HD-3(-ND) Interfaces63A2.1 COM1 & COM2 Interfaces63Figure A2.1 COM1 & COM2 Interface Pinout63Table A2.1 COM1 & COM2 Connector Signals63A2.2 Mouse & Keyboard Interfaces64Figure A2.2 Mouse & Keyboard Interface Pinout64Table A2.2 Mouse & Keyboard Connector Signals64Table A2.3 USB Connector Signals65A2.3 USB 2.0 Interfaces65Figure A2.3 USB Interface Pinout65A2.4 EIDE Interface66A2.5 Slim-Line Floppy Disk Interface66B1 IPB-FPE12 CPU Extension68B1.1 J13 Interface for LPT168B1.2 IPB-FPE12 Front-Panel (4HP or 12HP)68Figure B1.2 IPB-FPE12 Stand-Alone or Integrated with CPU68B1.3 LPT1 Piggyback69Figure B1.3 LPT1 Piggyback Board IPB-FPE1269Table B1.3 IPB-FPE12 Connector Description70B1.4 LPT1 Interface70Figure B1.4 LPT1 Interface Pinout70Table B1.4 LPT1 Connector Signals70C1 ITM-RIO CPU Extension72C1.1 ITM-RIO-D Configurations72Table C1.10 Valid Rear I/O Configurations72Table C1.11 Rear I/O Module Functionality72C1.2 ITM-RIO Rear-Panels (4HP or 8HP)73Figure C1.2 The rear Panels of the Inova ITM-RIO-D-x73C1.3 ITM-RIO-D-x Transition Module74Figure C1.3 Inova Rear I/O Transition Module ITM-RIO-D-x74Table C1.3 ITM-RIO-D-x Connector Description75C1.4 COM1 & COM2 Interfaces76Figure C1.4 COM1 & COM2 Interface Pinout76Table C1.4 COM1 & COM2 Connector Signals76C1.5 LPT1 Interface77Figure C1.5 LPT1 Interface Pinout77Table C1.5 LPT1 Connector Signals77C1.6 Mouse & Keyboard Interfaces78Figure C1.6 Mouse & Keyboard Interface Pinout78Table C1.6 Mouse & Keyboard Connector Signals78C1.7 VGA Interface79Figure C1.7 VGA Interface Pinout79Table C1.7 Video Output Connector Signals79C1.8 Fast Ethernet Interface80Figure C1.8 Fast Ethernet Interface Pinout80Table C1.8 Fast Ethernet Connector Signals80C1.9 USB Interface (USB 4)81Figure C1.9 USB Interface Pinout81Table C1.9 USB Connector Signals81C1.10 EIDE Interface82C1.11 Slim-Line Floppy Disk Interface82C1.12 ITM-RIO(C&D)-FHLU Extension83Figure C1.12 ITM-RIO(C&D)-FHLU83D1 IPM-ATA CPU Extension86D1.1 rJ2 Interface86Figure D1.1a Dedicated IPM-ATA Backplane86D1.1 rJ2 Interfaces (Contd.)87Figure D1.1b The Complete Connection Picture87D1.2 IPM-ATA-HD88Figure D1.2 IPM-ATA-HD Board Layout88Table D1.2 IPM-ATA-HD Jumper Description (CF Socket)88D1.3 IPM-ATA-CF89Figure D1.3 IPM-ATA-CF Board Layout89Table D1.3 IPM-ATA-CF Jumper Description89D1.4 IPM-ATA-PCMCIA90Figure D1.4 IPM-ATA-PCMCIA Board Layout90Table D1.4 IPM-ATA-PCMCIA Jumper Description90D1.5 Device Compatibility91Table D1.5 Compatibility List91E1 AGP-R7000 CPU Extension94Table E1.00 AGP Piggyback Configurations94E1.1 Specifications95E1.2 J4 Interface96Figure E1.20 J4 on the Underside of the AGP-R7000 Piggyback96Table E1.20 J4 Pinout97Table E1.20 J4 Pinout - Contd.98E1.3 J3 & J5 IBP-GS-MULTILINK (TFT) Interfaces99Figure E1.30 J3 and J5 Topside Connectors for the Inova IPB-GS-MULTILINK99Table E1.30 J3 & J5 Interface Pinout100E1.4 J1 Front-Panel VGA/TMDS Interface101Figure E1.40 Standard Front-Panel VGA/TMDS Interface101Table E1.40 J1 Standard Front-Panel VGA/TMDS Pinout101Table E1.41 J2 DIP Switch Settings - Digital TMDS (PanelLink) or DVI-D102Table E1.42 J2 DIP Switch Settings - TFT (24Bit TTL/CMOS)102E1.5 Rear I/O VGA Interface103Overview Contents111.0 ICP-CM CPU131.01 Interfacing141.02 Peripherals141.03 Software141.04 Graphics141.1 Specifications151.2 Functional Overview17Figure 1.20 ICP-CM Interfacing17Figure 1.21 ICP-CM Board Overview181.3 Software191.31 Windows XP (Professional / Embedded)191.32 Windows 2000 (Professional)191.33 Linux191.34 VentureCom191.35 Windows CE201.36 VxWorks201.37 OS-9 x86201.38 QNX201.39 Jbed201.4 Hardware211.41 Block Diagram21Figure 1.41 Block Diagram211.42 Connector Location22Figure 1.42 Connector Locations221.43 Connector Description22Table 1.43 Connector Description22Table 1.43 Continued231.44 Front-Panel Features23Table 1.44 Front Panels23Figure 1.44 Front-Panel Options241.45 Interface Positions25Figure 1.45 Interfaces251.46 Construction - 4HP Standard CPU26Figure 1.46 Construction of CPU with Heat-Sink Assembly261.47 Construction - 8HP Standard CPU27Figure 1.47 Construction of CPU with Heat-Sink Assembly271.48 Construction - 8HP Standard CPU with AGP28Figure 1.48 Construction of CPU with Heat-Sink Assembly281.49 Power Requirements29Table 1.49 ICP-CM Power Reqirements291.50 Power Consumption30Figure 1.50 ICP-CM Power Consumption301.51 Thermal Considerations31Table 1.51 ICP-CM Airflow Requirements31Configuration Contents332.0 Memory Map34Figure 2.00 System Architecture342.1 I/O Mapped Peripherals36Table 2.10 Legacy I/O Map (ISA Compatible)36Table 2.10 Legacy I/O Map (ISA Compatible) Contd.372.2 Memory Mapped Peripherals382.3 Interrupt Routing38Table 2.30 PC-AT Interrupt Definitions392.4 DMA Channel Descriptions39Table 2.40 DMA Channel Description392.5 Inova CM SMB Devices40Table 2.50 SMB Devices402.6 Inova CM PCI Device List41Table 2.60 Legacy I/O Map (ISA Compatible)412.7 Interrupt Configuration42Table 2.70 CompactPCI Bus Interrupts422.8 Timer / Counter432.9 Watchdog43Interfaces Contents453.0 CompactPCI J1/J2 Connectors463.01 CompactPCI Connector Naming46Figure 3.01 Naming Convention as per PICMG 2.0 R3.0 Specification463.02 CompactPCI J1 Connector46Figure 3.02 J1- 32-Bit CompactPCI Bus Interface Connector463.03 ICP-PM Connector J1 and J246Table 3.03 32-Bit CompactPCI J1 Pin Assignment47Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. with Rear I/O (D))48Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. - with Rear I/O (D)) - Contd.49Table 3.05 Inova’s ICP-CM Rear I/O J2 (CPU) Integration503.1 CompactPCI Backplane51Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot523.2 Interfaces533.21 J6 & J7 Ethernet53Figure 3.21 RJ45 Pinout53Table 3.21 Ethernet Standards & Connector Signals533.22 J17 VGA Interface543.23 Graphic Features (Chipset)54Table 3.23a highlights just some of the features of the standard integrated video controller.54Figure 3.23 High-Density D-Sub VGA Interface Pinout55Table 3.23b Video Output Connector Signals553.24 J19 USB Interface56Figure 3.24 USB Interface Pinout56Table 3.24 USB Connector Signals563.25 J10 Hot-Swap Interface573.26 SW1 Reset Button573.27 J9 CompactFlash Interface573.28 Connecting the CM to the Inova ICP-HD3(-ND)573.29 Connecting the CM to the Inova IPB-FPE12573.30 Connecting the CM to a Slim-Line Floppy-Disk57ICP-HD-3 Contents59A1 ICP-HD-3(-ND) CPU Extension60A1.1 ICP-HD-3(-ND) Front-Panels (8HP or 12HP)60Figure A1.1 ICP-HD-3(-ND) CPU Front-Panels60A1.2 IDE Carrier Board ICP-HD-3(-ND)61Figure A1.2 Interface Location of the ICP-HD-3(-ND) Module61Table A1.2 Interface Description of the ICP-HD-3(-ND) Module62A2 ICP-HD-3(-ND) Interfaces63A2.1 COM1 & COM2 Interfaces63Figure A2.1 COM1 & COM2 Interface Pinout63Table A2.1 COM1 & COM2 Connector Signals63A2.2 Mouse & Keyboard Interfaces64Figure A2.2 Mouse & Keyboard Interface Pinout64Table A2.2 Mouse & Keyboard Connector Signals64Table A2.3 USB Connector Signals65A2.3 USB 2.0 Interfaces65Figure A2.3 USB Interface Pinout65A2.4 EIDE Interface66A2.5 Slim-Line Floppy Disk Interface66IPB-FPE12 Contents67B1 IPB-FPE12 CPU Extension68B1.1 J13 Interface for LPT168B1.2 IPB-FPE12 Front-Panel (4HP or 12HP)68Figure B1.2 IPB-FPE12 Stand-Alone or Integrated with CPU68B1.3 LPT1 Piggyback69Figure B1.3 LPT1 Piggyback Board IPB-FPE1269Table B1.3 IPB-FPE12 Connector Description70B1.4 LPT1 Interface70Figure B1.4 LPT1 Interface Pinout70Table B1.4 LPT1 Connector Signals70ITM-RIO Contents71C1 ITM-RIO CPU Extension72C1.1 ITM-RIO-D Configurations72Table C1.10 Valid Rear I/O Configurations72Table C1.11 Rear I/O Module Functionality72C1.2 ITM-RIO Rear-Panels (4HP or 8HP)73Figure C1.2 The rear Panels of the Inova ITM-RIO-D-x73C1.3 ITM-RIO-D-x Transition Module74Figure C1.3 Inova Rear I/O Transition Module ITM-RIO-D-x74Table C1.3 ITM-RIO-D-x Connector Description75C1.4 COM1 & COM2 Interfaces76Figure C1.4 COM1 & COM2 Interface Pinout76Table C1.4 COM1 & COM2 Connector Signals76C1.5 LPT1 Interface77Figure C1.5 LPT1 Interface Pinout77Table C1.5 LPT1 Connector Signals77C1.6 Mouse & Keyboard Interfaces78Figure C1.6 Mouse & Keyboard Interface Pinout78Table C1.6 Mouse & Keyboard Connector Signals78C1.7 VGA Interface79Figure C1.7 VGA Interface Pinout79Table C1.7 Video Output Connector Signals79C1.8 Fast Ethernet Interface80Figure C1.8 Fast Ethernet Interface Pinout80Table C1.8 Fast Ethernet Connector Signals80C1.9 USB Interface (USB 4)81Figure C1.9 USB Interface Pinout81Table C1.9 USB Connector Signals81C1.10 EIDE Interface82C1.11 Slim-Line Floppy Disk Interface82C1.12 ITM-RIO(C&D)-FHLU Extension83Figure C1.12 ITM-RIO(C&D)-FHLU83IPM-ATA85D1 IPM-ATA CPU Extension86D1.1 rJ2 Interface86Figure D1.1a Dedicated IPM-ATA Backplane86D1.1 rJ2 Interfaces (Contd.)87Figure D1.1b The Complete Connection Picture87D1.2 IPM-ATA-HD88Figure D1.2 IPM-ATA-HD Board Layout88Table D1.2 IPM-ATA-HD Jumper Description (CF Socket)88D1.3 IPM-ATA-CF89Figure D1.3 IPM-ATA-CF Board Layout89Table D1.3 IPM-ATA-CF Jumper Description89D1.4 IPM-ATA-PCMCIA90Figure D1.4 IPM-ATA-PCMCIA Board Layout90Table D1.4 IPM-ATA-PCMCIA Jumper Description90D1.5 Device Compatibility91Table D1.5 Compatibility List91AGP-R700093E1 AGP-R7000 CPU Extension94Table E1.00 AGP Piggyback Configurations94E1.1 Specifications95E1.2 J4 Interface96Figure E1.20 J4 on the Underside of the AGP-R7000 Piggyback96Table E1.20 J4 Pinout97Table E1.20 J4 Pinout - Contd.98E1.3 J3 & J5 IBP-GS-MULTILINK (TFT) Interfaces99Figure E1.30 J3 and J5 Topside Connectors for the Inova IPB-GS-MULTILINK99Table E1.30 J3 & J5 Interface Pinout100E1.4 J1 Front-Panel VGA/TMDS Interface101Figure E1.40 Standard Front-Panel VGA/TMDS Interface101Table E1.40 J1 Standard Front-Panel VGA/TMDS Pinout101Table E1.41 J2 DIP Switch Settings - Digital TMDS (PanelLink) or DVI-D102Table E1.42 J2 DIP Switch Settings - TFT (24Bit TTL/CMOS)102E1.5 Rear I/O VGA Interface103Size: 2.78 MBPages: 103Language: EnglishOpen manual