User Manual (YA80543KC0216M)Table of Contents1 Introduction111.1 Overview111.2 Processor Abstraction Layer111.3 Mixing Processors of Different Frequencies and Cache Sizes121.4 Terminology121.5 State of Data121.6 Reference Documents132 Electrical Specifications152.1 Itanium® 2 Processor System Bus152.1.1 System Bus Power Pins152.1.2 System Bus No Connect152.2 System Bus Signals152.2.1 Signal Groups152.2.2 Signal Descriptions162.3 Package Specifications172.4 Signal Specifications182.4.1 Maximum Ratings222.5 System Bus Signal Quality Specifications and Measurement Guidelines232.5.1 Overshoot/Undershoot Magnitude232.5.2 Overshoot/Undershoot Pulse Duration242.5.3 Activity Factor242.5.4 Reading Overshoot/Undershoot Specification Tables252.5.5 Determining if a System Meets the Overshoot/Undershoot Specifications252.5.6 Wired-OR Signals282.6 Power Pod Connector Signals302.7 Itanium® 2 Processor System Bus Clock and Processor Clocking322.8 Recommended Connections for Unused Pins353 Pinout Specifications374 Mechanical Specifications694.1 Mechanical Dimensions694.2 Package Marking724.2.1 Processor Top-Side Marking724.2.2 Processor Bottom-Side Marking725 Thermal Specifications755.1 Thermal Features755.1.1 Thermal Alert755.1.2 Enhanced Thermal Management765.1.3 Thermal Trip765.2 Case Temperature766 System Management Feature Specifications796.1 System Management Bus796.1.1 System Management Bus Interface796.1.2 System Management Interface Signals796.1.3 SMBus Device Addressing816.2 Processor Information ROM826.3 Scratch EEPROM856.4 Processor Information ROM and Scratch EEPROM Supported SMBus Transactions856.5 Thermal Sensing Device866.6 Thermal Sensing Device Supported SMBus Transactions876.7 Thermal Sensing Device Registers886.7.1 Thermal Reference Registers886.7.2 Thermal Limit Registers896.7.3 Status Register896.7.4 Configuration Register896.7.5 Conversion Rate Register90A Signals Reference91A.1 Alphabetical Signals Reference91A.1.1 A[49:3]# (I/O)91A.1.2 A20M# (I)91A.1.3 ADS# (I/O)91A.1.4 AP[1:0]# (I/O)91A.1.5 ASZ[1:0]# (I/O)91A.1.6 ATTR[3:0]# (I/O)92A.1.7 BCLKp/BCLKn (I)92A.1.8 BE[7:0]# (I/O)92A.1.9 BERR# (I/O)93A.1.10 BINIT# (I/O)94A.1.11 BNR# (I/O)94A.1.12 BPM[5:0]# (I/O)94A.1.13 BPRI# (I)94A.1.14 BR[0]# (I/O) and BR[3:1]# (I)94A.1.15 BREQ[3:0]# (I/O)95A.1.16 CCL# (I/O)96A.1.17 CPUPRES# (O)96A.1.18 D[127:0]# (I/O)96A.1.19 D/C# (I/O)96A.1.20 DBSY# (I/O)96A.1.21 DBSY_C1# (O)96A.1.22 DBSY_C2# (O)97A.1.23 DEFER# (I)97A.1.24 DEN# (I/O)97A.1.25 DEP[15:0]# (I/O)97A.1.26 DHIT# (I)97A.1.27 DPS# (I/O)98A.1.28 DRDY# (I/O)98A.1.29 DRDY_C1# (O)98A.1.30 DRDY_C2# (O)98A.1.31 DSZ[1:0]# (I/O)98A.1.32 EXF[4:0]# (I/O)98A.1.33 FCL# (I/O)99A.1.34 FERR# (O)99A.1.35 GSEQ# (I)99A.1.36 HIT# (I/O) and HITM# (I/O)99A.1.37 ID[9:0]# (I)99A.1.38 IDS# (I)99A.1.39 IGNNE# (I)100A.1.40 INIT# (I)100A.1.41 INT (I)100A.1.42 IP[1:0]# (I)100A.1.43 LEN[2:0]# (I/O)100A.1.44 LINT[1:0] (I)101A.1.45 LOCK# (I/O)101A.1.46 NMI (I)101A.1.47 OWN# (I/O)101A.1.48 PMI# (I)101A.1.49 PWRGOOD (I)101A.1.50 REQ[5:0]# (I/O)101A.1.51 RESET# (I)102A.1.52 RP# (I/O)102A.1.53 RS[2:0]# (I)103A.1.54 RSP# (I)103A.1.55 SBSY# (I/O)103A.1.56 SBSY_C1# (O)103A.1.57 SBSY_C2# (O)103A.1.58 SPLCK# (I/O)103A.1.59 STBn[7:0]# and STBp[7:0]# (I/O)104A.1.60 TCK (I)104A.1.61 TDI (I)104A.1.62 TDO (O)104A.1.63 THRMTRIP# (O)104A.1.64 THRMALERT# (O)105A.1.65 TMS (I)105A.1.66 TND# (I/O)105A.1.67 TRDY# (I)105A.1.68 TRST# (I)105A.1.69 WSNP# (I/O)105A.2 Signal Summaries105Size: 2.75 MBPages: 108Language: EnglishOpen manual