Intel 2.20 GHz User Manuals

Table of Contents

• Contents

  3
• Revision History

  7
• Introduction 1

  9
  • 1.1 Terminology

    9
    • 1.1.1 Processor Packaging Terminology

      10
  • 1.2 References

    11
• Electrical Specifications 2

  13
  • 2.1 System Bus and GTLREF

    13
  • 2.2 Power and Ground Pins

    13
  • 2.3 Decoupling Guidelines

    13
    • 2.3.1 VCC Decoupling

      14
    • 2.3.2 System Bus AGTL+ Decoupling

      14
    • 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking

      14
  • 2.4 Voltage Identification

    15
    • 2.4.1 Phase Lock Loop (PLL) Power and Filter

      16
  • 2.5 Reserved, Unused Pins, and TESTHI[12:0]

    18
  • 2.6 System Bus Signal Groups

    19
  • 2.7 Asynchronous GTL+ Signals

    20
  • 2.8 Test Access Port (TAP) Connection

    20
  • 2.9 System Bus Frequency Select Signals (BSEL[1:0])

    20
  • 2.10 Maximum Ratings

    21
  • 2.11 Processor DC Specifications

    21
    • 2.11.1 Flexible Motherboard Guidelines (FMB)

      21
  • 2.12 AGTL+ System Bus Specifications

    28
  • 2.13 System Bus AC Specifications

    29
  • 2.14 Processor AC Timing Waveforms

    32
• System Bus Signal Quality Specifications 3

  41
  • 3.1 System Bus Clock (BCLK) Signal Quality Specifications

    41
  • 3.2 System Bus Signal Quality Specifications and Measurement Guidelines

    42
  • 3.3 System Bus Signal Quality Specifications and Measurement Guidelines

    45
    • 3.3.1 Overshoot/Undershoot Guidelines

      45
    • 3.3.2 Overshoot/Undershoot Magnitude

      45
    • 3.3.3 Overshoot/Undershoot Pulse Duration

      45
    • 3.3.4 Activity Factor

      46
    • 3.3.5 Reading Overshoot/Undershoot Specification Tables

      46
    • 3.3.6 Conformance Determination to Overshoot/Undershoot Specifications

      47
• Package Mechanical Specifications 4

  51
  • 4.1 Package Load Specifications

    54
  • 4.2 Processor Insertion Specifications

    55
  • 4.3 Processor Mass Specifications

    55
  • 4.4 Processor Materials

    55
  • 4.5 Processor Markings

    55
• Pin Listing and Signal Definitions 5

  59
  • 5.1 Processor Pin Assignments

    59
  • 5.2 Alphabetical Signals Reference

    72
• Thermal Specifications and Design Considerations 6

  81
  • 6.1 Processor Thermal Specifications

    82
    • 6.1.1 Thermal Specifications

      82
    • 6.1.2 Thermal Metrology

      83
      • 6.1.2.1 Processor Case Temperature Measurement

        83
• Features 7

  85
  • 7.1 Power-On Configuration Options

    85
  • 7.2 Clock Control and Low Power States

    85
    • 7.2.1 Normal State—State 1

      85
    • 7.2.2 AutoHALT Powerdown State—State 2

      86
    • 7.2.3 Stop-Grant State—State 3

      87
    • 7.2.4 HALT/Grant Snoop State—State 4

      87
    • 7.2.5 Sleep State—State 5

      88
  • 7.3 Thermal Monitor

    88
    • 7.3.1 Thermal Diode

      90
• Boxed Processor Specifications 8

  91
  • 8.1 Introduction

    91
  • 8.2 Mechanical Specifications

    92
    • 8.2.1 Boxed Processor Cooling Solution Dimensions

      92
    • 8.2.2 Boxed Processor Fan Heatsink Weight

      93
    • 8.2.3 Boxed Processor Retention Mechanism and Heatsink Assembly

      93
  • 8.3 Electrical Requirements

    94
    • 8.3.1 Fan Heatsink Power Supply

      94
  • 8.4 Thermal Specifications

    97
    • 8.4.1 Boxed Processor Cooling Requirements

      97
    • 8.4.2 Variable Speed Fan

      98
• Debug Tools Specifications 9

  101
  • 9.1 Logic Analyzer Interface (LAI)

    101
    • 9.1.1 Mechanical Considerations

      101
    • 9.1.2 Electrical Considerations

      101