User ManualTable of ContentsCONTENTS3REVISION HISTORY5PREFACE7NOMENCLATURE7COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE7GENERAL INFORMATION882543GC Component Marking Information8Summary Table of Changes9Codes Used in Summary TableS9SPECIFICATION CHANGES11GMII Setup and Hold Times11ERRATA11MDI Control Register Returns Incorrect Values11Descriptor Queue Maximum Size Limitation11Late Collision Statistics May Be Incorrect11Some Registers Cannot Be Accessed During Reset12DAC Accesses May Be Interpreted Incorrectly12Flash Memory Interface Functions Incorrectly in 64-Bit Address Space12Excessive Errors in 100Mb Half-Duplex Mode1248 Bit Preambles Sent in 10Mb and 100Mb Operation13CRS Detection Takes Too Long in MII Half-Duplex Mode13DMA Early Receive Function Does Not Work13ILOS Bit Copied Incorrectly from EEPROM to Speed Bits13Gigabit Half-Duplex Mode Operates Incorrectly13Zero-Byte PCI Bus Writes14TCP Segmentation Feature Operates Incorrectly14Incorrect Checksum Calculation and Indication14Transmitter Affected by Discarding Packets14Flash Memory Address Conflicts15Packet Buffer Memory Address Conflicts15Transmit Packet Corruption of Small Packets15Receive Packet Buffer Corruption When Nearly Full15Receive Packet Loss in 100Mb Half-Duplex Operation16TNCRS Statistic Register Has Live Count in Full-Duplex Mode16Receive IP Checksum Offload Disabled16EEPROM Initializes Software Defined Pins Incorrectly16Continuous XOFFs Transmitted When Receive Buffer Is Full17Default Speed Selection May Depend on EEPROM Presence17Link Status Change Interrupt Only Occurs If Link is Up17Early Transmit Feature Does Not Operate Correctly17TDO Output Not Floated When JTAG TAP Controller Inactive18Initialization Ignores Incorrect EEPROM Signature18Internal Loopback Difficulties18Collision Pin Not Ignored in TBI Mode18Receive Descriptor Writeback Problems for Packets Spanning Multiple Buffers19Illegal Oversize Packets Overflow Receive FIFO19Transmit Descriptor Writeback Problems with Non-Zero WTHRESH19Bus Initialization with Some Chipsets20Use of Receive Delay Timer Ring Register (RDTR) Causes Occasional Lockups20Transmit TCP Checksum Incorrectly Modified if Calculated as 0x000020SPECIFICATION CLARIFICATIONS210-70C Ambient Temperature Range21Receiver Enabling and Disabling21DOCUMENTATION CHANGES21TX/RX Descriptor Register Addresses21Auto Speed Detect Function Requires CTRL.SLU Bit to Be Set22Values Programmed to Some Registers While in Reset Do Not Persist22JTAG Port Operation22Register Summary Uses Improper Page Reference Format23Change O_EN_CDET Output to NO_CONNECT23Change Recommended Transmit IPG Programming Value for 10/100/1000BASE-T23Remove Transmit Report Status Sent Function23Remove Transmit DMA Pre-fetching and Preemption Functions23Remove Gigabit Half-Duplex Transmit Burst Timer Control Function (TBT)24Remove Adaptive IFS Throttle Function (AIT)24Size: 119 KBPages: 24Language: EnglishOpen manual
User ManualTable of ContentsCONTENTS3REVISION HISTORY5PREFACE7NOMENCLATURE7COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE7GENERAL INFORMATION882543GC Component Marking Information8Summary Table of Changes9Codes Used in Summary TableS9SPECIFICATION CHANGES11GMII Setup and Hold Times11ERRATA11MDI Control Register Returns Incorrect Values11Descriptor Queue Maximum Size Limitation11Late Collision Statistics May Be Incorrect11Some Registers Cannot Be Accessed During Reset12DAC Accesses May Be Interpreted Incorrectly12Flash Memory Interface Functions Incorrectly in 64-Bit Address Space12Excessive Errors in 100Mb Half-Duplex Mode1248 Bit Preambles Sent in 10Mb and 100Mb Operation13CRS Detection Takes Too Long in MII Half-Duplex Mode13DMA Early Receive Function Does Not Work13ILOS Bit Copied Incorrectly from EEPROM to Speed Bits13Gigabit Half-Duplex Mode Operates Incorrectly13Zero-Byte PCI Bus Writes14TCP Segmentation Feature Operates Incorrectly14Incorrect Checksum Calculation and Indication14Transmitter Affected by Discarding Packets14Flash Memory Address Conflicts15Packet Buffer Memory Address Conflicts15Transmit Packet Corruption of Small Packets15Receive Packet Buffer Corruption When Nearly Full15Receive Packet Loss in 100Mb Half-Duplex Operation16TNCRS Statistic Register Has Live Count in Full-Duplex Mode16Receive IP Checksum Offload Disabled16EEPROM Initializes Software Defined Pins Incorrectly16Continuous XOFFs Transmitted When Receive Buffer Is Full17Default Speed Selection May Depend on EEPROM Presence17Link Status Change Interrupt Only Occurs If Link is Up17Early Transmit Feature Does Not Operate Correctly17TDO Output Not Floated When JTAG TAP Controller Inactive18Initialization Ignores Incorrect EEPROM Signature18Internal Loopback Difficulties18Collision Pin Not Ignored in TBI Mode18Receive Descriptor Writeback Problems for Packets Spanning Multiple Buffers19Illegal Oversize Packets Overflow Receive FIFO19Transmit Descriptor Writeback Problems with Non-Zero WTHRESH19Bus Initialization with Some Chipsets20Use of Receive Delay Timer Ring Register (RDTR) Causes Occasional Lockups20Transmit TCP Checksum Incorrectly Modified if Calculated as 0x000020SPECIFICATION CLARIFICATIONS210-70C Ambient Temperature Range21Receiver Enabling and Disabling21DOCUMENTATION CHANGES21TX/RX Descriptor Register Addresses21Auto Speed Detect Function Requires CTRL.SLU Bit to Be Set22Values Programmed to Some Registers While in Reset Do Not Persist22JTAG Port Operation22Register Summary Uses Improper Page Reference Format23Change O_EN_CDET Output to NO_CONNECT23Change Recommended Transmit IPG Programming Value for 10/100/1000BASE-T23Remove Transmit Report Status Sent Function23Remove Transmit DMA Pre-fetching and Preemption Functions23Remove Gigabit Half-Duplex Transmit Burst Timer Control Function (TBT)24Remove Adaptive IFS Throttle Function (AIT)24Size: 119 KBPages: 24Language: EnglishOpen manual
