User ManualTable of Contents1.0 Introduction51.1 Functional Overview5Figure 1. 82555 10/100 Mbps Ethernet Solution51.2 Compliance to Industry Standards52.0 Architectural Overview7Figure 2. 82555 Simplified Block Diagram72.1 100 Mbps Mode7Figure 3. 82555 Analog Logic82.2 10 Mbps Mode8Figure 4. Intel 82557/82555 Solution92.3 Media Independent Interface (MII)9Table 1. 82555 MII93.0 Pin Definitions11Figure 5. 82555 Pin Numbers and Labels113.1 Pin Types123.2 Clock Pins123.3 Twisted Pair Ethernet (TPE) Pins123.4 Media Independent Interface (MII) Pins123.5 Media Access Control/Repeater Interface Control Pins133.6 LED Pins143.7 External Bias Pins143.8 Miscellaneous Control Pins153.9 Power and Ground Pins164.0 100BASE-TX Adapter Mode Operation174.1 100BASE-TX Transmit Clock Generation174.2 100BASE-TX Transmit Blocks174.2.1 100BASE-TX 4B/5B Encoder17Table 2. 4B/5B Encoder174.2.2 100BASE-TX Scrambler and MLT-3 Encoder18Figure 6. NRZ to MLT-3 Encoding Diagram194.2.3 100BASE-TX Transmit Framing194.2.4 Transmit Driver20Figure 7. Conceptual Transmit Differential Waveform20Table 3. Magnetics Modules204.3 100BASE-TX Receive Blocks204.3.1 Adaptive Equalizer214.3.2 Receive Clock and Data Recovery214.3.3 MLT-3 Decoder, Descrambler, and Receive Digital Section214.3.4 100BASE-TX Receive Framing214.3.5 100BASE-TX Receive Error Detection and Reporting214.4 100BASE-TX Collision Detection214.5 100BASE-TX Link Integrity and Auto-Negotiation Solution224.5.1 Link Integrity224.5.2 Auto-Negotiation224.5.3 Combination Tx/T4 Auto-Negotiation Solution22Figure 8. Combination Card Example234.6 Auto 10/100 Mbps Speed Selection234.7 Adapter Mode Addresses235.0 10BASE-T Functionality in Adapter Mode255.1 10BASE-T Transmit Clock Generation255.2 10BASE-T Transmit Blocks255.2.1 10BASE-T Manchester Encoder255.2.2 10BASE-T Driver and Filter255.3 10BASE-T Receive Blocks255.3.1 10BASE-T Manchester Decoder255.3.2 10BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter255.3.3 10BASE-T Error Detection and Reporting265.4 10BASE-T Collision Detection265.5 10BASE-T Link Integrity265.6 10BASE-T Jabber Control Function265.7 10BASE-T Full Duplex276.0 Repeater Mode296.1 Special Repeater Features296.2 Connectivity29Figure 9. Clock Signal Example307.0 Management Data Interface317.1 MDI Frame Structure317.2 MDI Registers327.2.1 MDI Registers 0 - 7327.2.1.1 Register 0: Control Register Bit Definitions327.2.1.2 Register 1: Status Register Bit Definitions337.2.1.3 Register 2: 82555 Identifier Register Bit Definitions347.2.1.4 Register 3: 82555 Identifier Register Bit Definitions347.2.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions347.2.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions357.2.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions357.2.2 MDI Registers 8 - 15357.2.3 MDI Registers 16 - 31357.2.3.1 Register 16: 82555 Status and Control Register Bit Definitions367.2.3.2 Register 17: 82555 Special Control Bit Definitions367.2.3.3 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions377.2.3.4 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions377.2.3.5 Register 22: Receive Symbol Error Counter Bit Definitions387.2.3.6 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions387.2.3.7 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions387.2.3.8 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions387.2.3.9 Register 27: 82555 Special Control Bit Definitions388.0 Auto-Negotiation Functionality398.1 Description39Table 4. Technology Ability Field Bit Assignments39Table 5. Technology Priority398.2 Parallel Detect and Auto-Negotiation40Figure 10. Auto-Negotiation and Parallel Detect419.0 LED Descriptions4310.0 Reset and Miscellaneous Test Modes4510.1 Reset4510.2 Loopback4510.3 Scrambler Bypass4510.4 Test Port45Table 6. Test Instruction Coding4611.0 Electrical Specifications and Timing Parameters4711.1 Absolute Maximum Ratings4711.2 General Operating Conditions4711.3 DC Characteristics4711.3.1 MII DC Characteristics4711.3.2 10BASE-T Voltage/Current DC Characteristics47Figure 11. RBIAS10 Resistance versus ICCT104811.3.3 100BASE-TX Voltage/Current DC Characteristics48Figure 12. RBIAS100 Resistance versus ICCT1004911.4 AC Characteristics49Figure 13. AC Testing Level Conditions4911.4.1 MII Clock Specifications49Figure 14. MII Clocks AC Timing5011.4.2 MII Timing Parameters50Figure 15. MII Transmit Timing Parameters50Figure 16. MII Receive Timing Parameters51Figure 17. MII Timing Parameters: MDC/MDIO5111.4.3 Repeater Mode Timing Parameters51Figure 18. PORT Enable Timing5111.4.4 Transmit Packet Timing Parameters52Figure 19. Transmit Frame Timing Parameters5211.4.5 Squelch Test Timing Parameters52Figure 20. Squelch Test Timing Parameters5311.4.6 Jabber Timing Parameters53Figure 21. Jabber Timing Parameters5311.4.7 Receive Packet Timing Parameters53Figure 22. Receive Packet Timing Parameters5411.4.8 10BASE-T Normal Link Pulse (NLP) Timing Parameters54Figure 23. Normal Link Pulse Timing Parameters5411.4.9 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters54Figure 24. Fast Link Pulse Timing Parameters5511.4.10 Reset Timing Parameters55Figure 25. Reset Timing Parameters5511.4.11 X1 Clock Specifications55Figure 26. X1 Clock Specifications5611.4.12 100BASE-TX Transmitter AC Specification5612.0 82555 Package Information57Figure 27. Dimension Diagram for the 82555 QFP57Table 7. Dimensions for the 82555 QFP57Size: 864 KBPages: 58Language: EnglishOpen manual