User ManualTable of Contents1 Introduction81.1 Processor Feature Details91.2 Supported Technologies101.3 Interfaces101.3.1 System Memory Support101.3.2 PCI Express*111.3.3 Direct Media Interface Gen 2 (DMI2)121.3.4 Platform Environment Control Interface (PECI)131.4 Power Management Support131.4.1 Processor Package and Core States131.4.2 System States Support131.4.3 Memory Controller131.4.4 PCI Express*131.5 Thermal Management Support131.6 Package Summary141.7 Terminology141.8 Related Documents162 Interfaces182.1 System Memory Interface182.1.1 System Memory Technology Support182.1.2 System Memory Timing Support182.2 PCI Express* Interface192.2.1 PCI Express* Architecture192.2.2 PCI Express* Configuration Mechanism202.3 Direct Media Interface 2 (DMI2) / PCI Express* Interface212.3.1 DMI2 Error Flow212.3.2 Processor / PCH Compatibility Assumptions212.3.3 DMI2 Link Down212.4 Platform Environment Control Interface (PECI)213 Technologies223.1 Intel® Virtualization Technology (Intel® VT)223.1.1 Intel® VT-x Objectives223.1.2 Intel® VT-x Features233.1.3 Intel® VT-d Objectives233.1.4 Intel® Virtualization Technology Processor Extensions243.2 Security Technologies253.2.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Instructions253.2.2 Execute Disable Bit253.3 Intel® Hyper-Threading Technology (Intel® HT Technology)253.4 Intel® Turbo Boost Technology263.4.1 Intel® Turbo Boost Operating Frequency263.5 Enhanced Intel® SpeedStep® Technology263.6 Intel® Advanced Vector Extensions (Intel® AVX)274 Power Management294.1 Advanced Configuration and Power Interface (ACPI) States Supported294.1.1 System States294.1.2 Processor Package and Core States294.1.3 Integrated Memory Controller (IMC) States314.1.4 Direct Media Interface Gen 2 (DMI2) / PCI Express* Link States314.1.5 G, S, and C State Combinations324.2 Processor Core / Package Power Management324.2.1 Enhanced Intel® SpeedStep® Technology324.2.2 Low-Power Idle States334.2.3 Requesting Low-Power Idle States344.2.4 Core C-states354.2.5 Package C-States364.2.6 Package C-State Power Specifications394.3 System Memory Power Management394.3.1 CKE Power-Down404.3.2 Self-Refresh404.3.3 DRAM I/O Power Management414.4 Direct Media Interface 2 (DMI2) / PCI Express* Power Management415 Thermal Management Specifications426 Signal Descriptions436.1 System Memory Interface Signals436.2 PCI Express* Based Interface Signals446.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Port 0 Signals466.4 Platform Environment Control Interface (PECI) Signal466.5 System Reference Clock Signals466.6 Joint Test Action Group (JTAG) and Test Access Point (TAP) Signals466.7 Serial Voltage Identification (SVID) Signals476.8 Processor Asynchronous Sideband and Miscellaneous Signals476.9 Processor Power and Ground Supplies507 Electrical Specifications517.1 Processor Signaling517.1.1 System Memory Interface Signal Groups517.1.2 PCI Express* Signals517.1.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Signals517.1.4 Platform Environmental Control Interface (PECI)527.1.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN)527.1.6 Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals537.1.7 Processor Sideband Signals537.1.8 Power, Ground and Sense Signals537.1.9 Reserved or Unused Signals587.2 Signal Group Summary587.3 Power-On Configuration (POC) Options617.4 Absolute Maximum and Minimum Ratings627.4.1 Storage Conditions Specifications627.5 DC Specifications637.5.1 Voltage and Current Specifications637.5.2 Die Voltage Validation667.5.3 Signal DC Specifications678 Processor Land Listing739 Package Mechanical Specifications11610 Boxed Processor Specifications11710.1 Introduction11710.2 Boxed Processor Contents117Size: 876 KBPages: 117Language: EnglishOpen manual
User ManualTable of Contents1 Introduction81.1 Processor Feature Details91.2 Supported Technologies101.3 Interfaces101.3.1 System Memory Support101.3.2 PCI Express*111.3.3 Direct Media Interface Gen 2 (DMI2)121.3.4 Platform Environment Control Interface (PECI)131.4 Power Management Support131.4.1 Processor Package and Core States131.4.2 System States Support131.4.3 Memory Controller131.4.4 PCI Express*131.5 Thermal Management Support131.6 Package Summary141.7 Terminology141.8 Related Documents162 Interfaces182.1 System Memory Interface182.1.1 System Memory Technology Support182.1.2 System Memory Timing Support182.2 PCI Express* Interface192.2.1 PCI Express* Architecture192.2.2 PCI Express* Configuration Mechanism202.3 Direct Media Interface 2 (DMI2) / PCI Express* Interface212.3.1 DMI2 Error Flow212.3.2 Processor / PCH Compatibility Assumptions212.3.3 DMI2 Link Down212.4 Platform Environment Control Interface (PECI)213 Technologies223.1 Intel® Virtualization Technology (Intel® VT)223.1.1 Intel® VT-x Objectives223.1.2 Intel® VT-x Features233.1.3 Intel® VT-d Objectives233.1.4 Intel® Virtualization Technology Processor Extensions243.2 Security Technologies253.2.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Instructions253.2.2 Execute Disable Bit253.3 Intel® Hyper-Threading Technology (Intel® HT Technology)253.4 Intel® Turbo Boost Technology263.4.1 Intel® Turbo Boost Operating Frequency263.5 Enhanced Intel® SpeedStep® Technology263.6 Intel® Advanced Vector Extensions (Intel® AVX)274 Power Management294.1 Advanced Configuration and Power Interface (ACPI) States Supported294.1.1 System States294.1.2 Processor Package and Core States294.1.3 Integrated Memory Controller (IMC) States314.1.4 Direct Media Interface Gen 2 (DMI2) / PCI Express* Link States314.1.5 G, S, and C State Combinations324.2 Processor Core / Package Power Management324.2.1 Enhanced Intel® SpeedStep® Technology324.2.2 Low-Power Idle States334.2.3 Requesting Low-Power Idle States344.2.4 Core C-states354.2.5 Package C-States364.2.6 Package C-State Power Specifications394.3 System Memory Power Management394.3.1 CKE Power-Down404.3.2 Self-Refresh404.3.3 DRAM I/O Power Management414.4 Direct Media Interface 2 (DMI2) / PCI Express* Power Management415 Thermal Management Specifications426 Signal Descriptions436.1 System Memory Interface Signals436.2 PCI Express* Based Interface Signals446.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Port 0 Signals466.4 Platform Environment Control Interface (PECI) Signal466.5 System Reference Clock Signals466.6 Joint Test Action Group (JTAG) and Test Access Point (TAP) Signals466.7 Serial Voltage Identification (SVID) Signals476.8 Processor Asynchronous Sideband and Miscellaneous Signals476.9 Processor Power and Ground Supplies507 Electrical Specifications517.1 Processor Signaling517.1.1 System Memory Interface Signal Groups517.1.2 PCI Express* Signals517.1.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Signals517.1.4 Platform Environmental Control Interface (PECI)527.1.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN)527.1.6 Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals537.1.7 Processor Sideband Signals537.1.8 Power, Ground and Sense Signals537.1.9 Reserved or Unused Signals587.2 Signal Group Summary587.3 Power-On Configuration (POC) Options617.4 Absolute Maximum and Minimum Ratings627.4.1 Storage Conditions Specifications627.5 DC Specifications637.5.1 Voltage and Current Specifications637.5.2 Die Voltage Validation667.5.3 Signal DC Specifications678 Processor Land Listing739 Package Mechanical Specifications11610 Boxed Processor Specifications11710.1 Introduction11710.2 Boxed Processor Contents117Size: 876 KBPages: 117Language: EnglishOpen manual
