User ManualTable of ContentsContents3Figures6Tables7Revision History91.0 Introduction101.1 Supported Technologies111.2 Interfaces121.3 Power Management Support121.4 Thermal Management Support131.5 Package Support131.6 Terminology131.7 Related Documents162.0 Interfaces182.1 System Memory Interface182.1.1 System Memory Technology Supported192.1.2 System Memory Timing Support202.1.3 System Memory Organization Modes212.1.3.1 System Memory Frequency222.1.3.2 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements222.1.3.3 Data Scrambling232.2 PCI Express* Interface232.2.1 PCI Express* Support232.2.2 PCI Express* Architecture242.2.3 PCI Express* Configuration Mechanism242.3 Direct Media Interface (DMI)262.4 Processor Graphics282.5 Processor Graphics Controller (GT)282.5.1 3D and Video Engines for Graphics Processing292.5.2 Multi Graphics Controllers Multi-Monitor Support312.6 Digital Display Interface (DDI)312.7 Intel® Flexible Display Interface (Intel® FDI)372.8 Platform Environmental Control Interface (PECI)372.8.1 PECI Bus Architecture373.0 Technologies393.1 Intel® Virtualization Technology (Intel® VT)393.2 Intel® Trusted Execution Technology (Intel® TXT)433.3 Intel® Hyper-Threading Technology (Intel® HT Technology)443.4 Intel® Turbo Boost Technology 2.0453.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)453.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)463.7 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)463.8 Intel® 64 Architecture x2APIC473.9 Power Aware Interrupt Routing (PAIR)483.10 Execute Disable Bit483.11 Supervisor Mode Execution Protection (SMEP)484.0 Power Management494.1 Advanced Configuration and Power Interface (ACPI) States Supported504.2 Processor Core Power Management514.2.1 Enhanced Intel® SpeedStep® Technology Key Features514.2.2 Low-Power Idle States524.2.3 Requesting Low-Power Idle States534.2.4 Core C-State Rules544.2.5 Package C-States554.2.6 Package C-States and Display Resolutions594.3 Integrated Memory Controller (IMC) Power Management604.3.1 Disabling Unused System Memory Outputs604.3.2 DRAM Power Management and Initialization614.3.2.1 Initialization Role of CKE624.3.2.2 Conditional Self-Refresh624.3.2.3 Dynamic Power-Down624.3.2.4 DRAM I/O Power Management634.3.3 DRAM Running Average Power Limitation (RAPL)634.3.4 DDR Electrical Power Gating (EPG)634.4 PCI Express* Power Management634.5 Direct Media Interface (DMI) Power Management634.6 Graphics Power Management644.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)644.6.2 Graphics Render C-State644.6.3 Intel® Graphics Dynamic Frequency645.0 Thermal Management655.1 Desktop Processor Thermal Profiles665.1.1 Processor (PCG 2013D) Thermal Profile675.1.2 Processor (PCG 2013C) Thermal Profile685.1.3 Processor (PCG 2013B) Thermal Profile695.1.4 Processor (PCG 2013A) Thermal Profile705.2 Thermal Metrology715.3 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1715.4 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0735.5 Processor Temperature745.6 Adaptive Thermal Monitor755.7 THERMTRIP# Signal785.8 Digital Thermal Sensor785.8.1 Digital Thermal Sensor Accuracy (Taccuracy)795.9 Intel® Turbo Boost Technology Thermal Considerations795.9.1 Intel® Turbo Boost Technology Power Control and Reporting795.9.2 Package Power Control805.9.3 Turbo Time Parameter816.0 Signal Description826.1 System Memory Interface Signals826.2 Memory Reference and Compensation Signals846.3 Reset and Miscellaneous Signals856.4 PCI Express*-Based Interface Signals866.5 Display Interface Signals866.6 Direct Media Interface (DMI)866.7 Phase Locked Loop (PLL) Signals876.8 Testability Signals876.9 Error and Thermal Protection Signals886.10 Power Sequencing Signals886.11 Processor Power Signals896.12 Sense Signals896.13 Ground and Non-Critical to Function (NCTF) Signals896.14 Processor Internal Pull-Up / Pull-Down Terminations897.0 Electrical Specifications907.1 Integrated Voltage Regulator907.2 Power and Ground Lands907.3 VCC Voltage Identification (VID)907.4 Reserved or Unused Signals957.5 Signal Groups957.6 Test Access Port (TAP) Connection977.7 DC Specifications977.8 Voltage and Current Specifications987.8.1 Platform Environment Control Interface (PECI) DC Characteristics1037.8.2 Input Device Hysteresis1048.0 Package Mechanical Specifications1058.1 Processor Component Keep-Out Zone1058.2 Package Loading Specifications1058.3 Package Handling Guidelines1068.4 Package Insertion Specifications1068.5 Processor Mass Specification1068.6 Processor Materials1068.7 Processor Markings1078.8 Processor Land Coordinates1078.9 Processor Storage Specifications1089.0 Processor Ball and Signal Information110Size: 2.41 MBPages: 120Language: EnglishOpen manual
User ManualTable of ContentsDesktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family1Revision History5Preface6Affected Documents6Related Documents6Nomenclature7Summary Tables of Changes8Codes Used in Summary Tables8Errata (Sheet 5 of 5)9Specification Clarifications13Documentation Changes13Identification Information14Component Identification using Programming Interface14Component Marking Information15Errata17Specification Changes47Specification Clarifications48Documentation Changes49Size: 532 KBPages: 50Language: EnglishOpen manual
