Intel Core™ i5-750 Processor (8M Cache, 2.66 GHz) User Manuals

Table of Contents

• 1 Introduction

  17
  • 1.1 Register Terminology

    17
• 2 Configuration Process and Registers

  19
  • 2.1 Platform Configuration Structure

    19
    • 2.1.1 Processor Integrated I/O (IIO) Devices (PCI Bus 0)

      19
    • 2.1.2 Processor Uncore Devices (PCI Bus — FFh)

      20
  • 2.2 Configuration Mechanisms

    21
    • 2.2.1 Standard PCI Express* Configuration Mechanism

      21
    • 2.2.2 PCI Express* Configuration Mechanism

      21
  • 2.3 Routing Configuration Accesses

    23
    • 2.3.1 Internal Device Configuration Accesses

      24
    • 2.3.2 Bridge-Related Configuration Accesses

      24
  • 2.4 Processor Register Introduction

    25
  • 2.5 I/O Mapped Registers

    26
• 3 Processor Integrated I/O (IIO) Configuration Registers

  27
  • 3.1 Processor IIO Devices (PCI Bus 0)

    27
  • 3.2 Device Mapping

    28
    • 3.2.1 Unimplemented Devices/Functions and Registers

      28
  • 3.3 PCI Express*/DMI Configuration Registers

    28
    • 3.3.1 Other Register Notes

      28
    • 3.3.2 Configuration Register Map

      29
    • 3.3.3 Standard PCI Configuration Space (0h to 3Fh) — Type 0/1 Common Configuration Space

      35
    • 3.3.4 Device-Specific PCI Configuration Space — 40h to FFh

      51
    • 3.3.5 PCIe/DMI Extended Configuration Space

      79
    • 3.3.6 DMI Root Complex Register Block

      84
  • 3.4 Integrated I/O Core Registers (Device 8, Function 0-3)

    92
    • 3.4.1 Configuration Register Map (Device 8, Function 0-3)

      92
    • 3.4.2 Standard PCI Configuration Registers

      98
    • 3.4.3 Common Extended Configuration Space Registers

      105
    • 3.4.4 Intel® VT-d, Address Mapping, System Management Registers (Device 8, Function 0)

      111
    • 3.4.5 Semaphore and ScratchPad Registers (Dev:8, F:1)

      128
    • 3.4.6 System Control/Status Registers (Device 8, Function 2)

      134
    • 3.4.7 Miscellaneous Registers (Dev:8, F:3)

      135
  • 3.5 Intel® VT-d Memory Mapped Registers

    137
    • 3.5.1 Intel® VT-d Configuration Register Space (MMIO)

      138
    • 3.5.2 Register Description

      141
  • 3.6 Intel® Trusted Execution Technology (Intel® TXT) Register Map

    157
    • 3.6.1 Intel® TXT Space Registers

      162
  • 3.7 Intel® QuickPath Interconnect Device/Functions

    176
    • 3.7.1 Intel® QuickPath Interconnect Link Layer Registers

      177
    • 3.7.2 Intel® QuickPath Interconnect Routing & Protocol Layer Registers

      180
• 4 Processor Uncore Configuration Registers

  183
  • 4.1 Processor Uncore Configuration Structure (PCI Bus — FFh)

    183
  • 4.2 Device Mapping

    184
  • 4.3 Detailed Configuration Space Maps

    185
  • 4.4 PCI Standard Registers

    201
    • 4.4.1 VID—Vendor Identification Register

      201
    • 4.4.2 DID—Device Identification Register

      201
    • 4.4.3 RID—Revision Identification Register

      202
    • 4.4.4 CCR—Class Code Register

      204
    • 4.4.5 HDR—Header Type Register

      205
    • 4.4.6 SVID—Subsystem Vendor Identification Register

      205
    • 4.4.7 SID—Subsystem Identity

      206
    • 4.4.8 PCICMD—Command Register

      207
    • 4.4.9 PCISTS—PCI Status Register

      208
  • 4.5 SAD—System Address Decoder Registers

    209
    • 4.5.1 SAD_PAM0123

      209
    • 4.5.2 SAD_PAM456

      211
    • 4.5.3 SAD_HEN

      212
    • 4.5.4 SAD_SMRAM

      212
    • 4.5.5 SAD_PCIEXBAR

      213
    • 4.5.6 SAD_TPCIEXBAR

      213
    • 4.5.7 SAD_MCSEG_BASE

      214
    • 4.5.8 SAD_MCSEG_MASK

      214
    • 4.5.9 SAD_MESEG_BASE

      215
    • 4.5.10 SAD_MESEG_MASK

      215
    • 4.5.11 SAD_DRAM_RULE_0; SAD_DRAM_RULE_1 SAD_DRAM_RULE_2; SAD_DRAM_RULE_3 SAD_DRAM_RULE_4; SAD_DRAM_RULE_5 SAD_DRAM_RULE_6; SAD_DRAM_RULE_7

      216
    • 4.5.12 SAD_INTERLEAVE_LIST_0; SAD_INTERLEAVE_LIST_1 SAD_INTERLEAVE_LIST_2; SAD_INTERLEAVE_LIST_3 SAD_INTERLEAVE_LIST_4; SAD_INTERLEAVE_LIST_5 SAD_INTERLEAVE_LIST_6; SAD_INTERLEAVE_LIST_7

      217
  • 4.6 Intel® QuickPath Interconnect Link Registers

    218
    • 4.6.1 QPI_QPILCL_L0

      218
  • 4.7 Integrated Memory Controller Control Registers

    220
    • 4.7.1 MC_CONTROL

      220
    • 4.7.2 MC_SMI_DIMM_ERROR_STATUS

      221
    • 4.7.3 MC_SMI_CNTRL

      221
    • 4.7.4 MC_STATUS

      222
    • 4.7.5 MC_RESET_CONTROL

      222
    • 4.7.6 MC_CHANNEL_MAPPER

      223
    • 4.7.7 MC_MAX_DOD

      223
    • 4.7.8 MC_CFG_LOCK

      224
    • 4.7.9 MC_RD_CRDT_INIT

      225
    • 4.7.10 MC_CRDT_WR_THLD

      226
  • 4.8 TAD—Target Address Decoder Registers

    227
    • 4.8.1 TAD_DRAM_RULE_0; TAD_DRAM_RULE_1 TAD_DRAM_RULE_2; TAD_DRAM_RULE_3 TAD_DRAM_RULE_4; TAD_DRAM_RULE_5 TAD_DRAM_RULE_6; TAD_DRAM_RULE_7

      227
    • 4.8.2 TAD_INTERLEAVE_LIST_0; TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2; TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4; TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6; TAD_INTERLEAVE_LIST_7

      228
  • 4.9 Integrated Memory Controller Test Registers

    229
    • 4.9.1 Integrated Memory Controller Padscan

      229
    • 4.9.2 MC_DIMM_CLK_RATIO_STATUS

      231
    • 4.9.3 MC_DIMM_CLK_RATIO

      232
    • 4.9.4 MC_TEST_LTRCON

      232
    • 4.9.5 MC_TEST_PH_CTR

      233
    • 4.9.6 MC_TEST_PH_PIS

      233
    • 4.9.7 MC_TEST_PAT_GCTR

      234
    • 4.9.8 MC_TEST_PAT_BA

      235
    • 4.9.9 MC_TEST_PAT_IS

      235
    • 4.9.10 MC_TEST_PAT_DCD

      235
    • 4.9.11 MC_TEST_EP_SCCTL

      236
    • 4.9.12 MC_TEST_EP_SCD

      236
  • 4.10 Integrated Memory Controller Channel Control Registers

    237
    • 4.10.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD

      237
    • 4.10.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD

      238
    • 4.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS

      239
    • 4.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS

      240
    • 4.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD

      241
    • 4.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT

      242
    • 4.10.7 MC_CHANNEL_0_MRS_VALUE_0_1 MC_CHANNEL_1_MRS_VALUE_0_1

      242
    • 4.10.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2

      243
    • 4.10.9 MC_CHANNEL_0_RANK_PRESENT MC_CHANNEL_1_RANK_PRESENT

      244
    • 4.10.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A

      245
    • 4.10.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B

      247
    • 4.10.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING

      248
    • 4.10.13 MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_1_REFRESH_TIMING

      248
    • 4.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING

      249
    • 4.10.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING

      250
    • 4.10.16 MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_1_RCOMP_PARAMS

      250
    • 4.10.17 MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS1

      251
    • 4.10.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2

      252
    • 4.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD

      252
    • 4.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD

      253
    • 4.10.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR

      253
    • 4.10.22 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR

      253
    • 4.10.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS

      254
    • 4.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS

      255
    • 4.10.25 MC_CHANNEL_0_MAINTENANCE_OPS MC_CHANNEL_1_MAINTENANCE_OPS

      255
    • 4.10.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS

      256
    • 4.10.27 MC_CHANNEL_0_RX_BGF_SETTINGS MC_CHANNEL_1_RX_BGF_SETTINGS

      257
    • 4.10.28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS

      257
    • 4.10.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS

      258
    • 4.10.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY MC_CHANNEL_1_ROUND_TRIP_LATENCY

      258
    • 4.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS1

      259
    • 4.10.32 MC_CHANNEL_0_PAGETABLE_PARAMS2 MC_CHANNEL_1_PAGETABLE_PARAMS2

      259
    • 4.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1

      260
    • 4.10.34 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0 MC_TX_BG_CMD_OFFSET_SETTINGS_CH1

      260
    • 4.10.35 MC_TX_BG_DATA_OFFSET_SETTINGS_CH0 MC_TX_BG_DATA_OFFSET_SETTINGS_CH1

      260
  • 4.11 Integrated Memory Controller Channel Address Registers

    261
    • 4.11.1 MC_DOD_CH0_0 MC_DOD_CH0_1

      261
    • 4.11.2 MC_DOD_CH1_0 MC_DOD_CH1_1

      262
    • 4.11.3 MC_SAG_CH0_0; MC_SAG_CH0_1; MC_SAG_CH0_2; MC_SAG_CH0_3; MC_SAG_CH0_4; MC_SAG_CH0_5; MC_SAG_CH0_6; MC_SAG_CH0_7

      263
    • 4.11.4 MC_SAG_CH1_0; MC_SAG_CH1_1; MC_SAG_CH1_2; MC_SAG_CH1_3; MC_SAG_CH1_4; MC_SAG_CH1_5; MC_SAG_CH1_6; MC_SAG_CH1_7

      264
  • 4.12 Integrated Memory Controller Channel Rank Registers

    265
    • 4.12.1 MC_RIR_LIMIT_CH0_0; MC_RIR_LIMIT_CH0_1; MC_RIR_LIMIT_CH0_2; MC_RIR_LIMIT_CH0_3; MC_RIR_LIMIT_CH0_4; MC_RIR_LIMIT_CH0_5; MC_RIR_LIMIT_CH0_6; MC_RIR_LIMIT_CH0_7

      265
    • 4.12.2 MC_RIR_LIMIT_CH1_0; MC_RIR_LIMIT_CH1_1; MC_RIR_LIMIT_CH1_2; MC_RIR_LIMIT_CH1_3; MC_RIR_LIMIT_CH1_4; MC_RIR_LIMIT_CH1_5; MC_RIR_LIMIT_CH1_6; MC_RIR_LIMIT_CH1_7

      265
    • 4.12.3 MC_RIR_WAY_CH0_0; MC_RIR_WAY_CH0_1; MC_RIR_WAY_CH0_2; MC_RIR_WAY_CH0_3; MC_RIR_WAY_CH0_4; MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6; MC_RIR_WAY_CH0_7 MC_RIR_WAY_CH0_8; MC_RIR_WAY_CH0_9 MC_RIR_WAY_CH0_10; MC_RIR_WAY_CH0_11 MC_RIR_WAY_CH0_12; MC_RIR_WAY...

      266
    • 4.12.4 MC_RIR_WAY_CH1_0; MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2; MC_RIR_WAY_CH1_3 MC_RIR_WAY_CH1_4; MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6; MC_RIR_WAY_CH1_7 MC_RIR_WAY_CH1_8; MC_RIR_WAY_CH1_9 MC_RIR_WAY_CH1_10; MC_RIR_WAY_CH1_11 MC_RIR_WAY_CH1_12; MC_RIR_WAY_C...

      267
  • 4.13 Memory Thermal Control

    268
    • 4.13.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1

      268
    • 4.13.2 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1

      268
    • 4.13.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1

      269
    • 4.13.4 MC_THERMAL_PARAMS_A0 MC_THERMAL_PARAMS_A1

      269
    • 4.13.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1

      270
    • 4.13.6 MC_COOLING_COEF0 MC_COOLING_COEF1

      270
    • 4.13.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1

      271
    • 4.13.8 MC_THROTTLE_OFFSET0 MC_THROTTLE_OFFSET1

      271
    • 4.13.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP1

      272
    • 4.13.10 MC_DDR_THERM_COMMAND0 MC_DDR_THERM_COMMAND1

      272
    • 4.13.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS1

      273
• 5 System Address Map

  275
  • 5.1 Introduction

    275
  • 5.2 Memory Address Space

    276
    • 5.2.1 System Address Map

      277
    • 5.2.2 System DRAM Memory Regions

      278
    • 5.2.3 VGA/SMM and Legacy C/D/E/F Regions

      279
    • 5.2.4 Address Region between 1 MB and TOLM

      280
    • 5.2.5 Address Region from TOLM to 4 GB

      281
    • 5.2.6 Address Regions above 4 GB

      284
    • 5.2.7 Protected System DRAM Regions

      285
  • 5.3 IO Address Space

    285
    • 5.3.1 VGA I/O Addresses

      285
    • 5.3.2 ISA Addresses

      286
    • 5.3.3 CFC/CF8 Addresses

      286
    • 5.3.4 PCIe Device I/O Addresses

      286
  • 5.4 Configuration/CSR Space

    286
    • 5.4.1 PCIe Configuration Space

      286
  • 5.5 System Management Mode (SMM)

    287
    • 5.5.1 SMM Space Definition

      287
    • 5.5.2 SMM Space Restrictions

      288
    • 5.5.3 SMM Space Combinations

      288
    • 5.5.4 SMM Control Combinations

      289
    • 5.5.5 SMM Space Decode and Transaction Handling

      289
    • 5.5.6 Processor WB Transaction to an Enabled SMM Address Space

      289
    • 5.5.7 SMM Access Through GTT TLB

      289
  • 5.6 Memory Shadowing

    290
  • 5.7 IIO Address Map Notes

    290
    • 5.7.1 Memory Recovery

      290
    • 5.7.2 Non-Coherent Address Space

      290
  • 5.8 IIO Address Decoding

    291
    • 5.8.1 Outbound Address Decoding

      291
    • 5.8.2 Inbound Address Decoding

      295
    • 5.8.3 Intel® VT-d Address Map Implications

      300