User ManualTable of Contents1.0 Introduction111.1 Overview111.2 Terminology171.3 Reference Documents192.0 Intel® 82854 GMCH Overview212.1 System Architecture212.1.1 Intel® 82854 GMCH212.2 Processor Host Interface222.3 GMCH System Memory Interface222.4 Graphics Features232.5 Display Features232.5.1 GMCH Analog Display Port232.5.2 GMCH Integrated DVO Ports232.6 Hub Interface242.7 Address Decode Policies242.8 GMCH Clocking252.9 System Interrupts263.0 Signal Description273.1 Host Interface Signals283.2 DDR SDRAM Interface313.3 Hub Interface Signals323.4 Clocks333.5 Internal Graphics Display Signals353.5.1 Digital Video Output B (DVOB) Port353.5.2 Digital Video Output C (DVOC) Port363.5.3 Analog CRT Display373.5.4 General Purpose Input/Output Signals383.6 Voltage References, PLL Power394.0 Register Description414.1 Conceptual Overview of the Platform Configuration Structure414.2 Nomenclature for Access Attributes424.3 Standard PCI Bus Configuration Mechanism434.4 Routing Configuration Accesses434.4.1 PCI Bus #0 Configuration Mechanism434.4.2 Primary PCI and Downstream Configuration Mechanism444.5 Register Definitions444.6 I/O Mapped Registers454.6.1 CONFIG_ADDRESS - Configuration Address Register454.6.2 CONFIG_DATA - Configuration Data Register474.7 VGA I/O Mapped Registers484.8 Intel 854 GMCH Host-Hub Interface Bridge Device Registers (Device #0, Function #0)494.8.1 VID - Vendor Identification Register514.8.2 DID - Device Identification Register514.8.3 PCICMD - PCI Command Register524.8.4 PCI Status Register534.8.5 RID - Register Identification544.8.6 SUBC - Sub Class Code Register544.8.7 BCC - Base Class Code Register554.8.8 HDR - Header Type Register554.8.9 SVID - Subsystem Vendor Identification Register554.8.10 SID - Subsystem Identification Register564.8.11 CAPPTR - Capabilities Pointer Register564.8.12 CAPID - Capabilities Identification Register (Device #0)574.8.13 GMC - GMCH Miscellaneous Control Register (Device #0)584.8.14 GGC - GMCH Graphics Control Register (Device #0)594.8.15 DAFC - Device and Function Control Register (Device #0)604.8.16 FDHC - Fixed DRAM Hold Control Register (Device #0)604.8.17 PAM(6:0) - Programmable Attribute Map Register (Device #0)614.8.18 SMRAM - System Management RAM Control Register (Device #0)644.8.19 ESMRAMC - Extended System Management RAM Control (Device #0)654.8.20 ERRSTS - Error Status Register (Device #0)664.8.21 ERRCMD - Error Command Register (Device #0)674.8.22 SMICMD - SMI Error Command Register (Device #0)684.8.23 SCICMD - SCI Error Command Register (Device #0)694.8.24 SHIC - Secondary Host Interface Control Register (Device #0)704.8.25 HEM - Host Error Control, Status, and Observation (Device #0)714.9 Intel 854 GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function #1)724.9.1 VID - Vendor Identification Register734.9.2 DID - Device Identification Register734.9.3 PCICMD - PCI Command Register744.9.4 PCISTS - PCI Status Register754.9.5 RID - Revision Identification Register764.9.6 RID - Revision Identification Register764.9.7 BCC - Base Class Code Register764.9.8 HDR - Header Type Register774.9.9 SVID - Subsystem Vendor Identification Register774.9.10 SID - Subsystem Identification Register774.9.11 CAPPTR - Capabilities Pointer Register784.9.12 DRB - DRAM Row (0:3) Boundary Register (Device #0)784.9.13 DRA - DRAM Row Attribute Register (Device #0)794.9.14 DRT - DRAM Timing Register (Device #0)804.9.15 PWRMG - DRAM Controller Power Management Control Register (Device #0)834.9.16 DRC - DRAM Controller Mode Register (Device #0)854.9.17 DTC - DRAM Throttling Control Register (Device #0)884.10 Intel 854 GMCH Configuration Process Registers (Device #0, Function #3)924.10.1 VID - Vendor Identification Register924.10.2 DID - Device Identification Register934.10.3 PCICMD - PCI Command Register944.10.4 PCISTS - PCI Status Register954.10.5 RID - Revision Identification Register964.10.6 SUBC - Sub-Class Code Register964.10.7 BCC - Base Class Code Register964.10.8 HDR - Header Type Register974.10.9 SVID - Subsystem Vendor Identification Register974.10.10 ID - Subsystem Identification Register974.10.11 CAPPTR - Capabilities Pointer Register984.10.12 HPLLCC - HPLL Clock Control Register (Device #0)984.11 Intel® 82854 GMCH Integrated Graphics Device Registers (Device #2, Function #0)1004.11.1 VID - Vendor Identification Register (Device #2)1014.11.2 DID - Device Identification Register (Device #2)1014.11.3 PCICMD - PCI Command Register (Device #2)1024.11.4 PCISTS - PCI Status Register (Device #2)1034.11.5 RID - Revision Identification Register (Device #2)1034.11.6 CC - Class Code Register (Device #2)1044.11.7 CLS - Cache Line Size Register (Device #2)1044.11.8 MLT - Master Latency Timer Register (Device #2)1044.11.9 HDR - Header Type Register (Device #2)1054.11.10 GMADR - Graphics Memory Range Address Register (Device #2)1054.11.11 MMADR - Memory Mapped Range Address Register (Device #2)1064.11.12 IOBAR - I/O Base Address Register (Device #2)1064.11.13 SVID - Subsystem Vendor Identification Register (Device #2)1074.11.14 SID - Subsystem Identification Register (Device #2)1074.11.15 ROMADR - Video BIOS ROM Base Address Registers (Device #2)1074.11.16 INTRLINE - Interrupt Line Register (Device #2)1084.11.17 INTRPIN - Interrupt Pin Register (Device #2)1084.11.18 MINGNT - Minimum Grant Register (Device #2)1084.11.19 MAXLAT - Maximum Latency Register (Device #2)1094.11.20 PMCAP - Power Management Capabilities Register (Device #2)1094.11.21 PMCS - Power Management Control/Status Register (Device #2)1105.0 Intel® 82854 GMCH System Address Map1115.1 System Memory Address Ranges1115.2 DOS Compatibility Area1125.3 Extended System Memory Area1145.4 Main System Memory Address Range (0010_0000h to Top of Main Memory)1155.4.1 15 MB-16 MB Window1155.4.2 Pre-allocated System Memory1155.4.3 System Management Mode (SMM) Memory Range1185.4.4 System Memory Shadowing1195.4.5 I/O Address Space1195.4.6 GMCH Decode Rules and Cross-Bridge Address Mapping1205.4.7 Hub Interface Decode Rules1216.0 Functional Description1236.1 Host Interface Overview1236.2 Dynamic Bus Inversion1236.2.1 System Bus Interrupt Delivery1236.2.2 Upstream Interrupt Messages1246.3 System Memory Interface1246.3.1 DDR SDRAM Interface Overview1246.3.2 System Memory Organization and Configuration1246.3.3 DDR SDRAM Performance Description1256.4 Integrated Graphics Overview1266.4.1 3D/2D Instruction Processing1266.4.2 3D Engine1276.4.3 Raster Engine1306.4.4 2D Engine1336.4.5 Planes and Engines1346.4.6 Hardware Cursor Plane (Native Graphic Mode only)1346.4.7 Overlay Plane1356.4.8 Video Functionality1376.5 Internal Graphic Display Interface1386.5.1 Pipe A Timing Generator Unit1386.5.2 Blend Function1416.5.3 Interlaced Video Field display1416.5.4 Interlace support for Video Overlay Window1436.5.5 Analog Display Port Characteristics1457.0 Power and Thermal Management1477.1 General Description of Supported CPU States1487.2 General Description of ACPI States1487.3 Internal Thermal Sensor1497.3.1 Overview1497.3.2 Hysteresis Operation1497.4 External Thermal Sensor Input1507.4.1 Usage1508.0 Intel® 82854 GMCH Strap Pins1518.1 Strapping Configuration1519.0 Ballout and Package Information1539.1 VCC/VSS Voltage Groups1549.2 Package Mechanical Information164Size: 897 KBPages: 166Language: EnglishOpen manual