User ManualTable of ContentsIntel® EP80579 Software for Security Applications on Intel® QuickAssist Technology1Contents3Figures5Tables5Revision History61.0 Introduction71.1 What’s New in this Chapter71.2 About this Document71.3 Where to Find Current Software and Documentation71.4 Related Information81.4.1 Reference Documents81.5 Glossary81.6 Features Supported in this Release10Part 1: Architectural Overview112.0 Silicon Overview122.1 What’s New in this Chapter122.2 High Level Overview123.0 Software Overview143.1 What’s New in this Chapter143.2 Shared Memory Allocation143.3 Logical View153.3.1 Acceleration Firmware Layer153.3.2 Acceleration Access Layer and Acceleration APIs153.3.3 Infrastructure163.3.4 Acceleration System Driver (ASD)163.3.5 Shim Layers173.4 Development View173.5 Process View183.6 Deployment View184.0 Intel® QuickAssist Technology Cryptographic API Architecture Overview204.1 What’s New in this Chapter204.2 Feature List204.2.1 Symmetric Operations204.2.1.1 Cipher204.2.1.2 Hash/Authentication204.2.1.3 Partial Packets for Cipher and Hash/Authentication Commands204.2.1.4 Out-Of-Place Operation Support214.2.1.5 Combined Cipher Hash Commands (Algorithm-Chaining)214.2.1.6 Authenticated-Encryption Commands214.2.1.7 Key Generation224.2.2 Random Number224.2.3 Public Key Operations224.2.3.1 Diffie-Hellman224.2.3.2 RSA224.2.3.3 DSA224.2.3.4 Prime Number224.2.3.5 Large Number224.3 Intel® QuickAssist Technology Cryptographic API Documentation224.4 Lookaside Security Algorithms High Level Overview234.4.1 Lookaside Symmetric Overview234.4.2 Key Generation264.4.3 Lookaside PKE Overview264.4.3.1 Diffie-Hellman Key Exchange264.4.3.2 RSA Cryptographic Standard274.4.3.3 Digital Signature Algorithm274.4.3.4 Prime Number Testing274.4.3.5 Large Number284.4.4 Lookaside Random Overview285.0 QAT Access Layer Architecture Overview295.1 What’s New in this Chapter295.2 Overview296.0 Debug Component Architecture Overview306.1 What’s New in this Chapter306.2 Overview306.3 Version Information306.4 Liveness Detection306.5 Data Structure Dump317.0 ASD Module Architecture Overview327.1 What’s New in this Chapter327.2 Overview327.3 Functional Description327.3.1 Configuration327.4 Boot Time Configuration Instructions348.0 ASD Hardware Services358.1 What’s New in this Chapter358.2 Overview358.3 Functional Description358.3.1 Interrupt Management Services358.3.2 NCDRAM/CDRAM Interface388.3.2.1 Development Board Environment38Part 2: Using the API419.0 Introduction to Use Cases429.1 What’s New in this Chapter429.2 Use Cases429.2.1 Lookaside Acceleration Model4210.0 Programming Model4310.1 What’s New in this Chapter4310.2 Overview4310.3 Intel® QuickAssist Technology API Conventions4310.3.1 Memory Allocation and Ownership4310.3.2 Data Buffer Models4410.3.2.1 Flat Buffers4410.3.2.2 Scatter Gather Lists4410.3.3 Synchronous and Asynchronous Support4410.3.3.1 Asynchronous Operation4410.3.3.2 Synchronous Operation4410.3.4 Pre-Registration4510.4 Other API Conventions4510.4.1 Asynchronous API and Function Completion Callbacks4510.4.2 Memory Allocation and Ownership4610.4.3 Callback Data Structures4610.4.4 Return Codes4711.0 Debugging Applications4811.1 What’s New in this Chapter4811.2 Management Interface Layer (MIL) Introduction4811.2.1 Loading the MIL Application4911.3 MIL User Command Details4911.3.1 help5011.3.2 DebugEnable5011.3.3 DebugDisable5111.3.4 VersionDumpAll5211.3.5 setHC <timeout>5311.3.6 SystemHealthCheck5411.3.7 DataDump5511.3.8 SetFileName <filename>5611.4 APIs5612.0 Using the Intel® QuickAssist Technology Cryptographic API5812.1 What’s New in this Chapter5812.2 Intel® QuickAssist Technology Cryptographic API5812.2.1 Modes of Operation6012.2.1.1 Asynchronous Operation6012.2.1.2 Synchronous Operation6012.2.2 Interrupt Operation6012.2.2.1 Interrupt Coalescing6112.2.3 Engine and Priority Support6112.2.4 Statistics6112.3 Symmetric Cryptographic API Data Flow6112.4 Data Format6412.4.1 Flat Buffers6412.4.2 Buffer List6512.5 Memory Management6512.6 Endianness and Alignment6612.7 High-Level API Flow6612.7.1 Cryptographic API Initialization and Shutdown6612.7.1.1 Initialization6612.7.1.2 Start6612.7.1.3 Stop6712.7.1.4 Shutdown6712.8 Intel® QuickAssist Technology Cryptographic API Data Flow6712.8.1 Completion of an Operation6712.8.2 Symmetric Operations6712.8.2.1 Session Initialization6712.8.2.2 Session Removal6812.8.2.3 Cipher, Hash, Nested and Authentication (Full Packet)6812.8.2.4 Partial Packet Variation (Cipher, Hash, Authentication)6812.8.2.5 Algorithm Chaining and Authenticated-Encryption6912.8.2.6 SSL, TLS Key and MGF Mask Generation6912.8.2.7 Generate Random Data7112.8.3 Asymmetric Operations7112.8.3.1 Test Prime Number7112.8.3.2 Diffie-Hellman Phase 1 Key and Phase 2 Private Key Generation7212.8.3.3 DSA P, G, Y Parameter Generate7212.8.3.4 DSA R, S, R & S Signature Generation7212.8.3.5 DSA Signature Verification7312.8.3.6 RSA Key Generation Type 1 and Type 27312.8.3.7 RSA Encryption and Signature Verification7312.8.3.8 RSA Decryption and Signature Generation7312.8.3.9 Large Number Operations - Modular Exponentiation & Inversion7312.9 Using a Cryptographic Framework7412.10 Accelerating Cryptographic Protocols7412.11 Error Handling75Appendix A NPF Copyright Notice76Size: 684 KBPages: 76Language: EnglishOpen manual
