Intel Evaluation Board for Quad T1/E1 Applications LXD386 User Manuals

Table of Contents

• 1.0 General Description

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  • 1.1 Features

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    • Figure 1. LXD386 Evaluation Board

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• 2.0 Overview

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  • 2.1 LXD386 Packing List

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  • 2.2 Equipment Requirements

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  • 2.3 Control Modes

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  • 2.4 Factory Settings

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• 3.0 Hardware Mode Set-Up and Operation

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  • 3.1 Power Connections

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  • 3.2 Hardware Mode Selection

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  • 3.3 Loopback Mode Selection

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    • Table 1. LOOP/DLOOP Switch Settings

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  • 3.4 Clock Edge Selection

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  • 3.5 Output Enable Selection

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  • 3.6 Code Selection

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  • 3.7 Monitoring Address Selection

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  • 3.8 Jitter Attenuator Selection

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    • Figure 2. Default Switch Settings

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  • 3.9 Line Buildout Selection

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  • 3.10 Master Clock Setup

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    • Table 2. JP5 Jumper Settings

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    • Figure 3. Jumper Block JP5

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  • 3.11 JTAG Boundary Scan Port

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    • Figure 4. Jumper Block JP2

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  • 3.12 Framer/ASIC Connection

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    • Figure 5. Jumper Block JP 31

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  • 3.13 LED Indicators

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  • 3.14 Line Interface

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  • 3.15 Board Protection

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• 4.0 Software Mode Set-Up and Operation

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  • 4.1 i8051 Microcontroller Board

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  • 4.2 Evaluation Board Set-up

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  • 4.3 Test Equipment Connections

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  • 4.4 Power Connections

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  • 4.5 Evaluation Board Software

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  • 4.6 Software Installation and Start-Up

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  • 4.7 Hardware Set-up Screen

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  • 4.8 Quitting the Program

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    • Figure 6. Hardware Set-up Screen

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  • 4.9 Configuration Screen

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    • 4.9.1 Communications Modes

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    • 4.9.2 Registers

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    • 4.9.3 Setting Individual Transceiver Operating Modes

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    • 4.9.4 Apply to all Channels

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    • 4.9.5 Exit

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      • Figure 7. Configuration Screen

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  • 4.10 Registers Screen

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    • 4.10.1 Setting Registers

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    • 4.10.2 Status Indicators

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    • 4.10.3 Control Buttons

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    • 4.10.4 Interrupts

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    • 4.10.5 Reset

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      • Figure 8. Registers Screen

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• 5.0 Evaluation Board Schematics

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  • Figure 9. Evaluation Board Schematic — Data/Control

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  • Figure 10. Evaluation Board Schematic — Line Interface Unit

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  • Figure 11. Evaluation Board Schematic — Monitoring

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  • Figure 12. Evaluation Board Schematic — LOS Detector

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  • Figure 13. Evaluation Board Schematic — Analog

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  • Figure 14. Evaluation Board Schematic — Digital I/O

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