User ManualTable of ContentsINTRODUCTION1GD82559ER Overview1Suggested Reading1GD82559ER ARCHITECTURAL OVERVIEW3Parallel Subsystem Overview3FIFO Subsystem Overview410/100 Mbps Serial CSMA/CD Unit Overview510/100 Mbps Physical Layer Unit5SIGNAL DESCRIPTIONS7Signal Type Definitions7PCI Bus Interface Signals73.2.1 Address and Data Signals73.2.2 Interface Control Signals83.2.3 System and Power Management Signals9Local Memory Interface Signals9Testability Port Signals10PHY Signals11GD82559ER MEDIA ACCESS CONTROL FUNCTIONAL DESCRIPTION1382559ER Initialization134.1.1 Initialization Effects on 82559ER Units13PCI Interface144.2.1 82559ER Bus Operations144.2.2 Clockrun Signal224.2.3 Power Management Event Signal224.2.4 Power States234.2.5 Wake-up Events27Parallel Flash Interface28Serial EEPROM Interface2810/100 Mbps CSMA/CD Unit304.5.1 Full Duplex314.5.2 Flow Control314.5.3 Address Filtering Modifications314.5.4 Long Frame Reception31Media Independent Interface (MII) Management Interface32GD82559ER TEST PORT FUNCTIONALITY33Introduction33Asynchronous Test Mode33Test Function Description3385/8533TriState34Nand - Tree34GD82559ER PHYSICAL LAYER FUNCTIONAL DESCRIPTION37100BASE-TX PHY Unit376.1.1 100BASE-TX Transmit Clock Generation376.1.2 100BASE-TX Transmit Blocks376.1.3 100BASE-TX Receive Blocks406.1.4 100BASE-TX Collision Detection416.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution416.1.6 Auto 10/100 Mbps Speed Selection4110BASE-T Functionality416.2.1 10BASE-T Transmit Clock Generation416.2.2 10BASE-T Transmit Blocks426.2.3 10BASE-T Receive Blocks426.2.4 10BASE-T Collision Detection436.2.5 10BASE-T Link Integrity436.2.6 10BASE-T Jabber Control Function436.2.7 10BASE-T Full Duplex43Auto-Negotiation Functionality436.3.1 Description446.3.2 Parallel Detect and Auto-Negotiation44LED Description45PCI CONFIGURATION REGISTERS47LAN (Ethernet) PCI Configuration Space477.1.1 PCI Vendor ID and Device ID Registers477.1.2 PCI Command Register487.1.3 PCI Status Register497.1.4 PCI Revision ID Register507.1.5 PCI Class Code Register507.1.6 PCI Cache Line Size Register507.1.7 PCI Latency Timer517.1.8 PCI Header Type517.1.9 PCI Base Address Registers517.1.10 PCI Subsystem Vendor ID and Subsystem ID Registers537.1.11 Capability Pointer537.1.12 Interrupt Line Register537.1.13 Interrupt Pin Register547.1.14 Minimum Grant Register547.1.15 Maximum Latency Register547.1.16 Capability ID Register547.1.17 Next Item Pointer547.1.18 Power Management Capabilities Register547.1.19 Power Management Control/Status Register (PMCSR)557.1.20 Data Register56CONTROL/STATUS REGISTERS57LAN (Ethernet) Control/Status Registers578.1.1 System Control Block Status Word588.1.2 System Control Block Command Word598.1.3 System Control Block General Pointer598.1.4 PORT598.1.5 Flash Control Register598.1.6 EEPROM Control Register598.1.7 Management Data Interface Control Register598.1.8 Receive Direct Memory Access Byte Count608.1.9 Early Receive Interrupt608.1.10 Flow Control Register608.1.11 Power Management Driver Register608.1.12 General Control Register618.1.13 General Status Register61Statistical Counters62PHY UNIT REGISTERS65MDI Registers 0 - 7659.1.1 Register 0: Control Register Bit Definitions659.1.2 Register 1: Status Register Bit Definitions669.1.3 Register 2: PHY Identifier Register Bit Definitions679.1.4 Register 3: PHY Identifier Register Bit Definitions679.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions679.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions679.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions68MDI Registers 8 - 1568MDI Register 16 - 31689.3.1 Register 16: PHY Unit Status and Control Register Bit Definitions689.3.2 Register 17: PHY Unit Special Control Bit Definitions699.3.3 Register 18: PHY Address Register709.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions709.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions709.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions709.3.7 Register 22: Receive Symbol Error Counter Bit Definitions70Bit Definitions719.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions719.3.11 Register 26: Equalizer Control and Status Bit Definitions719.3.12 Register 27: PHY Unit Special Control Bit Definitions71ELECTRICAL AND TIMING SPECIFICATIONS73Absolute Maximum Ratings73DC Specifications73AC Specifications76Timing Specifications7710.4.1 Clocks Specifications7710.4.2 Timing Parameters78PACKAGE AND PINOUT INFORMATION8512.1 Package Information8512.2 Pinout Information8612.2.1 GD82559ER Pin Assignments8612.2.2 GD82559ER Ball Grid Array Diagram88Size: 658 KBPages: 94Language: EnglishOpen manual