User Manual (BX80619I73970X)Table of Contents1 Introduction91.1 Processor Feature Details111.1.1 Supported Technologies111.2 Interfaces111.2.1 System Memory Support111.2.2 PCI Express*121.2.3 Direct Media Interface (DMI)141.2.4 Platform Environment Control Interface (PECI)141.2.5 Processor Graphics141.2.6 Intel® Flexible Display Interface (Intel® FDI)151.3 Power Management Support151.3.1 Processor Core151.3.2 System151.3.3 Memory Controller151.3.4 PCI Express*151.3.5 Direct Media Interface (DMI)161.3.6 Processor Graphics Controller (GT)161.3.7 Thermal Management Support161.4 Processor SKU Definitions161.5 Package171.6 Processor Compatibility171.7 Terminology191.8 Related Documents222 Interfaces232.1 System Memory Interface232.1.1 System Memory Technology Supported232.1.2 System Memory Timing Support242.1.3 System Memory Organization Modes252.1.3.1 Single-Channel Mode252.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode252.1.4 Rules for Populating Memory Slots262.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)272.1.5.1 Just-in-Time Command Scheduling272.1.5.2 Command Overlap272.1.5.3 Out-of-Order Scheduling272.1.6 Data Scrambling272.1.7 DDR3 Reference Voltage Generation272.2 PCI Express* Interface282.2.1 PCI Express* Architecture282.2.1.1 Transaction Layer292.2.1.2 Data Link Layer292.2.1.3 Physical Layer292.2.2 PCI Express* Configuration Mechanism302.2.3 PCI Express* Port312.2.3.1 PCI Express* Lanes Connection312.3 Direct Media Interface (DMI)322.3.1 DMI Error Flow322.3.2 Processor / PCH Compatibility Assumptions322.3.3 DMI Link Down322.4 Processor Graphics Controller (GT)332.4.1 3D and Video Engines for Graphics Processing332.4.1.1 3D Engine Execution Units332.4.1.2 3D Pipeline342.4.1.3 Video Engine342.4.1.4 2D Engine352.4.2 Processor Graphics Display362.4.2.1 Display Planes362.4.2.2 Display Pipes372.4.2.3 Display Ports372.4.3 Intel® Flexible Display Interface (Intel® FDI)372.4.4 Multi Graphics Controllers Multi-Monitor Support372.5 Platform Environment Control Interface (PECI)382.6 Interface Clocking382.6.1 Internal Clocking Requirements383 Technologies393.1 Intel® Virtualization Technology (Intel® VT)393.1.1 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Objectives393.1.2 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Features403.1.3 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Objectives403.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features413.1.5 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features Not Supported413.2 Intel® Trusted Execution Technology (Intel® TXT)423.3 Intel® Hyper-Threading Technology (Intel® HT Technology)423.4 Intel® Turbo Boost Technology433.4.1 Intel® Turbo Boost Technology Frequency433.4.2 Intel® Turbo Boost Technology Graphics Frequency433.5 Intel® Advanced Vector Extensions (Intel® AVX)443.6 Security and Cryptography Technologies443.6.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)443.6.2 PCLMULQDQ Instruction443.6.3 RDRAND Instruction453.7 Intel® 64 Architecture x2APIC453.8 Supervisor Mode Execution Protection (SMEP)463.9 Power Aware Interrupt Routing (PAIR)464 Power Management474.1 Advanced Configuration and Power Interface (ACPI) States Supported484.1.1 System States484.1.2 Processor Core / Package Idle States484.1.3 Integrated Memory Controller States484.1.4 PCI Express* Link States494.1.5 Direct Media Interface (DMI) States494.1.6 Processor Graphics Controller States494.1.7 Interface State Combinations494.2 Processor Core Power Management504.2.1 Enhanced Intel® SpeedStep® Technology504.2.2 Low-Power Idle States504.2.3 Requesting Low-Power Idle States524.2.4 Core C-states524.2.4.1 Core C0 State524.2.4.2 Core C1 / C1E State534.2.4.3 Core C3 State534.2.4.4 Core C6 State534.2.4.5 C-State Auto-Demotion534.2.5 Package C-States544.2.5.1 Package C0554.2.5.2 Package C1 / C1E554.2.5.3 Package C3 State564.2.5.4 Package C6 State564.3 Integrated Memory Controller (IMC) Power Management564.3.1 Disabling Unused System Memory Outputs564.3.2 DRAM Power Management and Initialization574.3.2.1 Initialization Role of CKE584.3.2.2 Conditional Self-Refresh584.3.2.3 Dynamic Power Down Operation594.3.2.4 DRAM I/O Power Management594.3.3 DDR Electrical Power Gating (EPG)594.4 PCI Express* Power Management604.5 DMI Power Management604.6 Graphics Power Management604.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR)604.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)604.6.3 Graphics Render C-State604.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)614.6.5 Intel® Graphics Dynamic Frequency614.7 Graphics Thermal Power Management615 Thermal Management636 Signal Description656.1 System Memory Interface Signals666.2 Memory Reference and Compensation Signals676.3 Reset and Miscellaneous Signals686.4 PCI Express*-based Interface Signals696.5 Intel® Flexible Display (Intel® FDI) Interface Signals696.6 Direct Media Interface (DMI) Signals706.7 Phase Lock Loop (PLL) Signals706.8 Test Access Points (TAP) Signals706.9 Error and Thermal Protection Signals716.10 Power Sequencing Signals726.11 Processor Power Signals736.12 Sense Signals736.13 Ground and Non-Critical to Function (NCTF) Signals746.14 Processor Internal Pull-Up / Pull-Down Resistors747 Electrical Specifications757.1 Power and Ground Lands757.2 Decoupling Guidelines757.2.1 Voltage Rail Decoupling757.3 Processor Clocking (BCLK[0], BCLK#[0])767.3.1 Phase Lock Loop (PLL) Power Supply767.4 VCC Voltage Identification (VID)767.5 System Agent (SA) VCC VID807.6 Reserved or Unused Signals807.7 Signal Groups807.8 Test Access Port (TAP) Connection827.9 Storage Conditions Specifications837.10 DC Specifications847.10.1 Voltage and Current Specifications847.11 Platform Environmental Control Interface (PECI) DC Specifications907.11.1 PECI Bus Architecture907.11.2 DC Characteristics917.11.3 Input Device Hysteresis918 Processor Land and Signal Information938.1 Processor Land Assignments939 DDR Data Swizzling109Size: 1.08 MBPages: 112Language: EnglishOpen manual
User Manual (CM8061901281201)Table of Contents1 Introduction91.1 Processor Feature Details111.1.1 Supported Technologies111.2 Interfaces111.2.1 System Memory Support111.2.2 PCI Express*121.2.3 Direct Media Interface (DMI)141.2.4 Platform Environment Control Interface (PECI)141.2.5 Processor Graphics141.2.6 Intel® Flexible Display Interface (Intel® FDI)151.3 Power Management Support151.3.1 Processor Core151.3.2 System151.3.3 Memory Controller151.3.4 PCI Express*151.3.5 Direct Media Interface (DMI)161.3.6 Processor Graphics Controller (GT)161.3.7 Thermal Management Support161.4 Processor SKU Definitions161.5 Package171.6 Processor Compatibility171.7 Terminology191.8 Related Documents222 Interfaces232.1 System Memory Interface232.1.1 System Memory Technology Supported232.1.2 System Memory Timing Support242.1.3 System Memory Organization Modes252.1.3.1 Single-Channel Mode252.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode252.1.4 Rules for Populating Memory Slots262.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)272.1.5.1 Just-in-Time Command Scheduling272.1.5.2 Command Overlap272.1.5.3 Out-of-Order Scheduling272.1.6 Data Scrambling272.1.7 DDR3 Reference Voltage Generation272.2 PCI Express* Interface282.2.1 PCI Express* Architecture282.2.1.1 Transaction Layer292.2.1.2 Data Link Layer292.2.1.3 Physical Layer292.2.2 PCI Express* Configuration Mechanism302.2.3 PCI Express* Port312.2.3.1 PCI Express* Lanes Connection312.3 Direct Media Interface (DMI)322.3.1 DMI Error Flow322.3.2 Processor / PCH Compatibility Assumptions322.3.3 DMI Link Down322.4 Processor Graphics Controller (GT)332.4.1 3D and Video Engines for Graphics Processing332.4.1.1 3D Engine Execution Units332.4.1.2 3D Pipeline342.4.1.3 Video Engine342.4.1.4 2D Engine352.4.2 Processor Graphics Display362.4.2.1 Display Planes362.4.2.2 Display Pipes372.4.2.3 Display Ports372.4.3 Intel® Flexible Display Interface (Intel® FDI)372.4.4 Multi Graphics Controllers Multi-Monitor Support372.5 Platform Environment Control Interface (PECI)382.6 Interface Clocking382.6.1 Internal Clocking Requirements383 Technologies393.1 Intel® Virtualization Technology (Intel® VT)393.1.1 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Objectives393.1.2 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Features403.1.3 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Objectives403.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features413.1.5 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features Not Supported413.2 Intel® Trusted Execution Technology (Intel® TXT)423.3 Intel® Hyper-Threading Technology (Intel® HT Technology)423.4 Intel® Turbo Boost Technology433.4.1 Intel® Turbo Boost Technology Frequency433.4.2 Intel® Turbo Boost Technology Graphics Frequency433.5 Intel® Advanced Vector Extensions (Intel® AVX)443.6 Security and Cryptography Technologies443.6.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)443.6.2 PCLMULQDQ Instruction443.6.3 RDRAND Instruction453.7 Intel® 64 Architecture x2APIC453.8 Supervisor Mode Execution Protection (SMEP)463.9 Power Aware Interrupt Routing (PAIR)464 Power Management474.1 Advanced Configuration and Power Interface (ACPI) States Supported484.1.1 System States484.1.2 Processor Core / Package Idle States484.1.3 Integrated Memory Controller States484.1.4 PCI Express* Link States494.1.5 Direct Media Interface (DMI) States494.1.6 Processor Graphics Controller States494.1.7 Interface State Combinations494.2 Processor Core Power Management504.2.1 Enhanced Intel® SpeedStep® Technology504.2.2 Low-Power Idle States504.2.3 Requesting Low-Power Idle States524.2.4 Core C-states524.2.4.1 Core C0 State524.2.4.2 Core C1 / C1E State534.2.4.3 Core C3 State534.2.4.4 Core C6 State534.2.4.5 C-State Auto-Demotion534.2.5 Package C-States544.2.5.1 Package C0554.2.5.2 Package C1 / C1E554.2.5.3 Package C3 State564.2.5.4 Package C6 State564.3 Integrated Memory Controller (IMC) Power Management564.3.1 Disabling Unused System Memory Outputs564.3.2 DRAM Power Management and Initialization574.3.2.1 Initialization Role of CKE584.3.2.2 Conditional Self-Refresh584.3.2.3 Dynamic Power Down Operation594.3.2.4 DRAM I/O Power Management594.3.3 DDR Electrical Power Gating (EPG)594.4 PCI Express* Power Management604.5 DMI Power Management604.6 Graphics Power Management604.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR)604.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)604.6.3 Graphics Render C-State604.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)614.6.5 Intel® Graphics Dynamic Frequency614.7 Graphics Thermal Power Management615 Thermal Management636 Signal Description656.1 System Memory Interface Signals666.2 Memory Reference and Compensation Signals676.3 Reset and Miscellaneous Signals686.4 PCI Express*-based Interface Signals696.5 Intel® Flexible Display (Intel® FDI) Interface Signals696.6 Direct Media Interface (DMI) Signals706.7 Phase Lock Loop (PLL) Signals706.8 Test Access Points (TAP) Signals706.9 Error and Thermal Protection Signals716.10 Power Sequencing Signals726.11 Processor Power Signals736.12 Sense Signals736.13 Ground and Non-Critical to Function (NCTF) Signals746.14 Processor Internal Pull-Up / Pull-Down Resistors747 Electrical Specifications757.1 Power and Ground Lands757.2 Decoupling Guidelines757.2.1 Voltage Rail Decoupling757.3 Processor Clocking (BCLK[0], BCLK#[0])767.3.1 Phase Lock Loop (PLL) Power Supply767.4 VCC Voltage Identification (VID)767.5 System Agent (SA) VCC VID807.6 Reserved or Unused Signals807.7 Signal Groups807.8 Test Access Port (TAP) Connection827.9 Storage Conditions Specifications837.10 DC Specifications847.10.1 Voltage and Current Specifications847.11 Platform Environmental Control Interface (PECI) DC Specifications907.11.1 PECI Bus Architecture907.11.2 DC Characteristics917.11.3 Input Device Hysteresis918 Processor Land and Signal Information938.1 Processor Land Assignments939 DDR Data Swizzling109Size: 1.08 MBPages: 112Language: EnglishOpen manual
