User Manual (CN80617004857AA)Table of ContentsContents31 Features Summary101.1 Introduction101.2 Processor Feature Details121.2.1 Supported Technologies121.3 Interfaces121.3.1 System Memory Support121.3.2 PCI Express*131.3.3 Direct Media Interface (DMI)141.3.4 Platform Environment Control Interface (PECI)151.3.5 Intel® HD Graphics Controller151.3.6 Embedded DisplayPort* (eDP*)151.3.7 Intel® Flexible Display Interface (Intel® FDI)161.4 Power Management Support161.4.1 Processor Core161.4.2 System161.4.3 Memory Controller161.4.4 PCI Express*161.4.5 DMI161.4.6 Integrated Graphics Controller161.5 Thermal Management Support171.6 Package171.7 Terminology171.8 Related Documents192 Interfaces202.1 System Memory Interface202.1.1 System Memory Technology Supported202.1.2 System Memory Timing Support212.1.3 System Memory Organization Modes212.1.4 Rules for Populating Memory Slots232.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)232.1.6 DRAM Clock Generation242.1.7 System Memory Pre-Charge Power Down Support Details242.2 PCI Express Interface242.2.1 PCI Express Architecture242.2.2 PCI Express Configuration Mechanism262.2.3 PCI Express Graphics272.3 DMI272.3.1 DMI Error Flow272.3.2 Processor/PCH Compatibility Assumptions272.3.3 DMI Link Down272.4 Integrated Graphics Controller272.4.1 3D and Video Engines for Graphics Processing282.4.2 Integrated Graphics Display Pipes302.4.3 Intel Flexible Display Interface322.5 Platform Environment Control Interface (PECI)332.6 Interface Clocking332.6.1 Internal Clocking Requirements333 Technologies343.1 Intel® Virtualization Technology (Intel® VT)343.1.1 Intel® VT-x Objectives343.1.2 Intel VT-x Features353.1.3 Intel® VT-d Objectives353.1.4 Intel VT-d Features Supported363.1.5 Intel VT-d Features Not Supported363.2 Intel® Trusted Execution Technology (Intel® TXT)373.3 Intel® Hyper-Threading Technology373.4 Intel® Turbo Boost Technology383.4.1 Intel Turbo Boost Technology Processor Frequency383.4.2 Intel HD Graphics with Dynamic Frequency383.5 New Instructions393.5.1 Advanced Encryption Standard New Instructions (AESNI)393.5.2 PCLMULQDQ Instruction394 Power Management404.1 ACPI States Supported404.1.1 System States404.1.2 Processor Core/Package Idle States404.1.3 Integrated Memory Controller States414.1.4 PCIe Link States414.1.5 DMI States414.1.6 Integrated Graphics Controller States414.1.7 Interface State Combinations424.2 Processor Core Power Management424.2.1 Enhanced Intel SpeedStep® Technology434.2.2 Low-Power Idle States434.2.3 Requesting Low-Power Idle States444.2.4 Core C-states454.2.5 Package C-States464.3 IMC Power Management494.3.1 Disabling Unused System Memory Outputs494.3.2 DRAM Power Management and Initialization494.4 PCIe Power Management514.5 DMI Power Management514.6 Integrated Graphics Power Management514.6.1 Intel® Display Power Saving Technology 5.0 (Intel® DPST 5.0)514.6.2 Graphics Render C-State514.6.3 Graphics Performance Modulation Technology514.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)514.7 Thermal Power Management525 Thermal Management535.1 Thermal Design Power and Junction Temperature535.1.1 Intel Turbo Boost Technology and Graphics Dynamic Frequency535.1.2 Intel Turbo Boost Technology and Graphics Dynamic Frequency Thermal Design Considerations and Specifications545.1.3 Idle Power Specifications565.1.4 Intel Turbo Boost Technology Control Overview575.1.5 Component Power Measurement/Estimation Error575.2 Thermal Management Features585.2.1 Processor Core Thermal Features585.2.2 Integrated Graphics and Memory Controller Thermal Features635.2.3 Platform Environment Control Interface (PECI)666 Signal Description686.1 System Memory Interface696.2 Memory Reference and Compensation716.3 Reset and Miscellaneous Signals726.4 PCI Express Graphics Interface Signals736.5 Embedded DisplayPort (eDP)746.6 Intel Flexible Display Interface Signals756.7 DMI756.8 PLL Signals766.9 TAP Signals766.10 Error and Thermal Protection776.11 Power Sequencing786.12 Processor Power Signals796.13 Ground and NCTF816.14 Processor Internal Pull Up/Pull Down827 Electrical Specifications837.1 Power and Ground Pins837.2 Decoupling Guidelines837.2.1 Voltage Rail Decoupling837.3 Processor Clocking (BCLK, BCLK#)837.3.1 PLL Power Supply837.4 Voltage Identification (VID)847.5 Reserved or Unused Signals887.6 Signal Groups897.7 Test Access Port (TAP) Connection917.8 Absolute Maximum and Minimum Ratings927.9 Storage Conditions Specifications927.10 DC Specifications937.10.1 Voltage and Current Specifications947.11 Platform Environmental Control Interface (PECI) DC Specifications1037.11.1 DC Characteristics1037.11.2 Input Device Hysteresis1048 Processor Pin and Signal Information1058.1 Processor Pin Assignments1058.2 Package Mechanical Information178Size: 1.55 MBPages: 181Language: EnglishOpen manual