Intel Video Game Controller Intel Gigabit Ethernet Controllers User Manuals

Table of Contents

• Introduction 1

  15
  • 1.1 Scope

    15
  • 1.2 Overview

    15
  • 1.3 Ethernet Controller Features

    16
    • 1.3.1 PCI Features

      16
    • 1.3.2 CSA Features (82547GI/EI Only)

      16
    • 1.3.3 Network Side Features

      16
    • 1.3.4 Host Offloading Features

      17
    • 1.3.5 Additional Performance Features

      18
    • 1.3.6 Manageability Features (Not Applicable to the 82544GC/EI or 82541ER)

      19
    • 1.3.7 Additional Ethernet Controller Features

      19
    • 1.3.8 Technology Features

      19
  • 1.4 Conventions

    20
    • 1.4.1 Register and Bit References

      20
    • 1.4.2 Byte and Bit Designations

      20
  • 1.5 Related Documents

    20
  • 1.6 Memory Alignment Terminology

    20
• Architectural Overview 2

  21
  • 2.1 Introduction

    21
  • 2.2 External Architecture

    22
  • 2.3 Microarchitecture

    24
    • 2.3.1 PCI/PCI-X Core Interface

      24
    • 2.3.2 82547GI/EI CSA Interface

      25
    • 2.3.3 DMA Engine and Data FIFO

      25
    • 2.3.4 10/100/1000 Mb/s Receive and Transmit MAC Blocks

      26
    • 2.3.5 MII/GMII/TBI/Internal SerDes Interface Block

      26
    • 2.3.6 10/100/1000 Ethernet Transceiver (PHY)

      27
    • 2.3.7 EEPROM Interface

      27
    • 2.3.8 FLASH Memory Interface

      28
  • 2.4 DMA Addressing

    28
  • 2.5 Ethernet Addressing

    29
  • 2.6 Interrupts

    30
  • 2.7 Hardware Acceleration Capability

    31
    • 2.7.1 Checksum Offloading

      31
    • 2.7.2 TCP Segmentation

      31
  • 2.8 Buffer and Descriptor Structure

    31
• Receive and Transmit Description 3

  33
  • 3.1 Introduction

    33
  • 3.2 Packet Reception

    33
    • 3.2.1 Packet Address Filtering

      33
    • 3.2.2 Receive Data Storage

      34
    • 3.2.3 Receive Descriptor Format

      34
      • 3.2.3.1 Receive Descriptor Status Field

        35
      • 3.2.3.2 Receive Descriptor Errors Field

        36
      • 3.2.3.3 Receive Descriptor Special Field

        38
    • 3.2.4 Receive Descriptor Fetching

      39
    • 3.2.5 Receive Descriptor Write-Back

      40
      • 3.2.5.1 Receive Descriptor Packing

        40
      • 3.2.5.2 Null Descriptor Padding

        40
    • 3.2.6 Receive Descriptor Queue Structure

      40
    • 3.2.7 Receive Interrupts

      42
      • 3.2.7.1 Receive Timer Interrupt

        42
      • 3.2.7.2 Small Receive Packet Detect

        44
      • 3.2.7.3 Receive Descriptor Minimum Threshold (ICR.RXDMT)

        45
      • 3.2.7.4 Receiver FIFO Overrun

        45
    • 3.2.8 82544GC/EI Receive Interrupts

      45
    • 3.2.9 Receive Packet Checksum Offloading

      45
      • 3.2.9.1 MAC Address Filter

        47
      • 3.2.9.2 SNAP/VLAN Filter

        48
      • 3.2.9.3 IPv4 Filter

        48
      • 3.2.9.4 IPv6 Filter

        48
      • 3.2.9.5 UDP/TCP Filter

        48
  • 3.3 Packet Transmission

    48
    • 3.3.1 Transmit Data Storage

      49
    • 3.3.2 Transmit Descriptors

      49
    • 3.3.3 Legacy Transmit Descriptor Format

      50
      • 3.3.3.1 Transmit Descriptor Command Field Format

        52
      • 3.3.3.2 Transmit Descriptor Status Field Format

        53
    • 3.3.4 Transmit Descriptor Special Field Format

      54
    • 3.3.5 TCP/IP Context Transmit Descriptor Format

      55
    • 3.3.6 TCP/IP Context Descriptor Layout

      56
      • 3.3.6.1 TCP/UDP Offload Transmit Descriptor Command Field

        58
      • 3.3.6.2 TCP/UDP Offload Transmit Descriptor Status Field

        60
    • 3.3.7 TCP/IP Data Descriptor Format

      60
      • 3.3.7.1 TCP/IP Data Descriptor Command Field

        62
      • 3.3.7.2 TCP/IP Data Descriptor Status Field

        63
      • 3.3.7.3 TCP/IP Data Descriptor Option Field

        64
      • 3.3.7.4 TCP/IP Data Descriptor Special Field

        64
  • 3.4 Transmit Descriptor Ring Structure

    65
    • 3.4.1 Transmit Descriptor Fetching

      67
    • 3.4.2 Transmit Descriptor Write-back

      67
    • 3.4.3 Transmit Interrupts

      68
      • 3.4.3.1 Delayed Transmit Interrupts

        69
  • 3.5 TCP Segmentation

    69
    • 3.5.1 Assumptions

      70
    • 3.5.2 Transmission Process

      70
      • 3.5.2.1 TCP Segmentation Data Fetch Control

        71
    • 3.5.3 TCP Segmentation Performance

      71
    • 3.5.4 Packet Format

      71
    • 3.5.5 TCP Segmentation Indication

      72
    • 3.5.6 TCP Segmentation Use of Multiple Data Descriptors

      73
    • 3.5.7 IP and TCP/UDP Headers

      74
    • 3.5.8 Transmit Checksum Offloading with TCP Segmentation

      78
    • 3.5.9 IP/TCP/UDP Header Updating

      79
      • 3.5.9.1 TCP/IP/UDP Header for the First Frame

        81
      • 3.5.9.2 TCP/IP/UDP Header for the Subsequent Frames

        81
      • 3.5.9.3 TCP/IP/UDP Header for the Last Frame

        82
  • 3.6 IP/TCP/UDP Transmit Checksum Offloading

    82
• PCI Local Bus Interface 4

  85
  • 4.1 PCI Configuration

    85
    • 4.1.1 PCI-X Configuration Registers

      93
      • 4.1.1.1 PCI-X Capability ID

        93
      • 4.1.1.2 Next Capability

        93
      • 4.1.1.3 PCI-X Command

        94
      • 4.1.1.4 PCI-X Status

        95
    • 4.1.2 Reserved and Undefined Addresses

      96
    • 4.1.3 Message Signaled Interrupts

      97
      • 4.1.3.1 Message Signaled Interrupt Configuration Registers

        97
  • 4.2 Commands

    99
  • 4.3 PCI/PCI-X Command Usage

    101
    • 4.3.1 Memory Write Operations

      101
      • 4.3.1.1 MWI Bursts

        102
      • 4.3.1.2 MW Bursts

        103
    • 4.3.2 Memory Read Operations

      103
      • 4.3.2.1 PCI-X Command Usage

        103
  • 4.4 Cache Line Information

    104
    • 4.4.1 Target Transaction Termination

      105
  • 4.5 Interrupt Assignment (82547GI/EI Only)

    105
  • 4.6 LAN Disable

    105
  • 4.7 CardBus Application (82541PI/GI/EI Only)

    106
• EEPROM Interface 5

  107
  • 5.1 General Overview

    107
  • 5.2 Component Identification Via Programming Interface

    108
  • 5.3 EEPROM Device and Interface

    109
    • 5.3.1 Software Access

      110
  • 5.4 Signature and CRC Fields

    110
  • 5.5 EEUPDATE Utility

    111
    • 5.5.1 Command Line Parameters

      111
  • 5.6 EEPROM Address Map

    112
    • 5.6.1 Ethernet Address (Words 00h-02h)

      117
    • 5.6.2 Software Compatibility Word (Word 03h)

      117
    • 5.6.3 SerDes Configuration (Word 04h)

      118
    • 5.6.4 EEPROM Image Version (Word 05h)

      118
    • 5.6.5 Compatibility Fields (Word 05h - 07h)

      118
    • 5.6.6 PBA Number (Word 08h, 09h)

      118
    • 5.6.7 Initialization Control Word 1 (Word 0Ah)

      119
    • 5.6.8 Subsystem ID (Word 0Bh)

      120
    • 5.6.9 Subsystem Vendor ID (Word 0Ch)

      120
    • 5.6.10 Device ID (Word 0Dh, 11h)

      121
    • 5.6.11 Vendor ID (Word 0Eh)

      121
    • 5.6.12 Initialization Control Word 2 (Word 0Fh)

      121
    • 5.6.13 PHY Register Address Data (Words 10h, 11h, and 13h - 1Eh)

      123
    • 5.6.14 OEM Reserved Words (Words 10h, 11h, 13h - 1Fh)

      123
    • 5.6.15 EEPROM Size (Word 12h)

      123
    • 5.6.16 Common Power (Word 12h)

      123
    • 5.6.17 Software Defined Pins Control (Word 10h, 20h)

      123
    • 5.6.18 CSA Port Configuration 2 (Word 21h)

      125
    • 5.6.19 Circuit Control (Word 21h)

      126
    • 5.6.20 D0 Power (Word 22h high byte)

      126
    • 5.6.21 D3 Power (Word 22h low byte)

      126
    • 5.6.22 Reserved Words (23h - 2Eh)

      126
    • 5.6.23 Reserved Words (23h - 2Fh)

      126
    • 5.6.24 Management Control (Word 13h, 23h)

      127
    • 5.6.25 SMBus Slave Address (Word 14h low byte, 24h low byte)

      128
    • 5.6.26 Initialization Control 3 (Word 14h high byte, 24h high byte)

      129
    • 5.6.27 IPv4 Address (Words 15h - 16h and 25h - 26h)

      130
    • 5.6.28 IPv6 Address (words 17h - 1Eh1 and 27h - 2Eh)

      130
    • 5.6.29 LED Configuration Defaults (Word 2Fh)

      130
    • 5.6.30 Boot Agent Main Setup Options (Word 30h)

      130
    • 5.6.31 Boot Agent Configuration Customization Options (Word 31h)

      132
    • 5.6.32 Boot Agent Configuration Customization Options (Word 32h)

      134
    • 5.6.33 IBA Capabilities (Word 33h)

      135
    • 5.6.34 IBA Secondary Port Configuration (Words 34h-35h)

      135
    • 5.6.35 Checksum Word Calculation (Word 3Fh)

      136
    • 5.6.36 82546GB/EB Dual-Channel Fiber Wake on LAN (WOL) Mode and Functionality (Word 0Ah, 20h)

      136
    • 5.6.37 EEPROM Images

      136
  • 5.7 Parallel FLASH Memory

    137
• FLASH Memory Interface 7

  139
  • 7.1 FLASH Interface Operation

    139
  • 7.2 FLASH Control and Accesses

    139
    • 7.2.1 Read Accesses

      140
    • 7.2.2 Write Accesses

      140
• Power Management 6

  143
  • 6.1 Introduction to Power Management

    143
  • 6.2 Assumptions

    143
  • 6.3 D3cold support

    144
    • 6.3.1 Power States

      144
      • 6.3.1.1 Dr State

        145
      • 6.3.1.2 D0u State

        145
      • 6.3.1.3 D0a (D0 active)

        146
      • 6.3.1.4 D3

        146
    • 6.3.2 Timing

      146
      • 6.3.2.1 Power Up (Off to Dr to D0u to D0a)

        147
      • 6.3.2.2 Transition From D0a to D3 and Back Without PCI Reset

        148
      • 6.3.2.3 Transition From D0a to D3 and Back with PCI Reset

        149
      • 6.3.2.4 PCI Reset Without Transition to D3

        150
    • 6.3.3 PCI Power Management Registers

      151
      • 6.3.3.1 Capability ID 1 Byte Offset = 0 (RO)

        151
      • 6.3.3.2 Next Item Pointer 1 Byte Offset = 1 (RO)

        151
      • 6.3.3.3 Power Management Capabilities - (PMC) 2 Bytes Offset = 2 (RO)

        152
      • 6.3.3.4 Power Management Control / Status Register - (PMCSR) 2 Bytes Offset = 4 (RO)

        153
      • 6.3.3.5 PMCSR_BSE Bridge Support Extensions 1 Byte Offset = 6 (RO)

        154
      • 6.3.3.6 Data Register 1 Byte Offset = 7 (RO)

        154
  • 6.4 Wakeup

    155
    • 6.4.1 Advanced Power Management Wakeup

      155
    • 6.4.2 ACPI Power Management Wakeup

      156
    • 6.4.3 Wakeup Packets

      157
      • 6.4.3.1 Pre-Defined Filters

        157
      • 6.4.3.2 Directed IPv6 Packet

        162
      • 6.4.3.3 Flexible Filter

        163
      • 6.4.3.4 IPv6 Neighbor Discovery Filter

        164
      • 6.4.3.5 Wakeup Packet Storage

        165
• Ethernet Interface 8

  167
  • 8.1 Introduction

    167
  • 8.2 Link Interfaces Overview

    167
    • 8.2.1 Internal SerDes Interface/TBI Mode- 1Gb/s

      168
      • 8.2.1.1 Gigabit Physical Coding Sub-Layer (PCS) for the Internal SerDes

        168
      • 8.2.1.2 8B10B Encoding/Decoding

        168
      • 8.2.1.3 Code Groups and Ordered Sets

        169
    • 8.2.2 GMII - 1 Gb/s

      169
    • 8.2.3 MII - 10/100 Mb/s

      170
  • 8.3 Internal Interface

    170
  • 8.4 Duplex Operation

    170
    • 8.4.1 Full Duplex

      171
    • 8.4.2 Half Duplex

      171
      • 8.4.2.1 Carrier Extension (1000 Mb/s Only)

        172
      • 8.4.2.2 Packet Bursting

        172
  • 8.5 Auto-Negotiation and Link Setup

    173
  • 8.6 Auto-Negotiation and Link Setup

    173
    • 8.6.1 Link Configuration in Internal Serdes/TBI Mode

      174
      • 8.6.1.1 Link Speed

        174
      • 8.6.1.2 Auto-Negotiation

        174
      • 8.6.1.3 Hardware Auto-Negotiation

        175
      • 8.6.1.4 Software Auto-Negotiation

        176
      • 8.6.1.5 Forcing Link

        177
    • 8.6.2 Internal GMII/MII Mode

      177
      • 8.6.2.1 Auto-Negotiation

        177
      • 8.6.2.2 Link Speed

        178
      • 8.6.2.3 Duplex

        179
      • 8.6.2.4 MII Management Registers

        179
      • 8.6.2.5 Comments Regarding Forcing Link

        179
    • 8.6.3 Internal SerDes Mode Control Bit Resolution

      180
    • 8.6.4 Internal PHY Mode Control Bit Resolution

      181
    • 8.6.5 Loss of Signal/Link Status Indication

      183
      • 8.6.5.1 Internal Serdes Mode

        183
      • 8.6.5.2 Internal PHY Mode

        183
  • 8.7 10/100 Mb/s Specific Performance Enhancements

    184
    • 8.7.1 Adaptive IFS

      184
    • 8.7.2 Flow Control

      185
    • 8.7.3 MAC Control Frames & Reception of Flow Control Packets

      185
    • 8.7.4 Discard PAUSE Frames and Pass MAC Control Frames

      187
    • 8.7.5 Transmission of PAUSE Frames

      187
    • 8.7.6 Software Initiated PAUSE Frame Transmission

      188
    • 8.7.7 External Control of Flow Control Operation

      188
• 802.1q VLAN Support 9

  189
  • 9.1 802.1q VLAN Packet Format

    189
    • 9.1.1 802.1q Tagged Frames

      189
  • 9.2 Transmitting and Receiving 802.1q Packets

    190
    • 9.2.1 Adding 802.1q Tags on Transmits

      190
    • 9.2.2 Stripping 802.1q Tags on Receives

      190
  • 9.3 802.1q VLAN Packet Filtering

    190
• Configurable LED Outputs 10

  193
  • 10.1 Configurable LED Outputs

    193
    • 10.1.1 Selecting an LED Output Source

      193
    • 10.1.2 Polarity Inversion

      194
    • 10.1.3 Blink Control

      194
• PHY Functionality and Features 11

  197
  • 11.1 Auto-Negotiation

    197
    • 11.1.1 Overview

      197
    • 11.1.2 Next Page Exchanges

      198
    • 11.1.3 Register Update

      198
    • 11.1.4 Status

      199
  • 11.2 MDI/MDI-X Crossover (copper only)

    199
    • 11.2.1 Polarity Correction (copper only)

      200
    • 11.2.2 10/100 Downshift (82540EP/EM Only)

      200
  • 11.3 Cable Length Detection (copper only)

    201
  • 11.4 PHY Power Management (copper only)

    201
    • 11.4.1 Link Down - Energy Detect (copper only)

      201
    • 11.4.2 D3 State, No Link Required (copper only)

      202
    • 11.4.3 D3 Link-Up, Speed-Management Enabled (copper only)

      202
    • 11.4.4 D3 Link-Up, Speed-Management Disabled (copper only)

      202
  • 11.5 Initialization

    203
    • 11.5.1 MDIO Control Mode

      203
  • 11.6 Determining Link State

    204
    • 11.6.1 False Link

      205
    • 11.6.2 Forced Operation

      205
    • 11.6.3 Auto Negotiation

      206
    • 11.6.4 Parallel Detection

      206
  • 11.7 Link Criteria

    206
    • 11.7.1 1000BASE-T

      206
    • 11.7.2 100BASE-TX

      206
    • 11.7.3 10BASE-T

      207
  • 11.8 Link Enhancements

    207
    • 11.8.1 SmartSpeed

      207
      • 11.8.1.1 Using SmartSpeed

        207
    • 11.8.2 Flow Control

      207
  • 11.9 Management Data Interface

    208
  • 11.10 Low Power Operation

    208
    • 11.10.1 Powerdown via the PHY Register

      209
    • 11.10.2 Smart Power-Down

      209
  • 11.11 1000 Mbps Operation

    209
    • 11.11.1 Introduction

      209
    • 11.11.2 Transmit Functions

      211
      • 11.11.2.1 Scrambler

        211
    • 11.11.3 Transmit FIFO

      211
      • 11.11.3.1 Transmit Phase-Locked Loop PLL

        211
      • 11.11.3.2 Trellis Encoder

        211
      • 11.11.3.3 4DPAM5 Encoder

        211
      • 11.11.3.4 Spectral Shaper

        212
      • 11.11.3.5 Low-Pass Filter

        212
      • 11.11.3.6 Line Driver

        212
      • 11.11.3.7 Transmit/Receive Flow

        212
    • 11.11.4 Receive Functions

      213
      • 11.11.4.1 Hybrid

        213
      • 11.11.4.2 Automatic Gain Control

        213
      • 11.11.4.3 Timing Recovery

        213
      • 11.11.4.4 Analog-to-Digital Converter

        213
      • 11.11.4.5 Digital Signal Processor

        213
      • 11.11.4.6 Descrambler

        214
      • 11.11.4.7 Viterbi Decoder/Decision Feedback Equalizer (DFE)

        214
      • 11.11.4.8 4DPAM5 Decoder

        214
  • 11.12 100 Mbps Operation

    214
  • 11.13 10 Mbps Operation

    214
    • 11.13.1 Link Test

      215
    • 11.13.2 10Base-T Link Failure Criteria and Override

      215
    • 11.13.3 Jabber

      215
    • 11.13.4 Polarity Correction

      215
    • 11.13.5 Dribble Bits

      215
  • 11.14 PHY Line Length Indication

    215
• Dual Port Characteristics 12

  217
  • 12.1 Introduction

    217
  • 12.2 Features of Each MAC

    217
    • 12.2.1 PCI/PCI-X interface

      217
    • 12.2.2 MAC Configuration Register Space

      219
    • 12.2.3 SDP, LED, INT# output

      219
  • 12.3 Shared EEPROM

    220
    • 12.3.1 EEPROM Map

      220
    • 12.3.2 EEPROM Arbitration

      220
  • 12.4 Shared FLASH

    221
    • 12.4.1 FLASH Access Contention

      221
  • 12.5 LAN Disable

    222
    • 12.5.1 Overview

      222
    • 12.5.2 Values Sampled on Reset

      222
    • 12.5.3 Multi-Function Advertisement

      223
    • 12.5.4 Interrupt Use

      223
    • 12.5.5 Power Reporting

      223
    • 12.5.6 Summary

      224
• Register Descriptions 13

  225
  • 13.1 Introduction

    225
  • 13.2 Register Conventions

    225
    • 13.2.1 Memory and I/O Address Decoding

      226
      • 13.2.1.1 Memory-Mapped Access to Internal Registers and Memories

        226
      • 13.2.1.2 Memory-Mapped Access to FLASH

        226
      • 13.2.1.3 Memory-Mapped Access to Expansion ROM

        226
    • 13.2.2 I/O-Mapped Internal Register, Internal Memory, and Flash

      227
      • 13.2.2.1 IOADDR

        227
      • 13.2.2.2 IODATA

        227
  • 13.3 PCI-X Register Access Split

    233
  • 13.4 Main Register Descriptions

    234
    • 13.4.1 Device Control Register

      234
    • 13.4.2 Device Status Register

      239
    • 13.4.3 EEPROM/Flash Control & Data Register

      242
    • 13.4.4 EEPROM Read Register

      244
    • 13.4.5 Flash Access

      246
    • 13.4.6 Extended Device Control Register

      247
    • 13.4.7 MDI Control Register

      252
      • 13.4.7.1 PHY Registers

        254
    • 13.4.8 Flow Control Address Low

      293
    • 13.4.9 Flow Control Address High

      293
    • 13.4.10 Flow Control Type

      294
    • 13.4.11 VLAN Ether Type

      294
    • 13.4.12 Flow Control Transmit Timer Value

      295
    • 13.4.13 Transmit Configuration Word Register

      296
    • 13.4.14 Receive Configuration Word Register

      297
    • 13.4.15 LED Control

      299
      • 13.4.15.1 MODE Encodings for LED Outputs1

        300
    • 13.4.16 Packet Buffer Allocation

      302
    • 13.4.17 Interrupt Cause Read Register

      303
    • 13.4.18 Interrupt Throttling Register

      305
    • 13.4.19 Interrupt Cause Set Register

      306
    • 13.4.20 Interrupt Mask Set/Read Register

      307
    • 13.4.21 Interrupt Mask Clear Register

      308
    • 13.4.22 Receive Control Register

      310
    • 13.4.23 Flow Control Receive Threshold Low

      314
    • 13.4.24 Flow Control Receive Threshold High

      315
    • 13.4.25 Receive Descriptor Base Address Low

      316
    • 13.4.26 Receive Descriptor Base Address High

      316
    • 13.4.27 Receive Descriptor Length

      317
    • 13.4.28 Receive Descriptor Head

      317
    • 13.4.29 Receive Descriptor Tail

      318
    • 13.4.30 Receive Delay Timer Register

      318
    • 13.4.31 Receive Interrupt Absolute Delay Timer

      319
    • 13.4.32 Receive Small Packet Detect Interrupt

      320
    • 13.4.33 Transmit Control Register

      320
    • 13.4.34 Transmit IPG Register

      322
    • 13.4.35 Adaptive IFS Throttle - AIT

      324
    • 13.4.36 Transmit Descriptor Base Address Low

      325
    • 13.4.37 Transmit Descriptor Base Address High

      326
    • 13.4.38 Transmit Descriptor Length

      326
    • 13.4.39 Transmit Descriptor Head

      327
    • 13.4.40 Transmit Descriptor Tail

      328
    • 13.4.41 Transmit Interrupt Delay Value

      328
    • 13.4.42 TX DMA Control (82544GC/EI only)

      329
    • 13.4.43 Transmit Descriptor Control

      329
    • 13.4.44 Transmit Absolute Interrupt Delay Value

      331
    • 13.4.45 TCP Segmentation Pad And Minimum Threshold

      332
    • 13.4.46 Receive Descriptor Control

      334
    • 13.4.47 Receive Checksum Control

      335
  • 13.5 Filter Registers

    337
    • 13.5.1 Multicast Table Array

      337
    • 13.5.2 Receive Address Low

      339
    • 13.5.3 Receive Address High

      339
    • 13.5.4 VLAN Filter Table Array

      340
  • 13.6 Wakeup Registers

    341
    • 13.6.1 Wakeup Control Register

      341
    • 13.6.2 Wakeup Filter Control Register

      342
    • 13.6.3 Wakeup Status Register

      343
    • 13.6.4 IP Address Valid

      345
    • 13.6.5 IPv4 Address Table

      346
    • 13.6.6 IPv6 Address Table

      347
    • 13.6.7 Wakeup Packet Length

      348
    • 13.6.8 Wakeup Packet Memory (128 Bytes)

      348
    • 13.6.9 Flexible Filter Length Table

      348
    • 13.6.10 Flexible Filter Mask Table

      349
    • 13.6.11 Flexible Filter Value Table

      350
  • 13.7 Statistics Registers

    350
    • 13.7.1 CRC Error Count

      351
    • 13.7.2 Alignment Error Count

      351
    • 13.7.3 Symbol Error Count

      352
    • 13.7.4 RX Error Count

      352
    • 13.7.5 Missed Packets Count

      353
    • 13.7.6 Single Collision Count

      353
    • 13.7.7 Excessive Collisions Count

      354
    • 13.7.8 Multiple Collision Count

      354
    • 13.7.9 Late Collisions Count

      355
    • 13.7.10 Collision Count

      355
    • 13.7.11 Defer Count

      356
    • 13.7.12 Transmit with No CRS

      356
    • 13.7.13 Sequence Error Count

      357
    • 13.7.14 Carrier Extension Error Count

      357
    • 13.7.15 Receive Length Error Count

      358
    • 13.7.16 XON Received Count

      358
    • 13.7.17 XON Transmitted Count

      359
    • 13.7.18 XOFF Received Count

      359
    • 13.7.19 XOFF Transmitted Count

      359
    • 13.7.20 FC Received Unsupported Count

      360
    • 13.7.21 Packets Received (64 Bytes) Count

      360
    • 13.7.22 Packets Received (65-127 Bytes) Count

      361
    • 13.7.23 Packets Received (128-255 Bytes) Count

      361
    • 13.7.24 Packets Received (256-511 Bytes) Count

      362
    • 13.7.25 Packets Received (512-1023 Bytes) Count

      362
    • 13.7.26 Packets Received (1024 to Max Bytes) Count

      363
    • 13.7.27 Good Packets Received Count

      363
    • 13.7.28 Broadcast Packets Received Count

      364
    • 13.7.29 Multicast Packets Received Count

      364
    • 13.7.30 Good Packets Transmitted Count

      365
    • 13.7.31 Good Octets Received Count

      365
    • 13.7.32 Good Octets Transmitted Count

      366
    • 13.7.33 Receive No Buffers Count

      366
    • 13.7.34 Receive Undersize Count

      367
    • 13.7.35 Receive Fragment Count

      367
    • 13.7.36 Receive Oversize Count

      368
    • 13.7.37 Receive Jabber Count

      368
    • 13.7.38 Management Packets Received Count

      369
    • 13.7.39 Management Packets Dropped Count1

      370
    • 13.7.40 Management Pkts Transmitted Count

      370
    • 13.7.41 Total Octets Received

      370
    • 13.7.42 Total Octets Transmitted

      371
    • 13.7.43 Total Packets Received

      372
    • 13.7.44 Total Packets Transmitted

      372
    • 13.7.45 Packets Transmitted (64 Bytes) Count

      373
    • 13.7.46 Packets Transmitted (65-127 Bytes) Count

      373
    • 13.7.47 Packets Transmitted (128-255 Bytes) Count

      374
    • 13.7.48 Packets Transmitted (256-511 Bytes) Count

      374
    • 13.7.49 Packets Transmitted (512-1023 Bytes) Count

      375
    • 13.7.50 Packets Transmitted (1024 Bytes or Greater) Count

      375
    • 13.7.51 Multicast Packets Transmitted Count

      376
    • 13.7.52 Broadcast Packets Transmitted Count

      376
    • 13.7.53 TCP Segmentation Context Transmitted Count

      377
    • 13.7.54 TCP Segmentation Context Transmit Fail Count

      377
  • 13.8 Diagnostics Registers

    378
    • 13.8.1 Receive Data FIFO Head Register

      378
    • 13.8.2 Receive Data FIFO Tail Register

      378
    • 13.8.3 Receive Data FIFO Head Saved Register

      379
    • 13.8.4 Receive Data FIFO Tail Saved Register

      379
    • 13.8.5 Receive Data FIFO Packet Count

      380
    • 13.8.6 Transmit Data FIFO Head Register

      380
    • 13.8.7 Transmit Data FIFO Tail Register

      381
    • 13.8.8 Transmit Data FIFO Head Saved Register

      381
    • 13.8.9 Transmit Data FIFO Tail Saved Register

      382
    • 13.8.10 Transmit Data FIFO Packet Count

      382
    • 13.8.11 Packet Buffer Memory

      383
• General Initialization and Reset Operation 14

  385
  • 14.1 Introduction

    385
  • 14.2 Power Up State

    385
  • 14.3 General Configuration

    385
  • 14.4 Receive Initialization

    386
  • 14.5 Transmit Initialization

    387
    • 14.5.1 Signal Interface

      390
    • 14.5.2 GMII/MII Features not Supported

      391
    • 14.5.3 Avoiding GMII Test Mode(s)

      392
    • 14.5.4 MAC Configuration

      392
    • 14.5.5 Link Setup

      393
  • 14.6 PHY Initialization (10/100/1000 Mb/s Copper Media)

    394
  • 14.7 Reset Operation

    395
  • 14.8 Initialization of Statistics

    398
• Diagnostics and Testability 15

  399
  • 15.1 Diagnostics

    399
    • 15.1.1 FIFO State

      399
    • 15.1.2 FIFO Data

      399
    • 15.1.3 Loopback

      399
      • 15.1.3.1 Internal Loopback

        400
  • 15.2 Testability

    400
    • 15.2.1 EXTEST Instruction

      401
    • 15.2.2 SAMPLE/PRELOAD Instruction

      401
    • 15.2.3 IDCODE Instruction

      401
    • 15.2.4 BYPASS Instruction

      401
• Appendix (Changes From 82544EI/82544GC) A

  403
• Appendix (82540EP/EM and 82545GM/EM Differences) B

  405