Intel IXP43X User Manuals

Table of Contents

• Contents

  3
  • Figures

    4
  • Tables

    5
• Revision History

  7
• Intel® IXP43X Product Line of Network Processors

  1
• 1.0 Introduction

  9
  • 1.1 Content Overview

    9
  • 1.2 Related Documentation

    10
  • 1.3 Acronyms

    10
    • Table 1. List of Acronyms and Abbreviations (Sheet 1 of 2)

      10
  • 1.4 Overview

    11
    • Figure 1. Intel® IXP435 Network Processor Block Diagram

      13
  • 1.5 Typical Applications

    14
• 2.0 System Architecture

  15
  • 2.1 System Architecture Description

    15
  • 2.2 System Memory Map

    15
    • Figure 2. Example: Intel® IXP43X Product Line of Network Processors System Block Diagram

      16
• 3.0 General Hardware Design Considerations

  17
  • Table 2. Signal Type Definitions

    17
  • 3.1 Soft Fusible Features

    17
    • Table 3. Soft Fusible Features (Sheet 1 of 2)

      17
  • 3.2 DDRII/I SDRAM Interface

    18
    • 3.2.1 Signal Interface

      19
      • Table 4. DDRII/I SDRAM Interface Pin Description (Sheet 1 of 2)

        19
    • 3.2.2 DDRII/I SDRAM Initialization

      20
  • 3.3 Expansion Bus

    21
    • 3.3.1 Signal Interface

      21
      • Table 5. Expansion Bus Signal Recommendations (Sheet 1 of 2)

        21
    • 3.3.2 Reset Configuration Straps

      22
      • Table 6. Boot/Reset Strapping Configuration (Sheet 1 of 2)

        22
      • Table 7. Setting Intel XScale® Processor Operation Speed

        24
    • 3.3.3 8-Bit Device Interface

      24
    • 3.3.4 16-Bit Device Interface

      25
      • Figure 3. 8/16-Bit Device Interface

        26
    • 3.3.5 Flash Interface

      26
      • Figure 4. Flash Interface Example

        27
  • 3.4 UART Interface

    27
    • 3.4.1 Signal Interface

      28
      • Table 8. UART Signal Recommendations

        28
      • Figure 5. UART Interface Example

        29
  • 3.5 MII Interface

    29
    • 3.5.1 Signal Interface MII

      30
      • Table 9. MII NPE A Signal Recommendations

        30
      • Table 10. MII NPE C Signal Recommendations (Sheet 1 of 2)

        30
      • Table 11. MAC Management Signal Recommendations - NPE A and NPE C

        31
    • 3.5.2 Device Connection, MII

      31
      • Figure 6. MII Interface Example

        32
  • 3.6 GPIO Interface

    32
    • 3.6.1 Signal Interface

      33
      • Table 12. GPIO Signal Recommendations

        33
    • 3.6.2 Design Notes

      33
  • 3.7 USB Interface

    33
    • 3.7.1 Signal Interface

      34
      • Table 13. USB Host Signal Recommendations

        34
      • Figure 7. Common Mode Choke

        35
      • Figure 8. USB RCOMP and ICOMP Pin Requirement

        36
      • Figure 9. USB Host Down Stream Interface Example

        36
  • 3.8 UTOPIA Level 2 Interface

    37
    • 3.8.1 Signal Interface

      37
      • Table 14. UTOPIA Level 2/MII_A

        37
    • 3.8.2 Device Connection

      41
      • Figure 10. UTOPIA Interface Example

        41
  • 3.9 HSS Interface

    41
    • 3.9.1 Signal Interface

      42
      • Table 15. High-Speed, Serial Interface 0

        42
    • 3.9.2 Device Connection

      42
      • Figure 11. HSS Interface Example

        43
  • 3.10 SSP Interface

    43
    • 3.10.1 Signal Interface

      44
      • Table 16. Synchronous Serial Peripheral Port Interface

        44
    • 3.10.2 Device Connection

      44
      • Figure 12. Serial Flash and SSP Port (SPI) Interface Example

        45
  • 3.11 PCI Interface

    45
    • 3.11.1 Signal Interface

      46
      • Table 17. PCI Controller (Sheet 1 of 2)

        46
    • 3.11.2 PCI Interface Block Diagram

      47
      • Figure 13. PCI Interface

        48
    • 3.11.3 PCI Option Interface

      48
      • Table 18. PCI Host/Option Interface Pin Description (Sheet 1 of 3)

        48
    • 3.11.4 Design Notes

      50
  • 3.12 JTAG Interface

    50
    • 3.12.1 Signal Interface

      51
      • Table 19. Synchronous Serial Peripheral Port Interface

        51
  • 3.13 Input System Clock

    51
    • 3.13.1 Clock Signals

      51
      • Table 20. Clock Signals

        51
    • 3.13.2 Clock Oscillator

      51
      • Figure 14. Clock Oscillator Interface Example

        52
    • 3.13.3 Recommendations for Crystal Selection

      52
      • Figure 15. Recommended circuit design on PCB for crystal oscillator

        53
  • 3.14 Power

    53
    • Table 21. Power Supply

      53
    • 3.14.1 Decoupling Capacitance Recommendations

      54
    • 3.14.2 VCC Decoupling

      54
    • 3.14.3 VCC33 Decoupling

      54
    • 3.14.4 VCCDDR Decoupling

      54
    • 3.14.5 Power Sequence

      54
    • 3.14.6 Reset Timing

      54
• 4.0 General PCB Guide

  56
  • 4.1 PCB Overview

    56
  • 4.2 General Recommendations

    56
  • 4.3 Component Selection

    56
  • 4.4 Component Placement

    56
    • Figure 16. Component Placement on a PCB

      57
  • 4.5 Stack-Up Selection

    57
    • Figure 17. 8-Layer Stackup

      59
    • Figure 18. 6-Layer Stackup

      59
• 5.0 General Layout and Routing Guide

  60
  • 5.1 Overview

    60
  • 5.2 General Layout Guidelines

    60
    • Figure 19. Signal Changing Reference Planes

      61
    • 5.2.1 General Component Spacing

      61
      • Figure 20. Good Design Practice for VIA Hole Placement

        62
      • Figure 21. Poor Design Practice for VIA Placement

        62
      • Figure 22. Pad-to-Pad Clearance of Passive Components to a PGA or BGA

        63
    • 5.2.2 Clock Signal Considerations

      63
    • 5.2.3 MII Signal Considerations

      64
    • 5.2.4 USB V2.0 Considerations

      64
    • 5.2.5 Crosstalk

      64
    • 5.2.6 EMI Design Considerations

      65
    • 5.2.7 Trace Impedance

      65
    • 5.2.8 Power and Ground Plane

      65
• 6.0 PCI Interface Design Considerations

  67
  • 6.1 Electrical Interface

    67
  • 6.2 Topology

    67
    • Figure 23. PCI Address/Data Topology

      68
    • Table 22. PCI Address/Data Routing Guidelines

      68
  • 6.3 Clock Distribution

    68
    • Figure 24. PCI Clock Topology

      69
    • Table 23. PCI Clock Routing Guidelines

      69
    • 6.3.1 Trace Length Limits

      69
    • 6.3.2 Routing Guidelines

      70
    • 6.3.3 Signal Loading

      70
• 7.0 DDRII / DDRI SDRAM

  71
  • 7.1 Introduction

    71
    • Table 24. DDRII/I Signal Groups

      72
    • Figure 25. Processor-DDRII/I SDRAM Interface

      73
    • Table 25. Supported DDRI 32-bit SDRAM Configurations

      74
    • Table 26. Supported DDRII 32-bit SDRAM Configurations

      74
    • Table 27. Supported DDRI 16-bit SDRAM Configurations

      74
    • Table 28. Supported DDRII 16-bit SDRAM Configurations

      75
  • 7.2 DDRII/DDRI RCOMP and Slew Resistances Pin Requirements

    75
    • Figure 26. DDRII/DDRI RCOMP Pin External Resistor Requirements

      75
  • 7.3 DDRII OCD Pin Requirements

    76
    • Figure 27. DDRII OCD Pin Requirements

      76
    • 7.3.1 Signal-Timing Analysis

      76
      • Figure 28. DDR Clock Timing Waveform

        76
      • Table 29. DDR Clock Timings

        76
      • Figure 29. DDR SDRAM Write Timings

        77
      • Figure 30. DDR SDRAM Read Timings

        77
      • Figure 31. DDR - Write Preamble/Postamble Duration

        78
      • Table 30. DDRII-400 MHz Interface -- Signal Timings

        78
      • Table 31. DDR II/I SDRAM Interface -- Signal Timings

        79
    • 7.3.2 Timing Relationships

      79
      • Table 32. Timing Relationships

        80
      • Table 33. Signal Package Lengths (Sheet 1 of 3)

        80
    • 7.3.3 Routing Guidelines

      82
      • 7.3.3.1 Clock Group

        82
        • Figure 32. DDRII Clock Simulation Results: CK Signals

          83
        • Table 34. Clock Signal Group Routing Guidelines

          83
      • 7.3.3.2 Data and Control Groups

        83
        • Figure 33. DDRII Data and Control Simulation Results: DQ and DQS signals

          84
        • Table 35. DDRII Data and Control Signal Group Routing Guidelines

          84
      • 7.3.3.3 Command Groups

        85
        • Figure 34. DDRII Command Simulation Results: ADDRESS signals

          85
        • Table 36. DDRII Command Signal Group Routing Guidelines

          85