Data SheetTable of ContentsProcessor Extension Pak and Header Specification1Processor Extension Pak and Header Defined1Why Do I Need A Header To Debug?2Debug Details3Programming Details4General Header Setup4Device vs. Optional Header Features6MPLAB IDE and MPLAB X IDE Use with Headers7Calibration Bits7Performance Issues7Related Debug Tools7Customer Support8Required Debug Headers9Introduction9AC162050, AC16205811AC162052, AC162055, AC162056, AC16205713AC162053, AC16205415AC162059, AC162070, AC16209617AC16206019AC16206121AC16206623AC16208325AC244023, AC24402428AC24402830AC24404532AC244051, AC24405234Optional Debug Headers37Introduction37AC162062, AC162079, AC162087, AC16209141AC16206443AC162065, AC24402245AC162067, AC16207448AC16207851AC162088, AC16209454AC244026, AC24402757AC244033, AC24403460AC244035, AC24403662AC244043, AC24404464AC244046, AC24404766AC244053, AC24405468Debug Header Target Footprints71Introduction71DIP Device Footprints71TQFP/PLCC Device Footprints71Debug Header Connections75Introduction756-Pin Modular Connector758-Pin SIL Connector766-Pin SIL Connector77SIL Optional Connection78Modular-to-SIL Adapter78Ordering Information79Appendix C: Revision History81Index83Worldwide Sales and Service88Size: 1.22 MBPages: 88Language: EnglishOpen manual
Data SheetTable of ContentsDevices Included In This Data Sheet:3High-Performance RISC CPU:3Special Microcontroller Features:3Extreme Low-Power Management PIC16LF72X with nanoWatt XLP:3Analog Features:3Peripheral Highlights:3Pin Diagrams – 28-Pin PDIP/SOIC/SSOP/QFN/UQFN (PIC16F722/723/726/PIC16LF722/723/726)5TABLE 1: 28-Pin PDIP/SOIC/SSOP/QFN/UQFN Summary (PIC16F722/723/726/PIC16LF722/723/726)6Pin Diagrams – 40-Pin PDIP (PIC16F724/727/PIC16LF724/727)7Pin Diagrams – 44-Pin TQFP (PIC16F724/727/PIC16LF724/727)8Pin Diagrams – 44-Pin QFN (PIC16F724/727/PIC16LF724/727)9TABLE 2: 40/44-Pin PDIP/tqfp/qfn Summary (PIC16F724/727/PIC16LF724/727)10Most Current Data Sheet12Errata12Customer Notification System121.0 Device Overview13FIGURE 1-1: PIC16F722/723/726/PIC16LF722/723/726 Block Diagram14FIGURE 1-2: PIC16F724/727/PIC16LF724/727 Block Diagram15TABLE 1-1: PIC16F72X/PIC16LF72X Pinout Description162.0 Memory Organization192.1 Program Memory Organization19FIGURE 2-1: Program Memory Map And Stack For The PIC16F722/LF72219FIGURE 2-2: Program Memory Map And Stack For The PIC16F723/LF723 and PIC16F724/LF72419FIGURE 2-3: Program Memory Map And Stack For The PIC16F726/LF726 and PIC16F727/LF727202.2 Data Memory Organization202.2.1 General Purpose Register File202.2.2 Special FUNCTION Registers20FIGURE 2-4: PIC16F722/LF722 Special Function Registers21FIGURE 2-5: PIC16F723/LF723 and PIC16F724/LF724 Special Function Registers22FIGURE 2-6: PIC16F726/LF726 and PIC16F727/LF727 Special Function Registers23TABLE 2-1: PIC16F72X/PIC16LF72X Special Function Register Summary24Register 2-1: STATUS: STATUS Register27Register 2-2: OPTION_REG: OPTION Register28Register 2-3: PCON: Power Control Register292.3 PCL and PCLATH30FIGURE 2-7: Loading Of PC In Different Situations302.3.1 computed goto302.3.2 Stack302.4 Program Memory Paging30EXAMPLE 2-1: Call of a Subroutine in Page 1 from Page 0302.5 Indirect Addressing, INDF and FSR Registers31EXAMPLE 2-2: Indirect Addressing31FIGURE 2-8: Direct/Indirect Addressing313.0 Resets33FIGURE 3-1: Simplified Block Diagram Of On-Chip Reset Circuit333.1 MCLR35FIGURE 3-2: Recommended MCLR Circuit353.2 Power-on Reset (POR)353.3 Power-up Timer (PWRT)353.4 Watchdog Timer (WDT)353.4.1 WDT Oscillator353.4.2 WDT Control36TABLE 3-1: WDT Status363.5 Brown-Out Reset (BOR)37FIGURE 3-3: Brown-Out Situations373.6 Time-out Sequence383.7 Power Control (PCON) Register38TABLE 3-2: Time-Out In Various Situations38TABLE 3-3: Reset Bits And Their Significance38FIGURE 3-4: Time-Out Sequence On Power-Up (Delayed MCLR): Case 139FIGURE 3-5: Time-Out Sequence On Power-Up (Delayed MCLR): Case 239FIGURE 3-6: Time-Out Sequence On Power-Up (MCLR With Vdd): Case 339TABLE 3-4: Initialization Condition for Registers40TABLE 3-5: Initialization Condition For Special Registers42TABLE 3-6: Summary Of Registers Associated With Resets424.0 Interrupts43FIGURE 4-1: Interrupt Logic434.1 Operation444.2 Interrupt Latency44FIGURE 4-2: INT Pin Interrupt Timing444.3 Interrupts During Sleep454.4 INT Pin454.5 Context Saving45EXAMPLE 4-1: Saving W, STATUS and PCLATH Registers in RAM454.5.1 INTCON Register46Register 4-1: INTCON: Interrupt Control Register464.5.2 PIE1 Register47Register 4-2: PIE1: Peripheral Interrupt Enable Register 1474.5.3 PIE2 Register48Register 4-3: PIE2: Peripheral Interrupt Enable Register 2484.5.4 PIR1 Register49Register 4-4: PIR1: Peripheral Interrupt Request Register 1494.5.5 PIR2 Register50Register 4-5: PIR2: Peripheral Interrupt Request Register 250TABLE 4-1: Summary of Registers Associated with Interrupts505.0 Low Dropout (LDO) Voltage Regulator516.0 I/O Ports536.1 Alternate Pin Function53Register 6-1: APFCON: Alternate Pin Function COntrol Register536.2 PORTA and the TRISA Registers54EXAMPLE 6-1: Initializing PORTA54Register 6-2: PORTA: PORTA Register54Register 6-3: TRISA: PORTA Tri-State Register546.2.1 ANSELA Register55Register 6-4: ANSELA: PORTA Analog Select Register556.2.2 Pin Descriptions and Diagrams56FIGURE 6-1: Block Diagram of RA057FIGURE 6-2: RA<3:1> Block Diagram58FIGURE 6-3: Block Diagram of RA458FIGURE 6-4: Block Diagram of RA559FIGURE 6-5: Block Diagram of RA660FIGURE 6-6: Block Diagram of RA760TABLE 6-1: Summary of Registers Associated with PORTA616.3 PORTB and TRISB Registers62EXAMPLE 6-2: Initializing PORTB626.3.1 ANSELB Register626.3.2 Weak Pull-Ups626.3.3 Interrupt-on-Change62Register 6-5: PORTB: PORTB Register63Register 6-6: TRISB: PORTB Tri-State Register63Register 6-7: WPUB: WEAK PULL-uP PORTB REGISTER64Register 6-8: IOCB: Interrupt-on-change PORTB Register64Register 6-9: ANSELB: PORTB Analog Select Register646.3.4 Pin Descriptions and Diagrams65FIGURE 6-7: Block Diagram of RB066FIGURE 6-8: Block Diagram of RB4, RB<2:1>67FIGURE 6-9: Block Diagram of RB368FIGURE 6-10: Block Diagram of rb569FIGURE 6-11: Block Diagram of RB670FIGURE 6-12: Block Diagram of RB771TABLE 6-2: Summary of Registers Associated with PORTB726.4 PORTC and TRISC Registers73EXAMPLE 6-3: Initializing PORTC73Register 6-10: PORTC: PORTC Register73Register 6-11: TRISC: PORTC Tri-State Register736.4.1 RC0/T1OSO/T1CKI746.4.2 RC1/T1OSi/CCP2746.4.3 RC2/CCP1746.4.4 RC3/SCK/SCL746.4.5 RC4/SDI/SDA746.4.6 RC5/SDO746.4.7 RC6/TX/CK746.4.8 RC7/RX/DT74FIGURE 6-13: Block Diagram of RC075FIGURE 6-14: Block Diagram of RC175FIGURE 6-15: Block Diagram of RC276FIGURE 6-16: Block Diagram of RC376FIGURE 6-17: Block Diagram of RC477FIGURE 6-18: Block Diagram of RC577FIGURE 6-19: Block Diagram of RC678FIGURE 6-20: Block Diagram of RC778TABLE 6-3: Summary of Registers Associated with PORTC796.5 PORTD and TRISD Registers80EXAMPLE 6-4: Initializing PORTD806.5.1 ANSELD Register80Register 6-12: PORTD: PORTD Register(1)80Register 6-13: TRISD: PORTD Tri-State Register(1)81Register 6-14: ANSELD: PORTD Analog Select Register(2)816.5.2 RD0/CPS8826.5.3 RD1/CPS9826.5.4 RD2/CPS10826.5.5 RD3/CPS11826.5.6 RD4/CPS12826.5.7 RD5/CPS13826.5.8 RD6/CPS14826.5.9 RD7/CPS1582FIGURE 6-21: Block Diagram of RD<7:0>82TABLE 6-4: Summary of Registers Associated with PORTD(1)836.6 PORTE and TRISE Registers84EXAMPLE 6-5: Initializing PORTE84Register 6-15: PORTE: PORTE Register85Register 6-16: TRISE: PORTE Tri-State Register85Register 6-17: ANSELE: PORTE Analog Select Register86TABLE 6-5: Summary of Registers Associated with PORTE866.6.1 RE0/AN5(1)876.6.2 RE1/AN6(1)876.6.3 RE2/AN7(1)876.6.4 RE3/MCLR/Vpp87FIGURE 6-22: Block Diagram of RE<2:0>88FIGURE 6-23: Block Diagram of RE3887.0 Oscillator Module897.1 Overview89FIGURE 7-1: Simplified PIC® MCU Clock Source Block Diagram897.2 Clock Source Modes907.3 Internal Clock Modes907.3.1 INTOSC and INTOSCIO Modes907.3.2 Frequency Select Bits (IRCF)907.4 Oscillator Control91Register 7-1: OSCCON: Oscillator Control Register917.5 Oscillator Tuning92Register 7-2: OSCTUNE: Oscillator Tuning ReGister927.6 External Clock Modes937.6.1 Oscillator Start-up Timer (OST)937.6.2 EC Mode93FIGURE 7-2: External Clock (EC) Mode Operation937.6.3 LP, XT, HS Modes93FIGURE 7-3: Quartz Crystal Operation (LP, XT or HS Mode)93FIGURE 7-4: Ceramic Resonator Operation (XT or HS Mode)947.6.4 External RC Modes94FIGURE 7-5: External RC Modes94TABLE 7-1: Summary of Registers Associated with Clock Sources948.0 Device Configuration958.1 Configuration Words95Register 8-1: CONFIG1: Configuration Word Register 195Register 8-2: CONFIG2: Configuration Word Register 2968.2 Code Protection978.3 User ID979.0 Analog-to-Digital Converter (ADC) Module99FIGURE 9-1: ADC Block Diagram999.1 ADC Configuration1009.1.1 Port Configuration1009.1.2 Channel Selection1009.1.3 ADC Voltage Reference1009.1.4 Conversion Clock100TABLE 9-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies101FIGURE 9-2: Analog-to-Digital Conversion Tad Cycles1019.1.5 Interrupts1029.2 ADC Operation1029.2.1 Starting a Conversion1029.2.2 Completion of a Conversion1029.2.3 Terminating a conversion1029.2.4 ADC Operation During Sleep1029.2.5 Special Event Trigger1029.2.6 A/D Conversion Procedure103EXAMPLE 9-1: A/D Conversion1039.2.7 ADC Register Definitions104Register 9-1: ADCON0: A/D Control Register 0104Register 9-2: ADCON1: A/D Control Register 1105Register 9-3: ADRES: ADC Result Register1059.3 A/D Acquisition Requirements106EQUATION 9-1: Acquisition Time Example106FIGURE 9-3: Analog Input Model107FIGURE 9-4: ADC Transfer Function107TABLE 9-2: Summary of Associated ADC Registers10810.0 Fixed Voltage Reference109Register 10-1: FVRCON: Fixed Voltage Reference Register10911.0 Timer0 Module11111.1 Timer0 Operation11111.1.1 8-bit Timer mode11111.1.2 8-Bit Counter Mode111FIGURE 11-1: Block Diagram of the Timer0/WDT Prescaler11111.1.3 Software Programmable Prescaler11211.1.4 Timer0 Interrupt11211.1.5 8-BIT COUNTER MODE SYNCHRONIZATION112Register 11-1: OPTION_REG: OPTION Register113TABLE 11-1: Summary of Registers Associated with Timer011312.0 Timer1 Module with Gate Control115FIGURE 12-1: Timer1 Block Diagram11512.1 Timer1 Operation116TABLE 12-1: Timer1 Enable Selections11612.2 Clock Source Selection11612.2.1 Internal Clock Source11612.2.2 External Clock Source116TABLE 12-2: Clock Source Selections11612.3 Timer1 Prescaler11712.4 Timer1 Oscillator11712.5 Timer1 Operation in Asynchronous Counter Mode11712.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode11712.6 Timer1 Gate11812.6.1 Timer1 Gate Count Enable118TABLE 12-3: Timer1 Gate Enable Selections11812.6.2 Timer1 Gate Source Selection118TABLE 12-4: Timer1 Gate Sources118TABLE 12-5: WDT/Timer1 Gate Interaction11912.6.3 Timer1 Gate Toggle Mode11912.6.4 Timer1 Gate Single-Pulse Mode11912.6.5 Timer1 Gate Value Status11912.6.6 Timer1 Gate Event Interrupt11912.7 Timer1 Interrupt12012.8 Timer1 Operation During Sleep12012.9 CCP Capture/Compare Time Base12012.10 CCP Special Event Trigger120FIGURE 12-2: Timer1 Incrementing Edge120FIGURE 12-3: Timer1 Gate Count Enable Mode121FIGURE 12-4: Timer1 Gate Toggle Mode121FIGURE 12-5: Timer1 Gate Single-Pulse Mode122FIGURE 12-6: Timer1 Gate Single-Pulse and Toggle Combined Mode12312.11 Timer1 Control Register124Register 12-1: T1CON: Timer1 Control Register12412.12 Timer1 Gate Control Register125Register 12-2: T1GCON: Timer1 Gate Control Register125TABLE 12-6: Summary of Registers Associated with Timer112613.0 Timer2 Module12713.1 Timer2 Operation127FIGURE 13-1: Timer2 Block Diagram127Register 13-1: T2CON: Timer2 Control Register128TABLE 13-1: Summary of Registers Associated With Timer212814.0 Capacitive Sensing Module129FIGURE 14-1: Capacitive Sensing Block Diagram12914.1 Analog MUX13014.2 Capacitive Sensing Oscillator13014.3 Timer resources13014.4 Fixed Time Base13014.4.1 Timer013014.4.2 Timer1130TABLE 14-1: TIMER1 ENABLE FUNCTION13014.5 Software Control13114.5.1 Nominal Frequency (No Capacitive Load)13114.5.2 Reduced Frequency (additional capacitive load)13114.5.3 Frequency threshold13114.6 Operation during Sleep132Register 14-1: CPSCON0: Capacitive Sensing Control Register 0133Register 14-2: CPSCON1: Capacitive Sensing Control Register 1134TABLE 14-2: Summary of Registers Associated with Capacitive Sensing13415.0 Capture/Compare/PWM (CCP) Module135TABLE 15-1: CCP Mode – Timer Resources Required135TABLE 15-2: Interaction of Two CCP Modules135Register 15-1: CCPxCON: CCPx Control Register13615.1 Capture Mode13715.1.1 CCPx pin Configuration137FIGURE 15-1: Capture Mode Operation Block Diagram13715.1.2 Timer1 Mode Selection13715.1.3 Software Interrupt13715.1.4 CCP Prescaler137EXAMPLE 15-1: Changing Between Capture Prescalers13715.1.5 Capture During Sleep137TABLE 15-3: Summary of Registers Associated with Capture13815.2 Compare Mode139FIGURE 15-2: Compare Mode Operation Block Diagram13915.2.1 CCPx Pin Configuration13915.2.2 timer1 Mode Selection13915.2.3 Software Interrupt Mode13915.2.4 Special Event Trigger13915.2.5 Compare During Sleep139TABLE 15-4: Summary of Registers Associated with Compare14015.3 PWM Mode141FIGURE 15-3: Simplified PWM Block Diagram141FIGURE 15-4: CCP PWM Output14115.3.1 CCPx Pin Configuration14115.3.2 PWM period142EQUATION 15-1: PWM Period14215.3.3 PWM Duty Cycle142EQUATION 15-2: Pulse Width142EQUATION 15-3: Duty Cycle Ratio14215.3.4 PWM Resolution143EQUATION 15-4: PWM Resolution143TABLE 15-5: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)143TABLE 15-6: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)14315.3.5 Operation in Sleep Mode14315.3.6 Changes in System Clock Frequency14315.3.7 Effects of Reset14315.3.8 Setup for PWM Operation143TABLE 15-7: Summary of Registers Associated with PWM14416.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)145FIGURE 16-1: AUSART Transmit Block Diagram145FIGURE 16-2: AUSART Receive Block Diagram14616.1 AUSART Asynchronous Mode14716.1.1 AUSART Asynchronous Transmitter147FIGURE 16-3: Asynchronous Transmission148FIGURE 16-4: Asynchronous Transmission (Back-to-Back)148TABLE 16-1: Registers Associated with Asynchronous Transmission14916.1.2 AUSART Asynchronous Receiver150FIGURE 16-5: Asynchronous Reception152TABLE 16-2: Registers Associated with Asynchronous Reception153Register 16-1: TXSTA: Transmit STATUS AND CONTROL REGISTER154Register 16-2: RCSTA: Receive STATUS AND CONTROL REGISTER15516.2 AUSART Baud Rate Generator (BRG)156EXAMPLE 16-1: Calculating Baud Rate Error156TABLE 16-3: Baud Rate Formulas156TABLE 16-4: Registers Associated with the bAUD rATE gENERATOR156TABLE 16-5: BAUD Rates for Asynchronous Modes15716.3 AUSART Synchronous Mode15916.3.1 Synchronous Master Mode159FIGURE 16-6: Synchronous Transmission160FIGURE 16-7: Synchronous Transmission (Through TXEN)160TABLE 16-6: Registers Associated with Synchronous Master Transmission160FIGURE 16-8: Synchronous Reception (Master Mode, SREN)162TABLE 16-7: Registers Associated with Synchronous Master Reception16216.3.2 Synchronous slave Mode163TABLE 16-8: Registers Associated with Synchronous Slave Transmission163TABLE 16-9: Registers Associated with Synchronous Slave Reception16416.4 AUSART Operation During Sleep16516.4.1 Synchronous Receive During Sleep16516.4.2 Synchronous Transmit During Sleep16517.0 SSP Module Overview16717.1 SPI Mode167FIGURE 17-1: Typical SPI Master/Slave Connection167FIGURE 17-2: SPI Mode Block Diagram16817.1.1 Master Mode169FIGURE 17-3: SPI Master Mode Waveform170EXAMPLE 17-1: Loading the SSPBUF (SSPSR) Register17017.1.2 Slave Mode171FIGURE 17-4: SPI Mode Waveform (Slave Mode with CKE = 0)172FIGURE 17-5: SPI Mode Waveform (Slave Mode with CKE = 1)172FIGURE 17-6: Slave Select Synchronization Waveform173Register 17-1: SSPCON: Sync Serial Port Control Register (SPI Mode)174Register 17-2: SSPSTAT: Sync Serial Port Status Register (SPI Mode)175TABLE 17-1: Summary of Registers Associated with SPI Operation17617.2 I2C Mode177FIGURE 17-7: I2C™ Mode Block Diagram177FIGURE 17-8: Typical I2C™ Connections17717.2.1 Hardware Setup17717.2.2 Start and Stop Conditions178FIGURE 17-9: Start and Stop Conditions17817.2.3 Acknowledge178TABLE 17-2: Data Transfer Received Byte Actions17817.2.4 Addressing17917.2.5 Reception180FIGURE 17-10: I2C™ Waveforms for Reception (7-bit Address)180FIGURE 17-11: I2C™ Slave Mode Timing (Reception, 10-bit Address)18117.2.6 Transmission182FIGURE 17-12: I2C Waveforms for Transmission (7-bit Address)182FIGURE 17-13: I2C Slave Mode Timing (Transmission 10-bit Address)18317.2.7 Clock Stretching18417.2.8 Firmware Master Mode18417.2.9 Multi-Master Mode18417.2.10 Clock Synchronization18517.2.11 Sleep Operation185FIGURE 17-14: Clock Synchronization Timing185Register 17-3: SSPCON: Synchronous Serial Port Control Register (I2C Mode)186Register 17-4: SSPSTAT: Synchronous Serial Port Status Register (I2C Mode)187Register 17-5: SSPMSK: SSP Mask Register188Register 17-6: SSPADD: SSP I2C Address Register18818.0 Program Memory Read189EXAMPLE 18-1: PROGRAM Memory Read189Register 18-1: PMCON1: Program Memory Control 1 register190Register 18-2: PMDATH: Program Memory Data High register190Register 18-3: PMDATL: Program Memory Data Low register190Register 18-4: PMADRH: Program Memory Address High register191Register 18-5: PMADRL: Program Memory Address Low register191TABLE 18-1: Summary of Registers Associated with Program Memory Read19119.0 Power-Down Mode (Sleep)19319.1 Wake-up from Sleep19319.2 Wake-up Using Interrupts194FIGURE 19-1: Wake-Up From Sleep Through Interrupt194TABLE 19-1: Summary of Registers Associated with pOWER-dOWN mODE19420.0 In-Circuit Serial Programming™ (ICSP™)195FIGURE 20-1: Typical connection for ICSP™ programming19521.0 Instruction Set Summary19721.1 Read-Modify-Write Operations197TABLE 21-1: Opcode Field Descriptions197FIGURE 21-1: General Format for Instructions197TABLE 21-2: PIC16F72X/PIC16LF72X Instruction Set19821.2 Instruction Descriptions1991.0 Development Support20723.0 Electrical Specifications211Absolute Maximum Ratings(†)21123.1 DC Characteristics: PIC16F72X/PIC16LF72X-I/E (Industrial, Extended)212FIGURE 23-1: POR and POR Rearm with Slow Rising Vdd21323.2 DC Characteristics: PIC16F72X/PIC16LF72X-I/E (Industrial, Extended)21423.3 DC Characteristics: PIC16F72X/PIC16LF72X-I/E (Power-Down)21623.4 DC Characteristics: PIC16F72X/PIC16LF72X-I/E21823.5 Thermal Considerations22023.6 Timing Parameter Symbology221FIGURE 23-2: Load Conditions22123.7 AC Characteristics: PIC16F72X-I/E222FIGURE 23-3: Clock Timing222FIGURE 23-4: PIC16F72X Voltage Frequency Graph, -40°C £ Ta £ +125°C222FIGURE 23-5: PIC16LF72X Voltage Frequency Graph, -40°C £ Ta £ +125°C223FIGURE 23-6: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature223TABLE 23-1: Clock Oscillator Timing Requirements224TABLE 23-2: Oscillator Parameters225FIGURE 23-7: CLKOUT and I/O Timing225TABLE 23-3: CLKOUT and I/O Timing Parameters226FIGURE 23-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing226FIGURE 23-9: Brown-Out Reset Timing and Characteristics227TABLE 23-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-Out Reset Parameters228FIGURE 23-10: Timer0 and Timer1 External Clock Timings229TABLE 23-5: Timer0 and Timer1 External Clock Requirements229FIGURE 23-11: Capture/Compare/PWM Timings (CCP)230TABLE 23-6: Capture/Compare/PWM Requirements (CCP)230TABLE 23-7: PIC16F72X A/D Converter (ADC) Characteristics:230TABLE 23-8: PIC16F72X A/D Conversion Requirements231FIGURE 23-12: PIC16F72X A/D Conversion Timing (Normal Mode)231FIGURE 23-13: PIC16F72X A/D Conversion Timing (Sleep Mode)232FIGURE 23-14: USART Synchronous Transmission (Master/Slave) Timing232TABLE 23-9: USART Synchronous Transmission Requirements232FIGURE 23-15: USART Synchronous Receive (Master/Slave) Timing233TABLE 23-10: USART Synchronous Receive Requirements233FIGURE 23-16: SPI Master Mode Timing (CKE = 0, SMP = 0)234FIGURE 23-17: SPI Master Mode Timing (CKE = 1, SMP = 1)234FIGURE 23-18: SPI Slave Mode Timing (CKE = 0)235FIGURE 23-19: SPI Slave Mode Timing (CKE = 1)235TABLE 23-11: SPI Mode requirements236FIGURE 23-20: I2C™ Bus Start/Stop Bits Timing236TABLE 23-12: I2C™ Bus Start/Stop Bits Requirements237FIGURE 23-21: I2C™ Bus Data Timing237TABLE 23-13: I2C™ Bus Data Requirements238TABLE 23-14: Cap Sense Oscillator Specifications239FIGURE 23-22: Cap Sense Oscillator23924.0 DC and AC Characteristics Graphs and Charts241FIGURE 24-1: PIC16F72X Maximum Idd vs. Fosc over Vdd, EC Mode, Vcap = 0.1µF241FIGURE 24-2: PIC16LF72X Maximum Idd vs. Fosc over Vdd, EC Mode241FIGURE 24-3: PIC16F72X Typical Idd vs. Fosc Over Vdd, EC Mode, Vcap = 0.1µF242FIGURE 24-4: PIC16LF72X Typical Idd vs. Fosc over Vdd, EC Mode242FIGURE 24-5: PIC16F72X Maximum Idd vs. Vdd over Fosc, EXTRC Mode, Vcap = 0.1µF243FIGURE 24-6: PIC16LF72X Maximum Idd vs. Vdd over Fosc, EXTRC Mode243FIGURE 24-7: PIC16F72X Typical Idd vs. Vdd over Fosc, EXTRC Mode, Vcap = 0.1µF244FIGURE 24-8: PIC16LF72X Typical Idd vs. Vdd over Fosc, EXTRC Mode244FIGURE 24-9: PIC16F72X maximum Idd vs. Fosc over Vdd, HS Mode, Vcap = 0.1µF245FIGURE 24-10: PIC16LF72X Maximum Idd vs. Fosc over Vdd, HS Mode245FIGURE 24-11: PIC16F72X Typical Idd vs. Fosc over Vdd, HS Mode, Vcap = 0.1µF246FIGURE 24-12: PIC16LF72X Typical Idd vs. Fosc over Vdd, HS Mode246FIGURE 24-13: PIC16F72X Maximum Idd vs. Vdd Over Fosc, XT Mode, Vcap = 0.1µF247FIGURE 24-14: PIC16LF72X Maximum Idd vs. Vdd Over Fosc, XT Mode247FIGURE 24-15: PIC16F72X Typical Idd vs. Vdd Over Fosc, XT Mode, Vcap = 0.1µF248FIGURE 24-16: PIC16LF72X Typical Idd vs. Vdd over Fosc, XT Mode248FIGURE 24-17: PIC16F72X Idd vs. Vdd, LP Mode, Vcap = 0.1µF249FIGURE 24-18: PIC16LF72X Idd vs. Vdd, LP Mode249FIGURE 24-19: PIC16F72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF250FIGURE 24-20: PIC16LF72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode250FIGURE 24-21: PIC16F72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF251FIGURE 24-22: PIC16LF72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode251FIGURE 24-23: PIC16F72X Typical Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF252FIGURE 24-24: PIC16LF72X Typical Idd vs. Fosc over Vdd, INTOSC Mode252FIGURE 24-25: PIC16F72X Typical Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF253FIGURE 24-26: PIC16LF72X Typical Idd vs. Fosc over Vdd, INTOSC Mode253FIGURE 24-27: PIC16F72X Maximum Base Ipd vs. Vdd, Vcap = 0.1µF254FIGURE 24-28: PIC16LF72X Maximum Base Ipd vs. Vdd254FIGURE 24-29: PIC16F72X typical Base Ipd vs. Vdd, Vcap = 0.1µF255FIGURE 24-30: PIC16LF72X Typical Base Ipd vs. Vdd255FIGURE 24-31: PIC16F72X fixed Voltage Reference Ipd vs. Vdd, Vcap = 0.1µF256FIGURE 24-32: PIC16LF72X Fixed Voltage Reference Ipd vs. Vdd256FIGURE 24-33: PIC16F72X BOR Ipd vs. Vdd, Vcap = 0.1µF257FIGURE 24-34: PIC16LF72X BOR Ipd vs. Vdd257FIGURE 24-35: PIC16F72X Cap Sense High Power Ipd vs. Vdd, Vcap = 0.1µF258FIGURE 24-36: PIC16LF72X Cap Sense High Power Ipd vs. Vdd258FIGURE 24-37: PIC16F72X Cap Sense Medium Power Ipd vs. Vdd, Vcap = 0.1µF259FIGURE 24-38: PIC16LF72X cap Sense Medium Power Ipd vs. Vdd259FIGURE 24-39: PIC16F72X Cap Sense low Power Ipd vs. Vdd, Vcap = 0.1µF260FIGURE 24-40: PIC16LF72X Cap Sense Low Power Ipd vs. Vdd260FIGURE 24-41: PIC16F72X T1OSC 32 Khz Ipd vs. Vdd, Vcap = 0.1µF261FIGURE 24-42: PIC16LF72X T1OSC 32 Khz Ipd vs. Vdd261FIGURE 24-43: PIC16F72X TYpical ADC Ipd vs. Vdd, Vcap = 0.1µF262FIGURE 24-44: PIC16LF72X Typical ADC Ipd vs. Vdd262FIGURE 24-45: PIC16F72X ADC Ipd vs. Vdd, Vcap = 0.1µF263FIGURE 24-46: PIC16LF72X ADC Ipd vs. Vdd263FIGURE 24-47: PIC16F72X WDT Ipd vs. Vdd, Vcap = 0.1µF264FIGURE 24-48: PIC16LF72X WDT Ipd vs. Vdd264FIGURE 24-49: TTL Input Threshold Vin vs. Vdd over Temperature265FIGURE 24-50: SCHMITT TRIGGER Input Threshold Vin vs. Vdd Over Temperature265FIGURE 24-51: SCHMITT TRIGGER Input Threshold Vin vs. Vdd Over Temperature266FIGURE 24-52: Voh vs. Ioh Over Temperature, Vdd = 5.5V266FIGURE 24-53: Voh vs. Ioh Over Temperature, Vdd = 3.6V267FIGURE 24-54: Voh vs. Ioh Over Temperature, Vdd = 1.8V267FIGURE 24-55: Vol vs. Iol Over Temperature, Vdd = 5.5V268FIGURE 24-56: Vol vs. Iol Over Temperature, Vdd = 3.6268FIGURE 24-57: Vol vs. Iol over Temperature, Vdd = 1.8V269FIGURE 24-58: PIC16F72X PWRT Period269FIGURE 24-59: PIC16F72X WDT Time-out Period270FIGURE 24-60: PIC16F72X HFINTOSC Wake-up from Sleep Start-up Time270FIGURE 24-61: PIC16F72X A/D Internal RC Oscillator Period271FIGURE 24-62: PIC16F72X Cap Sense Output Current, Power Mode = High271FIGURE 24-63: PIC16F72X Cap Sense Output Current, Power Mode = Medium272FIGURE 24-64: PIC16F72X Cap Sense Output Current, Power Mode = Low272FIGURE 24-65: PIC16F72X Cap sensor Hysteresis, Power Mode = High273FIGURE 24-66: PIC16F72X Cap sensor Hysteresis, power Mode = Medium273FIGURE 24-67: PIC16F72X Cap sensor Hysteresis, power Mode = LOw274FIGURE 24-68: Typical FVR (x1 and x2) vs. Supply Voltage (V) Normalized at 3.0V274FIGURE 24-69: Typical FVR Change vs. Temperature Normalized at 25°C27525.0 Packaging Information27725.1 Package Marking Information277Package Marking Information (Continued)27825.2 Package Details279Appendix A: Data Sheet Revision History291Revision A291Revision B291Revision C291Revision D291Revision E291Appendix B: Migrating From Other PIC® Devices291TABLE B-1: Feature Comparison291INDEX293The Microchip Web Site299Customer Change Notification Service299Customer Support299Reader Response300Product Identification System301Worldwide Sales302Size: 4.44 MBPages: 302Language: EnglishOpen manual
