Data SheetTable of ContentsHigh-Performance RISC CPU:3Peripheral Features:3Advanced Analog Features:3CAN bus Module Features:3Special Microcontroller Features:3Flash Technology:3Pin Diagrams4Table of Contents6Most Current Data Sheet7Errata7Customer Notification System71.0 Device Overview9TABLE 1-1: PIC18FXX8 Device Features9FIGURE 1-1: PIC18F248/258 Block Diagram10FIGURE 1-2: PIC18F448/458 Block Diagram11TABLE 1-2: PIC18FXX8 Pinout I/O Descriptions122.0 Oscillator Configurations192.1 Oscillator Types192.2 Crystal Oscillator/Ceramic Resonators19FIGURE 2-1: Crystal/Ceramic Resonator Operation (HS, XT or LP Osc Configuration)19TABLE 2-1: Ceramic Resonators19TABLE 2-2: Capacitor Selection for Crystal Oscillator202.3 RC Oscillator20FIGURE 2-2: RC Oscillator Mode202.4 External Clock Input21FIGURE 2-3: External Clock Input Operation (EC Osc Configuration)21FIGURE 2-4: External Clock Input Operation (ECIO Configuration)212.5 HS4 (PLL)21FIGURE 2-5: PLL Block Diagram212.6 Oscillator Switching Feature222.6.1 System Clock Switch Bit22FIGURE 2-6: Device Clock Sources22Register 2-1: OSCCON: Oscillator Control Register222.6.2 Oscillator Transitions23FIGURE 2-7: Timing Diagram for Transition From OSC1 to Timer1 Oscillator23FIGURE 2-8: Timing Diagram for Transition Between Timer1 and OSC1 (HS, XT, LP)23FIGURE 2-9: Timing for Transition Between Timer1 and OSC1 (HS with PLL)24FIGURE 2-10: Timing for Transition Between Timer1 and OSC1 (RC, EC)242.7 Effects of Sleep Mode on the OnChip Oscillator252.8 Power-up Delays25TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode253.0 Reset27FIGURE 3-1: Simplified Block Diagram of On-Chip Reset Circuit273.1 Power-on Reset (POR)283.2 MCLR28FIGURE 3-2: External Power-on Reset Circuit (for Slow Vdd Power-up)283.3 Power-up Timer (PWRT)283.4 Oscillator Start-up Timer (OST)283.5 PLL Lock Time-out283.6 Brown-out Reset (BOR)283.7 Time-out Sequence29TABLE 3-1: Time-out in Various Situations29Register 3-1: RCON Register Bits and Positions29TABLE 3-2: Status Bits, Their Significance and the Initialization Condition for RCON Register29FIGURE 3-3: Time-out Sequence on Power-up (MCLR Tied to Vdd)30FIGURE 3-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 130FIGURE 3-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 230FIGURE 3-6: Slow Rise Time (MCLR Tied to Vdd)31FIGURE 3-7: Time-out Sequence on POR w/PLL Enabled (MCLR Tied to Vdd)31TABLE 3-3: Initialization Conditions for All Registers324.0 Memory Organization394.1 Program Memory Organization39FIGURE 4-1: Program Memory Map and Stack for PIC18F248/448394.1.1 Internal Program Memory Operation39FIGURE 4-2: Program Memory Map and Stack for PIC18F258/458394.2 Return Address Stack404.2.1 Top-of-Stack Access404.2.2 Return Stack Pointer (STKPTR)40Register 4-1: STKPTR: Stack Pointer Register41FIGURE 4-3: Return Address Stack and Associated Registers414.2.3 PUSH and POP Instructions424.2.4 Stack Full/Underflow Resets424.3 Fast Register Stack42EXAMPLE 4-1: Fast Register Stack Code Example424.4 PCL, PCLATH and PCLATU424.5 Clocking Scheme/Instruction Cycle43FIGURE 4-4: Clock/Instruction Cycle434.6 Instruction Flow/Pipelining434.7 Instructions in Program Memory43EXAMPLE 4-2: Instruction Pipeline Flow44EXAMPLE 4-3: Instructions in Program Memory444.7.1 Two-Word Instructions454.8 Look-up Tables454.8.1 Computed GOTO454.8.2 Table Reads/Table Writes45EXAMPLE 4-4: Two-Word Instructions454.9 Data Memory Organization464.9.1 General Purpose Register File464.9.2 Special Function Registers46FIGURE 4-5: Data Memory Map for PIC18F248/44847FIGURE 4-6: Data Memory Map for PIC18F258/45848TABLE 4-1: Special Function Register Map49TABLE 4-2: Register File Summary514.10 Access Bank564.11 Bank Select Register (BSR)56FIGURE 4-7: Direct Addressing564.12 Indirect Addressing, INDF and FSR Registers57EXAMPLE 4-5: How to Clear RAM (Bank 1) Using Indirect Addressing574.12.1 Indirect Addressing Operation57FIGURE 4-8: Indirect Addressing584.13 Status Register59Register 4-2: Status Register594.14 RCON Register60Register 4-3: RCON: Reset Control Register605.0 Data EEPROM Memory615.1 EEADR Register615.2 EECON1 and EECON2 Registers61Register 5-1: EECON1: EEPROM Control Register 1625.3 Reading the Data EEPROM Memory63EXAMPLE 5-1: Data EEPROM Read635.4 Writing to the Data EEPROM Memory63EXAMPLE 5-2: Data EEPROM Write635.5 Write Verify645.6 Protection Against Spurious Write645.7 Operation During Code-Protect645.8 Using the Data EEPROM64EXAMPLE 5-3: Data EEPROM Refresh Routine64TABLE 5-1: Registers Associated with Data EEPROM Memory656.0 Flash Program Memory676.1 Table Reads and Table Writes67FIGURE 6-1: Table Read Operation67FIGURE 6-2: Table Write Operation686.2 Control Registers686.2.1 EECON1 and EECON2 Registers68Register 6-1: EECON1: EEPROM Control Register 1696.2.2 TABLAT – Table Latch Register706.2.3 TBLPTR – Table Pointer Register706.2.4 Table Pointer Boundaries70TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions70FIGURE 6-3: Table Pointer Boundaries Based on Operation706.3 Reading the Flash Program Memory71FIGURE 6-4: Reads From Flash Program Memory71EXAMPLE 6-1: Reading a Flash Program Memory Word716.4 Erasing Flash Program Memory726.4.1 Flash Program Memory Erase Sequence72EXAMPLE 6-2: Erasing a Flash Program Memory Row726.5 Writing to Flash Program Memory736.5.1 Flash Program Memory Write Sequence73FIGURE 6-5: Table Writes to Flash Program Memory73EXAMPLE 6-3: Writing to Flash Program Memory74EXAMPLE 6-3: Writing to Flash Program Memory (CONTINUED)756.5.2 Write Verify756.5.3 Unexpected Termination of Write Operation756.5.4 Protection Against Spurious Writes756.6 Flash Program Operation During Code Protection75TABLE 6-2: Registers Associated with Program Flash Memory767.0 8 x 8 Hardware Multiplier777.1 Introduction777.2 Operation77EXAMPLE 7-1: 8 x 8 Unsigned Multiply Routine77EXAMPLE 7-2: 8 x 8 Signed Multiply Routine77TABLE 7-1: Performance Comparison77EQUATION 7-1: 16 x 16 Unsigned Multiplication Algorithm78EXAMPLE 7-3: 16 x 16 Unsigned Multiply Routine78EQUATION 7-2: 16 x 16 Signed Multiplication Algorithm78EXAMPLE 7-4: 16 x 16 Signed Multiply Routine788.0 Interrupts79FIGURE 8-1: Interrupt Logic808.1 INTCON Registers81Register 8-1: INTCON: Interrupt Control Register81Register 8-2: INTCON2: Interrupt Control Register 282Register 8-3: INTCON3: Interrupt Control Register 3838.2 PIR Registers84Register 8-4: PIR1: Peripheral Interrupt Request (Flag) Register 184Register 8-5: PIR2: Peripheral Interrupt Request (Flag) Register 285Register 8-6: PIR3: Peripheral Interrupt Request (Flag) Register 3868.3 PIE Registers87Register 8-7: PIE1: Peripheral Interrupt Enable Register 187Register 8-8: PIE2: Peripheral Interrupt Enable Register 288Register 8-9: PIE3: Peripheral Interrupt Enable Register 3898.4 IPR Registers90Register 8-10: IPR1: Peripheral Interrupt Priority Register 190Register 8-11: IPR2: Peripheral Interrupt Priority Register 291Register 8-12: IPR3: Peripheral Interrupt Priority Register 3928.5 RCON Register93Register 8-13: RCON: Reset Control Register938.6 INT Interrupts948.7 TMR0 Interrupt948.8 PORTB Interrupt-on-Change948.9 Context Saving During Interrupts94EXAMPLE 8-1: Saving Status, WREG and BSR Registers in RAM949.0 I/O Ports959.1 PORTA, TRISA and LATA Registers95EXAMPLE 9-1: Initializing PORTA95FIGURE 9-1: RA3:RA0 and RA5 Pins Block Diagram96FIGURE 9-2: RA4/T0CKI Pin Block Diagram96FIGURE 9-3: OSC2/CLKO/RA6 Pin Block Diagram96TABLE 9-1: PORTA Functions97TABLE 9-2: Summary of Registers Associated with PORTA979.2 PORTB, TRISB and LATB Registers98EXAMPLE 9-2: Initializing PORTB98FIGURE 9-4: RB7:RB4 Pins Block Diagram99FIGURE 9-5: RB1:RB0 Pins Block Diagram99FIGURE 9-6: RB2/CANTX/INT2 Pin Block Diagram100FIGURE 9-7: RB3/CANRX Pin Block Diagram100TABLE 9-3: PORTB Functions101TABLE 9-4: Summary of Registers Associated with PORTB1019.3 PORTC, TRISC and LATC Registers102EXAMPLE 9-3: Initializing PORTC102FIGURE 9-8: PORTC Block Diagram (Peripheral Output Override)102TABLE 9-5: PORTC Functions103TABLE 9-6: Summary of Registers Associated with PORTC1039.4 PORTD, TRISD and LATD Registers104EXAMPLE 9-4: Initializing PORTD104FIGURE 9-9: PORTD Block Diagram in I/O Port Mode104TABLE 9-7: PORTD Functions105TABLE 9-8: Summary of Registers Associated with PORTD1059.5 PORTE, TRISE and LATE Registers106EXAMPLE 9-5: Initializing PORTE106FIGURE 9-10: PortE Block Diagram106Register 9-1: TRISE Register107TABLE 9-9: PORTE Functions108TABLE 9-10: Summary of Registers Associated with PORTE10810.0 Parallel Slave Port109FIGURE 10-1: PORTD and PORTE Block Diagram (Parallel Slave Port)109FIGURE 10-2: Parallel Slave Port Write Waveforms109FIGURE 10-3: Parallel Slave Port Read Waveforms110TABLE 10-1: Registers Associated with Parallel Slave Port11011.0 Timer0 Module111Register 11-1: T0CON: Timer0 Control Register111FIGURE 11-1: Timer0 Block Diagram in 8-bit Mode112FIGURE 11-2: Timer0 Block Diagram in 16-bit Mode11211.1 Timer0 Operation11311.2 Prescaler11311.2.1 Switching Prescaler Assignment11311.3 Timer0 Interrupt11311.4 16-Bit Mode Timer Reads and Writes113TABLE 11-1: Registers Associated with Timer011312.0 Timer1 Module115Register 12-1: T1CON: Timer1 Control Register11512.1 Timer1 Operation116FIGURE 12-1: Timer1 Block Diagram116FIGURE 12-2: Timer1 Block Diagram: 16-bit Read/Write Mode11612.2 Timer1 Oscillator117TABLE 12-1: Capacitor Selection for the Alternate Oscillator11712.3 Timer1 Interrupt11712.4 Resetting Timer1 Using a CCP Trigger Output11712.5 Timer1 16-Bit Read/Write Mode117TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter11813.0 Timer2 Module11913.1 Timer2 Operation119Register 13-1: T2CON: Timer2 Control Register11913.2 Timer2 Interrupt12013.3 Output of TMR2120FIGURE 13-1: Timer2 Block Diagram120TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter12014.0 Timer3 Module121Register 14-1: T3CON:Timer3 Control Register12114.1 Timer3 Operation122FIGURE 14-1: Timer3 Block Diagram122FIGURE 14-2: Timer3 Block Diagram Configured in 16-bit Read/Write Mode12214.2 Timer1 Oscillator12314.3 Timer3 Interrupt12314.4 Resetting Timer3 Using a CCP Trigger Output123TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter12315.0 Capture/Compare/PWM (CCP) Modules125Register 15-1: CCP1CON: CCP1 Control Register12515.1 CCP1 Module126TABLE 15-1: CCP1 Mode – Timer Resource12615.2 Capture Mode12615.2.1 CCP Pin Configuration12615.2.2 Timer1/Timer3 Mode Selection126TABLE 15-2: Interaction of CCP1 and ECCP1 Modules12615.2.3 Software Interrupt12715.2.4 CCP1 Prescaler12715.2.5 CAN Message Time-Stamp127EXAMPLE 15-1: Changing Between Capture Prescalers127FIGURE 15-1: Capture Mode Operation Block Diagram12715.3 Compare Mode12815.3.1 CCP1 Pin Configuration12815.3.2 Timer1/Timer3 Mode Selection12815.3.3 Software Interrupt Mode12815.3.4 Special Event Trigger128FIGURE 15-2: Compare Mode Operation Block Diagram128TABLE 15-3: Registers Associated with Capture, Compare, Timer1 and Timer312915.4 PWM Mode130FIGURE 15-3: Simplified PWM Block Diagram130FIGURE 15-4: PWM Output13015.4.1 PWM Period130EQUATION 15-1:13015.4.2 PWM Duty Cycle130EQUATION 15-2:130EQUATION 15-3:13115.4.3 Setup for PWM Operation131TABLE 15-4: Example PWM Frequencies and Resolutions at 40 MHz131TABLE 15-5: Registers Associated with PWM and Timer213116.0 Enhanced Capture/ Compare/PWM (ECCP) Module133Register 16-1: ECCP1Con: ECCP1 Control Register13316.1 ECCP1 Module134TABLE 16-1: ECCP1 Mode – Timer Resource134TABLE 16-2: Interaction of CCP1 and ECCP1 Modules134TABLE 16-3: Pin Assignments for Various ECCP Modes13416.2 Capture Mode13516.2.1 CAN Message TIME-STAMP13516.3 Compare Mode13516.3.1 Special Event Trigger135TABLE 16-4: Registers Associated with Enhanced Capture, Compare, Timer1 and Timer313516.4 Standard PWM Mode13616.5 Enhanced PWM Mode13616.5.1 PWM Output Configurations136FIGURE 16-1: Simplified Block Diagram of the Enhanced PWM Module136FIGURE 16-2: PWM Output Relationships13716.5.2 Half-Bridge Mode138FIGURE 16-3: Half-Bridge PWM Output138FIGURE 16-4: Examples of Half-Bridge Output Mode Applications13816.5.3 Full-Bridge Mode139FIGURE 16-5: Full-Bridge PWM Output139FIGURE 16-6: Example of Full-Bridge Application140FIGURE 16-7: PWM Direction Change141FIGURE 16-8: PWM Direction Change at Near 100% Duty Cycle14116.5.4 Programmable Dead-Band Delay14216.5.5 System Implementation14216.5.6 Start-up Considerations14216.5.7 Output Polarity Configuration142Register 16-2: ECCP1DEL: PWM Delay Register14216.5.8 Setup for PWM Operation143TABLE 16-5: Registers Associated with Enhanced PWM and Timer214316.6 Enhanced CCP Auto-Shutdown144Register 16-3: ECCPAS: Enhanced Capture/Compare/PWM Auto-Shutdown Control Register14417.0 Master Synchronous Serial Port (MSSP) Module14517.1 Master SSP (MSSP) Module Overview14517.2 Control Registers14517.3 SPI Mode145FIGURE 17-1: MSSP Block Diagram (SPI™Mode)14517.3.1 Registers146Register 17-1: SSPSTAT: MSSP Status Register (SPI Mode)146Register 17-2: SSPCON1: MSSP Control Register 1 (SPI Mode)14717.3.2 Operation148EXAMPLE 17-1: Loading the SSPBUF (SSPSR) Register14817.3.3 Enabling SPI I/O14917.3.4 Typical Connection149FIGURE 17-2: SPI™ Master/Slave Connection14917.3.5 Master Mode150FIGURE 17-3: SPI™ Mode Waveform (Master Mode)15017.3.6 Slave Mode15117.3.7 Slave Select Synchronization151FIGURE 17-4: Slave Synchronization Waveform151FIGURE 17-5: SPI™ Mode Waveform (Slave Mode with CKE = 0)152FIGURE 17-6: SPI™ Mode Waveform (Slave Mode with CKE = 1)15217.3.8 Sleep Operation15317.3.9 Effects of a Reset15317.3.10 Bus Mode Compatibility153TABLE 17-1: SPI™ Bus Modes153TABLE 17-2: Registers Associated with SPI™ Operation15317.4 I2C Mode154FIGURE 17-7: MSSP Block Diagram (I2C™ Mode)15417.4.1 Registers154Register 17-3: SSPSTAT: MSSP Status Register (I2C Mode)155Register 17-4: SSPCON1: MSSP Control Register 1 (I2C Mode)156Register 17-5: SSPCON2: MSSP Control Register 2 (I2C Mode)15717.4.2 Operation15817.4.3 Slave Mode158FIGURE 17-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)160FIGURE 17-9: I2C™ Slave Mode Timing (Transmission, 7-bit Address)161FIGURE 17-10: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)162FIGURE 17-11: I2C™ Slave Mode Timing (Transmission, 10-bit Address)16317.4.4 Clock Stretching164FIGURE 17-12: Clock Synchronization Timing165FIGURE 17-13: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)166FIGURE 17-14: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)16717.4.5 General Call Address Support168FIGURE 17-15: Slave Mode General Call Address Sequence (7 or 10-bit Address Mode)16817.4.6 Master Mode169FIGURE 17-16: MSSP Block Diagram (I2C™ Master Mode)16917.4.7 Baud Rate Generator171FIGURE 17-17: Baud Rate Generator Block Diagram171TABLE 17-3: I2C™ Clock Rate w/BRG171FIGURE 17-18: Baud Rate Generator Timing with Clock Arbitration17217.4.8 I2C Master Mode Start Condition Timing173FIGURE 17-19: First Start Bit Timing17317.4.9 I2C Master Mode Repeated Start Condition Timing174FIGURE 17-20: Repeated Start Condition Waveform17417.4.10 I2C Master Mode Transmission17517.4.11 I2C Master Mode Reception175FIGURE 17-21: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Address)176FIGURE 17-22: I2C™ Master Mode Waveform (Reception, 7-bit Address)17717.4.12 Acknowledge Sequence Timing17817.4.13 Stop Condition Timing178FIGURE 17-23: Acknowledge Sequence Waveform178FIGURE 17-24: Stop Condition Receive or Transmit Mode17817.4.14 Sleep Operation17917.4.15 Effect of a Reset17917.4.16 Multi-Master Mode17917.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration179FIGURE 17-25: Bus Collision Timing for Transmit and Acknowledge179FIGURE 17-26: Bus Collision During Start Condition (SDA Only)180FIGURE 17-27: Bus Collision During Start Condition (SCL = 0)181FIGURE 17-28: BRG Reset Due to SDA Arbitration During Start Condition181FIGURE 17-29: Bus Collision During a Repeated Start Condition (Case 1)182FIGURE 17-30: Bus Collision During a Repeated Start Condition (Case 2)182FIGURE 17-31: Bus Collision During a Stop Condition (Case 1)183FIGURE 17-32: Bus Collision During a Stop Condition (Case 2)18318.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)185Register 18-1: TXSTA: Transmit Status and Control Register185Register 18-2: RCSTA: Receive Status and Control Register18618.1 USART Baud Rate Generator (BRG)18718.1.1 Sampling187EXAMPLE 18-1: Calculating Baud Rate Error187TABLE 18-1: Baud Rate Formula187TABLE 18-2: Registers Associated with Baud Rate Generator187TABLE 18-3: Baud Rates for Synchronous Mode188TABLE 18-4: Baud Rates for Asynchronous Mode (BRGH = 0)189TABLE 18-5: Baud Rates for Asynchronous Mode (BRGH = 1)19018.2 USART Asynchronous Mode19118.2.1 USART Asynchronous Transmitter191FIGURE 18-1: USART Transmit Block Diagram191FIGURE 18-2: Asynchronous Transmission192FIGURE 18-3: Asynchronous Transmission (Back to Back)192TABLE 18-6: Registers Associated with Asynchronous Transmission19218.2.2 USART Asynchronous Receiver19318.2.3 Setting Up 9-bit Mode with Address Detect193FIGURE 18-4: USART Receive Block Diagram193FIGURE 18-5: Asynchronous Reception194TABLE 18-7: Registers Associated with Asynchronous Reception19418.3 USART Synchronous Master Mode19518.3.1 USART Synchronous Master Transmission195TABLE 18-8: Registers Associated with Synchronous Master Transmission195FIGURE 18-6: Synchronous Transmission196FIGURE 18-7: Synchronous Transmission (Through TXEN)19618.3.2 USART Synchronous Master Reception197TABLE 18-9: Registers Associated with Synchronous Master Reception197FIGURE 18-8: Synchronous Reception (Master Mode, SREN)19718.4 USART Synchronous Slave Mode19818.4.1 USART Synchronous Slave Transmit19818.4.2 USART Synchronous Slave Reception198TABLE 18-10: Registers Associated with Synchronous Slave Transmission199TABLE 18-11: Registers Associated with Synchronous Slave Reception19919.0 CAN Module20119.1 Overview20119.1.1 Overview of the Module20119.1.2 Transmit/Receive Buffers201FIGURE 19-1: CAN Buffers and Protocol Engine Block Diagram20219.2 CAN Module Registers20319.2.1 CAN Control and Status Registers203Register 19-1: CANCON: CAN Control Register203Register 19-2: CANSTAT: CAN Status Register204EXAMPLE 19-1: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers205EXAMPLE 19-1: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers (Cont...206Register 19-3: COMSTAT: Communication Status Register20719.2.2 CAN Transmit Buffer Registers208Register 19-4: TXBnCON: Transmit Buffer n Control Registers208Register 19-5: TXBnSIDH: Transmit Buffer n Standard Identifier, High Byte Registers209Register 19-6: TXBnSIDL: Transmit Buffer n Standard Identifier, Low Byte Registers209Register 19-7: TXBnEIDH: Transmit Buffer n Extended Identifier, High Byte Registers209Register 19-8: TXBnEIDL: Transmit Buffer n Extended Identifier, Low Byte Registers210Register 19-9: TXBnDm: Transmit Buffer n Data Field Byte m Registers210Register 19-10: TXBnDLC: Transmit Buffer N Data Length Code Registers211Register 19-11: TXERRCNT: Transmit Error Count Register21119.2.3 CAN Receive Buffer Registers212Register 19-12: RXB0CON: Receive Buffer 0 Control Register212Register 19-13: RXB1CON: Receive Buffer 1 Control Register213Register 19-14: RXBnSIDH: Receive Buffer N Standard Identifier, High Byte Registers214Register 19-15: RXBnSIDL: Receive Buffer N Standard Identifier, Low Byte Registers214Register 19-16: RXBnEIDH: Receive Buffer N Extended Identifier, High Byte Registers214Register 19-17: RXBnEIDL: Receive Buffer N Extended Identifier, Low Byte Registers215Register 19-18: RXBnDLC: Receive Buffer N Data Length Code Registers215Register 19-19: RXBnDm: Receive Buffer N Data Field Byte M Registers216Register 19-20: RXERRCNT: Receive Error Count Register216Register 19-21: RXFnSIDH: Receive Acceptance Filter N Standard Identifier Filter, High Byte Regis...217Register 19-22: RXFnSIDL: Receive Acceptance Filter N Standard Identifier Filter, Low Byte Registers217Register 19-23: RXFnEIDH: Receive Acceptance Filter N Extended Identifier, High Byte Registers218Register 19-24: RXFnEIDL: Receive Acceptance Filter N Extended Identifier, Low Byte Registers218Register 19-25: RXMnSIDH: Receive Acceptance Mask N Standard Identifier Mask, High Byte Registers218Register 19-26: RXMnSIDL: Receive Acceptance Mask N Standard Identifier Mask, Low Byte Registers219Register 19-27: RXMnEIDH: Receive Acceptance Mask N Extended Identifier Mask, High Byte Registers219Register 19-28: RXMnEIDL: Receive Acceptance Mask N Extended Identifier Mask, Low Byte Registers21919.2.4 CAN Baud Rate Registers220Register 19-29: BRGCON1: Baud Rate Control Register 1220Register 19-30: BRGCON2: Baud Rate Control Register 2221Register 19-31: BRGCON3: Baud Rate Control Register 322219.2.5 CAN Module I/O Control Register223Register 19-32: CIOCON: CAN I/O Control Register22319.2.6 CAN Interrupt Registers224Register 19-33: PIR3: Peripheral Interrupt Request (Flag) Register 3224Register 19-34: PIE3: Peripheral Interrupt Enable Register 3225Register 19-35: IPR3: Peripheral Interrupt Priority Register 3226TABLE 19-1: CAN Controller Register Map22719.3 CAN Modes of Operation22819.3.1 Configuration Mode22819.3.2 Disable Mode22819.3.3 Normal Mode22819.3.4 Listen Only Mode22819.3.5 Loopback Mode22919.3.6 Error Recognition Mode22919.4 CAN Message Transmission22919.4.1 Transmit Buffers22919.4.2 Transmit Priority229FIGURE 19-2: Transmit Buffer Block Diagram22919.4.3 Initiating Transmission23019.4.4 Aborting Transmission230FIGURE 19-3: Internal Transmit Message Flowchart23119.5 Message Reception23219.5.1 Receive Message Buffering23219.5.2 Receive Buffers23219.5.3 Receive Priority23219.5.4 Time-Stamping232FIGURE 19-4: Receive Buffer Block Diagram232FIGURE 19-5: Internal Message Reception Flowchart23319.6 Message Acceptance Filters and Masks234TABLE 19-2: Filter/Mask Truth Table234FIGURE 19-6: Message Acceptance Mask and Filter Operation23419.7 Baud Rate Setting235FIGURE 19-7: Bit Time Partitioning23519.7.1 Time Quanta236EXAMPLE 19-2: Calculating Tq, Nominal Bit Rate and Nominal Bit Time23619.7.2 Synchronization Segment23619.7.3 Propagation Segment23619.7.4 Phase Buffer Segments23619.7.5 Sample Point23619.7.6 Information Processing Time23619.8 Synchronization23719.8.1 Hard Synchronization23719.8.2 Resynchronization23719.8.3 synchronization rules237FIGURE 19-8: Lengthening a Bit Period (Adding SJW to Phase Segment 1)237FIGURE 19-9: Shortening a Bit Period (Subtracting SJW From Phase Segment 2)23819.9 Programming Time Segments23819.10 Oscillator Tolerance23819.11 Bit Timing Configuration Registers23819.11.1 BRGCON123819.11.2 BRGCON223819.11.3 BRGCON323819.12 Error Detection23919.12.1 CRC Error23919.12.2 Acknowledge Error23919.12.3 Form Error23919.12.4 Bit Error23919.12.5 Stuff Bit Error23919.12.6 Error States23919.12.7 Error Modes and Error Counters239FIGURE 19-10: Error Modes State Diagram24019.13 CAN Interrupts24019.13.1 Interrupt Code Bits24019.13.2 Transmit Interrupt24019.13.3 Receive Interrupt240TABLE 19-3: Values for ICODE<2:0>24119.13.4 Message Error Interrupt24119.13.5 Bus Activity Wake-up Interrupt24119.13.6 Error Interrupt24119.13.7 Interrupt Acknowledge24120.0 Compatible 10-Bit Analog- to-Digital Converter (A/D) Module243Register 20-1: ADCON0: A/D Control Register 0243Register 20-2: ADCON1: A/D Control Register 1244FIGURE 20-1: A/D Block Diagram24520.1 A/D Acquisition Requirements246FIGURE 20-2: Analog Input Model246EQUATION 20-1: Acquisition Time247EQUATION 20-2: A/D Minimum Charging Time247EXAMPLE 20-1: Calculating The Minimum Required Acquisition Time24720.2 Selecting the A/D Conversion Clock24820.3 Configuring Analog Port Pins248TABLE 20-1: Tad vs. Device Operating Frequencies248TABLE 20-2: Tad vs. Device Operating Frequencies (for Extended, LF Devices)24820.4 A/D Conversions24920.4.1 A/D Result Registers249FIGURE 20-3: A/D Result Justification24920.5 Use of the ECCP Trigger250FIGURE 20-4: A/D Conversion Tad Cycles250TABLE 20-3: Summary of A/D Registers25021.0 Comparator Module251Register 21-1: CMCON: Comparator Control Register25121.1 Comparator Configuration252FIGURE 21-1: Comparator I/O Operating Modes25221.2 Comparator Operation25321.3 Comparator Reference253FIGURE 21-2: Single Comparator25321.3.1 External Reference Signal25321.3.2 Internal Reference Signal25321.4 Comparator Response Time25321.5 Comparator Outputs253FIGURE 21-3: Comparator Output Block Diagram25421.6 Comparator Interrupts25421.7 Comparator Operation During Sleep25521.8 Effects of a Reset25521.9 Analog Input Connection Considerations255FIGURE 21-4: Analog Input Model255TABLE 21-1: Registers Associated with Comparator Module25622.0 Comparator Voltage Reference Module25722.1 Configuring the Comparator Voltage Reference257EQUATION 22-1:257EQUATION 22-2:257Register 22-1: CVRCON: Comparator Voltage Reference Control Register257FIGURE 22-1: Voltage Reference Block Diagram25822.2 Voltage Reference Accuracy/Error25822.3 Operation During Sleep25822.4 Effects of a Reset25822.5 Connection Considerations258FIGURE 22-2: Voltage Reference Output Buffer Example259TABLE 22-1: Registers Associated with Comparator Voltage Reference25923.0 Low-Voltage Detect261FIGURE 23-1: Typical Low-Voltage Detect Application261FIGURE 23-2: Low-Voltage Detect (LVD) Block Diagram262FIGURE 23-3: Low-Voltage Detect (LVD) with External Input Block Diagram26223.1 Control Register263Register 23-1: LVDCON: Low-Voltage Detect Control Register26323.2 Operation264FIGURE 23-4: Low-Voltage Detect Waveforms26423.2.1 Reference Voltage Set Point26523.2.2 Current Consumption26523.3 Operation During Sleep26523.4 Effects of a Reset26524.0 Special Features of the CPU26724.1 Configuration Bits267TABLE 24-1: Configuration Bits and Device IDs267Register 24-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)268Register 24-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)268Register 24-3: config2h: Configuration Register 2 High (Byte Address 300003h)269Register 24-4: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)269Register 24-5: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)270Register 24-6: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)270Register 24-7: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)271Register 24-8: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)271Register 24-9: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)272Register 24-10: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)272Register 24-11: DEVID1: Device ID Register 1 for PIC18FXX8 Devices (Byte Address 3FFFFEh)273Register 24-12: DEVID2: Device ID Register 2 for PIC18FXX8 Devices (Byte Address 3FFFFFh)27324.2 Watchdog Timer (WDT)27424.2.1 Control Register274Register 24-13: WDTCON: Watchdog Timer Control Register27424.2.2 WDT Postscaler275FIGURE 24-1: Watchdog Timer Block Diagram275TABLE 24-2: Summary of Watchdog Timer Registers27524.3 Power-Down Mode (Sleep)27624.3.1 Wake-up From Sleep27624.3.2 Wake-up Using Interrupts276FIGURE 24-2: Wake-up From Sleep Through Interrupt(1,2)27724.4 Program Verification and Code Protection278FIGURE 24-3: Code-Protected Program Memory for PIC18FXX8278TABLE 24-3: Summary of Code Protection Registers27824.4.1 Program Memory Code Protection279FIGURE 24-4: Table Write (WRTn) Disallowed279FIGURE 24-5: External Block Table Read (EBTRn) Disallowed280FIGURE 24-6: External Block Table Read (EBTRn) Allowed28024.4.2 Data EEPROM Code Protection28124.4.3 Configuration Register Protection28124.5 ID Locations28124.6 In-Circuit Serial Programming28124.7 In-Circuit Debugger28124.8 Low-Voltage ICSP Programming28125.0 Instruction Set Summary28325.1 ReadModify-Write Operations283TABLE 25-1: Opcode Field Descriptions284FIGURE 25-1: General Format for Instructions285TABLE 25-2: PIC18FXXX Instruction Set28625.2 Instruction Set28926.0 Development Support32526.1 MPLAB Integrated Development Environment Software32526.2 MPASM Assembler32526.3 MPLAB C17 and MPLAB C18 C Compilers32626.4 MPLINK Object Linker/ MPLIB Object Librarian32626.5 MPLAB C30 C Compiler32626.6 MPLAB ASM30 Assembler, Linker and Librarian32626.7 MPLAB SIM Software Simulator32626.8 MPLAB SIM30 Software Simulator32626.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator32726.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator32726.11 MPLAB ICD 2 In-Circuit Debugger32726.12 PRO MATE II Universal Device Programmer32726.13 MPLAB PM3 Device Programmer32726.14 PICSTART Plus Development Programmer32826.15 PICDEM 1 PICmicro Demonstration Board32826.16 PICDEM.net Internet/Ethernet Demonstration Board32826.17 PICDEM 2 Plus Demonstration Board32826.18 PICDEM 3 PIC16C92X Demonstration Board32826.19 PICDEM 4 8/14/18-Pin Demonstration Board32826.20 PICDEM 17 Demonstration Board32926.21 PICDEM 18R PIC18C601/801 Demonstration Board32926.22 PICDEM LIN PIC16C43X Demonstration Board32926.23 PICkitTM 1 Flash Starter Kit32926.24 PICDEM USB PIC16C7X5 Demonstration Board32926.25 Evaluation and Programming Tools32927.0 Electrical Characteristics331Absolute Maximum Ratings(†)331FIGURE 27-1: PIC18FXX8 Voltage-Frequency Graph (Industrial)332FIGURE 27-2: PIC18FXX8 Voltage-Frequency Graph (Extended)332FIGURE 27-3: PIC18LFXX8 Voltage-Frequency Graph (Industrial)33327.1 DC Characteristics33427.2 DC Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial)338FIGURE 27-4: Low-Voltage Detect Characteristics340TABLE 27-1: Low-Voltage Detect Characteristics340TABLE 27-2: DC Characteristics: EEPROM and Enhanced Flash341TABLE 27-3: Comparator Specifications342TABLE 27-4: Voltage Reference Specifications34227.3 AC (Timing) Characteristics34327.3.1 Timing Parameter Symbology34327.3.2 Timing Conditions344TABLE 27-5: Temperature and Voltage Specifications – AC344FIGURE 27-5: Load Conditions for Device Timing Specifications34427.3.3 Timing Diagrams and Specifications345FIGURE 27-6: External Clock Timing345TABLE 27-6: External Clock Timing Requirements345TABLE 27-7: PLL Clock Timing Specifications (Vdd = 4.2 to 5.5V)346FIGURE 27-7: CLKO and I/O Timing346TABLE 27-8: CLKO and I/O Timing Requirements346FIGURE 27-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing347FIGURE 27-9: Brown-out Reset and Low-Voltage Detect Timing347TABLE 27-9: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and...347FIGURE 27-10: Timer0 and Timer1 External Clock Timings348TABLE 27-10: Timer0 and Timer1 External Clock Requirements348FIGURE 27-11: Capture/Compare/PWM Timings (CCP1 and ECCP1)349TABLE 27-11: Capture/Compare/PWM Requirements (CCP1 and ECCP1)349FIGURE 27-12: Parallel Slave Port Timing (PIC18F248 and PIC18F458)350TABLE 27-12: Parallel Slave Port Requirements (PIC18F248 and PIC18F458)350FIGURE 27-13: Example SPI™ Master Mode Timing (CKE=0)351TABLE 27-13: Example SPI™ Mode Requirements (Master Mode, CKE=0)351FIGURE 27-14: Example SPI™ Master Mode Timing (CKE=1)352TABLE 27-14: Example SPI™ Mode Requirements (Master Mode, CKE=1)352FIGURE 27-15: Example SPI™ Slave Mode Timing (CKE=0)353TABLE 27-15: Example SPI™ Mode Requirements, Slave Mode Timing (CKE=0)353FIGURE 27-16: Example SPI™ Slave Mode Timing (CKE=1)354TABLE 27-16: Example SPI™ Slave Mode Requirements (CKE=1)354FIGURE 27-17: I2C™ Bus Start/Stop Bits Timing355TABLE 27-17: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)355FIGURE 27-18: I2C™ Bus Data Timing355TABLE 27-18: I2C™ Bus Data Requirements (Slave Mode)356FIGURE 27-19: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms357TABLE 27-19: Master SSP I2C™ Bus Start/Stop Bits Requirements357FIGURE 27-20: Master SSP I2C™ Bus Data Timing357TABLE 27-20: Master SSP I2C™ Bus Data Requirements358FIGURE 27-21: USART Synchronous Transmission (Master/Slave) Timing359TABLE 27-21: USART Synchronous Transmission Requirements359FIGURE 27-22: USART Synchronous Receive (Master/Slave) Timing359TABLE 27-22: USART Synchronous Receive Requirements359TABLE 27-23: A/D Converter Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial)360FIGURE 27-23: A/D Conversion Timing361TABLE 27-24: A/D Conversion Requirements36128.0 DC and AC Characteristics Graphs and Tables363FIGURE 28-1: Typical Idd vs. Fosc Over Vdd (Hs Mode)363FIGURE 28-2: Maximum Idd vs. Fosc Over Vdd (Hs Mode)363FIGURE 28-3: Typical Idd vs. Fosc Over Vdd (HS/PLL Mode)364FIGURE 28-4: Maximum Idd vs. Fosc Over Vdd (HS/PLL Mode)364FIGURE 28-5: Typical Idd vs. Fosc Over Vdd (XT Mode)365FIGURE 28-6: Maximum Idd vs. Fosc Over Vdd (XT Mode)365FIGURE 28-7: Typical Idd vs. Fosc Over Vdd (LP Mode)366FIGURE 28-8: Maximum Idd vs. Fosc Over Vdd (LP Mode)366FIGURE 28-9: Typical Idd vs. Fosc Over Vdd (EC Mode)367FIGURE 28-10: Maximum Idd vs. Fosc Over Vdd (EC Mode)367FIGURE 28-11: Typical and Maximum Idd vs. Vdd (Timer1 as Main Oscillator 32.768kHz, C1 and C2 = ...368FIGURE 28-12: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 20 pF, +25°C)368FIGURE 28-13: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 100pF, +25°C)369FIGURE 28-14: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 300pF, +25°C)369FIGURE 28-15: Ipd vs. Vdd, -40°C to +125°C (Sleep Mode, All Peripherals Disabled)370FIGURE 28-16: DIbor vs. Vdd Over Temperature (BOR Enabled, Vbor = 2.00-2.16V)370FIGURE 28-17: Typical and Maximum DItmr1 vs. Vdd Over Temperature (-10°C to +70°C, Timer1 with Os...371FIGURE 28-18: Typical and Maximum DIwdt vs. Vdd Over Temperature (WDT Enabled)371FIGURE 28-19: Typical, Minimum and Maximum WDT Period vs. Vdd (-40°C to +125°C)372FIGURE 28-20: DIlvd vs. Vdd Over Temperature (LVD Enabled, Vlvd = 4.5 - 4.78V)372FIGURE 28-21: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 5V, -40°C to +125°C)373FIGURE 28-22: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 3V, -40°C to +125°C)373FIGURE 28-23: Typical and Maximum Vol vs. Iol (Vdd = 5V, -40°C to +125°C)374FIGURE 28-24: Typical and Maximum Vol vs. Iol (Vdd = 3V, -40°C to +125°C)374FIGURE 28-25: Minimum and Maximum Vin vs. Vdd (ST Input, -40°C to +125°C)375FIGURE 28-26: Minimum and Maximum Vin vs. Vdd (TTL Input, -40°C to +125°C)375FIGURE 28-27: Minimum and Maximum Vin vs. Vdd (I2C™ Input, -40°C to +125°C)376FIGURE 28-28: A/D Nonlinearity vs. Vrefh (Vdd = Vrefh, -40°C to +125°C)376FIGURE 28-29: A/D Nonlinearity vs. Vrefh (Vdd = 5V, -40°C to +125°C)37729.0 Packaging Information37929.1 Package Marking Information37929.1 Package Marking Information (Continued)38029.2 Package Details38128-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)38128-Lead Plastic Small Outline (SO) –Wide, 300 mil Body (SOIC)38240-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)38344-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)38444-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)385Appendix A: Data Sheet Revision History387Revision A (June 2001)387Revision B (May 2002)387Revision C (January 2003)387Revision D (September 2004)387Revision E (October 2006)387Appendix B: Device Differences387TABLE B-1: Device Differences387Appendix C: Device Migrations388Appendix D: Migrating From Other PICmicro® Devices388INDEX389The Microchip Web Site399Customer Change Notification Service399Customer Support399Reader Response400PIC18FXX8 Product Identification System401Worldwide Sales and Service402Size: 6.56 MBPages: 402Language: EnglishOpen manual