Data Sheet (PIC16F676-I/ST)Table of ContentsHigh-Performance RISC CPU:3Special Microcontroller Features:3Low-Power Features:3Peripheral Features:3Pin Diagrams4Most Current Data Sheet5Errata5Customer Notification System51.0 Device Overview7FIGURE 1-1: PIC16F630/676 block diagram7TABLE 1-1: PIC16F630/676 Pinout Description82.0 Memory Organization92.1 Program Memory Organization9FIGURE 2-1: Program Memory Map and Stack for the PIC16F630/67692.2 Data Memory Organization92.2.1 General Purpose Register File92.2.2 Special FUNCTION Registers10FIGURE 2-2: Data Memory Map of the PIC16F630/67610TABLE 2-1: PIC16F630/676 Special Registers Summary Bank 011TABLE 2-2: PIC16F630/676 Special Function Registers Summary Bank 1122.3 PCL and PCLATH19FIGURE 2-3: Loading Of PC In Different Situations192.3.1 computed goto192.3.2 Stack192.4 Indirect Addressing, INDF and FSR Registers20FIGURE 2-4: Direct/Indirect Addressing PIC16F630/676203.0 Ports A and C213.1 PORTA and the TRISA Registers213.2 Additional Pin Functions213.2.1 Weak Pull-up213.2.2 Interrupt-on-change223.2.3 Pin Descriptions and Diagrams24FIGURE 3-1: Block Diagram of RA0 and RA1 Pins24FIGURE 3-2: Block Diagram of RA225FIGURE 3-3: Block Diagram of RA325FIGURE 3-4: Block Diagram of RA426FIGURE 3-5: Block Diagram of RA526TABLE 3-1: Summary of Registers Associated with PORTA273.3 PORTC283.3.1 RC0/AN4, RC1/AN5, RC2/AN6, RC3/ AN728FIGURE 3-6: BLOCK DIAGRAM OF RC0/RC1/RC2/RC3 PINs283.3.2 RC4 and RC528FIGURE 3-7: BLOCK DIAGRAM OF RC4 AND RC5 PINS28TABLE 3-2: Summary of Registers Associated with PORTC294.0 Timer0 Module314.1 Timer0 Operation314.2 Timer0 Interrupt31FIGURE 4-1: Block Diagram of thE Timer0/WDT Prescaler314.3 Using Timer0 with an External Clock324.4 Prescaler334.4.1 Switching Prescaler Assignment33TABLE 4-1: Registers Associated with Timer0335.0 Timer1 Module with Gate Control34FIGURE 5-1: TIMER1 BLOCK DIAGRAM345.1 Timer1 Modes of Operation355.2 Timer1 Interrupt355.3 Timer1 Prescaler35FIGURE 5-2: TIMER1 INCREMENTING EDGE355.4 Timer1 Operation in Asynchronous Counter Mode375.4.1 Reading and writing Timer1 in asynchronous counter mode375.5 Timer1 Oscillator375.6 Timer1 Operation During Sleep37TABLE 5-1: Registers Associated with Timer1 as a Timer/Counter376.0 Comparator Module396.1 Comparator Operation40TABLE 6-1: Output state vs. input conditions40FIGURE 6-1: Single Comparator406.2 Comparator Configuration41FIGURE 6-2: Comparator I/O operating Modes416.3 Analog Input Connection Considerations42FIGURE 6-3: Analog Input Mode426.4 Comparator Output42FIGURE 6-4: Modified Comparator Output Block Diagram426.5 Comparator Reference436.5.1 Configuring the Voltage Reference436.5.2 Voltage Reference Accuracy/Error43FIGURE 6-5: Comparator VOLTAGE REFERENCE BLOCK DIAGRAM436.6 Comparator Response Time436.7 Operation During Sleep436.8 Effects of a Reset436.9 Comparator Interrupts44TABLE 6-2: Registers Associated with Comparator Module447.0 Analog-to-Digital Converter (A/D) Module (PIC16F676 only)45FIGURE 7-1: A/D Block Diagram457.1 A/D Configuration and Operation457.1.1 Analog Port Pins457.1.2 Channel Selection457.1.3 Voltage Reference457.1.4 Conversion Clock45TABLE 7-1: Tad VS. DEVICE OPERATING FREQUENCIES467.1.5 Starting a Conversion467.1.6 Conversion Output46FIGURE 7-2: 10-Bit A/D Result Format467.2 A/D Acquisition Requirements49FIGURE 7-3: Analog Input Model497.3 A/D Operation During Sleep507.4 Effects of Reset50TABLE 7-2: Summary of A/D Registers508.0 Data EEPROM Memory518.1 EEADR528.2 EECON1 AND EECON2 REGISTERS528.3 READING THE EEPROM DATA MEMORY538.4 WRITING TO THE EEPROM DATA MEMORY538.5 WRITE VERIFY538.5.1 Using the data EEprom538.6 PROTECTION AGAINST SPURIOUS WRITE538.7 DATA EEPROM OPERATION DURING CODE-PROTECT54TABLE 8-1: Registers/Bits Associated with Data EEPROM549.0 Special Features of the CPU559.1 Configuration Bits569.2 Oscillator Configurations579.2.1 Oscillator Types579.2.2 Crystal Oscillator / CERAmic Resonators57FIGURE 9-1: Crystal Operation (or Ceramic Resonator) (HS, XT or LP Osc Configuration)57FIGURE 9-2: External Clock Input Operation (HS, XT, EC, or LP Osc Configuration)57TABLE 9-1: Capacitor Selection for Ceramic Resonators57TABLE 9-2: Capacitor Selection for Crystal Oscillator579.2.3 External Clock In589.2.4 RC Oscillator58FIGURE 9-3: RC OSCILLATOR MODE589.2.5 Internal 4 MHz Oscillator589.2.6 CLKOUT589.3 Reset59FIGURE 9-4: Simplified Block Diagram of On-chip Reset Circuit599.3.1 MCLR60FIGURE 9-5: Recommended MCLR Circuit609.3.2 Power-On Reset (POR)609.3.3 Power-up Timer (PWRT)609.3.4 Oscillator Start-up Timer (OST)609.3.5 Brown-out Detect (BOD)61FIGURE 9-6: Brown-out Situations619.3.6 Time-out Sequence619.3.7 Power Control (PCON) Status Register61TABLE 9-3: Time-out in Various Situations62TABLE 9-4: Status/PCON Bits and Their Significance62TABLE 9-5: Summary of Registers Associated with Brown-out62TABLE 9-6: Initialization Condition for Special Registers62TABLE 9-7: Initialization Condition for Registers63FIGURE 9-7: Time-out Sequence on Power-up (MCLR not tied to Vdd): Case 164FIGURE 9-8: Time-out Sequence on Power-up (MCLR not tied to Vdd): Case 264FIGURE 9-9: Time-out Sequence on Power-up (MCLR tied to Vdd)649.4 Interrupts65FIGURE 9-10: INTERRUPT LOGIC669.4.1 RA2/INT Interrupt679.4.2 TMR0 Interrupt679.4.3 PORTA Interrupt679.4.4 Comparator Interrupt679.4.5 A/D Converter Interrupt67FIGURE 9-11: INT Pin Interrupt Timing67TABLE 9-8: Summary of interrupt registers689.5 Context Saving During Interrupts689.6 Watchdog Timer (WDT)689.6.1 WDT Period689.6.2 WDT Programming Considerations68FIGURE 9-12: Watchdog Timer Block Diagram69TABLE 9-9: Summary of Watchdog Timer Registers699.7 Power-Down Mode (Sleep)709.7.1 Wake-up from SLEEP70FIGURE 9-13: Wake-up from Sleep Through Interrupt709.8 Code Protection719.9 ID Locations719.10 In-Circuit Serial Programming71FIGURE 9-14: Typical In-Circuit Serial Programming Connection719.11 In-Circuit Debugger71TABLE 9-10: Debugger resources7110.0 Instruction Set Summary7310.1 READ-MODIFY-WRITE OPERATIONS73TABLE 10-1: Opcode Field Descriptions73FIGURE 10-1: General Format for Instructions73TABLE 10-2: PIC16F630/676 Instruction Set7410.2 Instruction Descriptions7511.0 Development Support8111.1 MPLAB Integrated Development Environment Software8111.2 MPLAB C Compilers for Various Device Families8211.3 HI-TECH C for Various Device Families8211.4 MPASM Assembler8211.5 MPLINK Object Linker/ MPLIB Object Librarian8211.6 MPLAB Assembler, Linker and Librarian for Various Device Families8211.7 MPLAB SIM Software Simulator8311.8 MPLAB REAL ICE In-Circuit Emulator System8311.9 MPLAB ICD 3 In-Circuit Debugger System8311.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express8311.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express8411.12 MPLAB PM3 Device Programmer8411.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits8412.0 Electrical Specifications85FIGURE 12-1: PIC16F630/676 With A/D Disabled Voltage-Frequency Graph, -40°C £ ta £ +125°C86FIGURE 12-2: PIC16F676 With A/D Enabled Voltage-Frequency Graph, -40°C £ ta £ +125°C86FIGURE 12-3: PIC16F676 With A/D Enabled Voltage-Frequency Graph, 0°C £ ta £ +125°C8712.1 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended)8812.2 DC Characteristics: PIC16F630/676-I (Industrial)8912.3 DC Characteristics: PIC16F630/676-I (Industrial)9012.4 DC Characteristics: PIC16F630/676-E (Extended)9112.5 DC Characteristics: PIC16F630/676-E (Extended)9212.6 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended)9312.7 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended) (Cont.)9412.8 Timing Parameter Symbology95FIGURE 12-4: LOAD CONDITIONS9512.9 AC Characteristics: PIC16F630/676 (Industrial, Extended)96FIGURE 12-5: External Clock Timing96TABLE 12-1: External Clock Timing Requirements96TABLE 12-2: pRECISION INTERNAL OSCILLATOR Parameters97FIGURE 12-6: CLKOUT and I/O Timing98TABLE 12-3: CLKOUT and I/O Timing Requirements98FIGURE 12-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing99FIGURE 12-8: Brown-out Detect Timing and Characteristics99TABLE 12-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Detect Requirements100FIGURE 12-9: Timer0 and Timer1 External Clock Timings101TABLE 12-5: Timer0 and Timer1 External Clock Requirements101TABLE 12-6: Comparator Specifications102TABLE 12-7: Comparator Voltage Reference Specifications102TABLE 12-8: PIC16F676 A/D Converter Characteristics:103FIGURE 12-10: PIC16F676 A/D Conversion Timing (Normal Mode)104TABLE 12-9: PIC16F676 A/D Conversion Requirements104FIGURE 12-11: PIC16F676 A/D Conversion Timing (Sleep Mode)105TABLE 12-10: PIC16F676 A/D Conversion Requirements (SLEEP Mode)10513.0 DC and AC Characteristics Graphs and Tables107FIGURE 13-1: Typical Ipd vs. Vdd OVER TEMP (-40°C to +25°C)107FIGURE 13-2: Typical Ipd vs. Vdd OVER TEMP (+85°C)107FIGURE 13-3: Typical Ipd vs. Vdd OVER TEMP (+125°C)108FIGURE 13-4: Maximum Ipd vs. Vdd OVER TEMP (-40°C to +25°C)108FIGURE 13-5: Maximum Ipd vs. Vdd OVER TEMP (+85°C)109FIGURE 13-6: Maximum Ipd vs. Vdd OVER TEMP (+125°C)109FIGURE 13-7: Typical Ipd with BOD Enabled vs. Vdd Over Temp (-40°C to +125°C)110FIGURE 13-8: Typical Ipd with CMP Enabled vs. Vdd Over Temp (-40°C to +125°C)110FIGURE 13-9: Typical Ipd with A/D Enabled vs. Vdd Over Temp (-40°C to +25°C)111FIGURE 13-10: Typical Ipd with A/D Enabled vs. Vdd Over Temp (+85°C)111FIGURE 13-11: Typical Ipd with A/D Enabled vs. Vdd Over Temp (+125°C)112FIGURE 13-12: Typical Ipd with T1 OSC Enabled vs. Vdd Over Temp (-40°C to +125°C), 32 kHz, C1 and C2=50 pF)112FIGURE 13-13: Typical Ipd with CVref Enabled vs. Vdd Over Temp (-40°C to +125°C)113FIGURE 13-14: Typical Ipd with WDT Enabled vs. Vdd Over Temp (-40°C to +125°C)113FIGURE 13-15: MAXIMUM and MINIMUM INTOSC FREQ vs. Temperature with 0.1mF and 0.01mF decoupling (Vdd = 3.5V)114FIGURE 13-16: MAXIMUM and MINIMUM INTOSC FREQ vs. Vdd with 0.1mF and 0.01mF decoupling (+25°C)114FIGURE 13-17: Typical WDT Period vs. Vdd (-40°C to +125°C)11514.0 Packaging Information11714.1 Package Marking Information11714.2 Package Details118Appendix A: Data Sheet Revision History123Revision A123Revision B123Revision C123Revision D123Revision E (03/2007)123Revision F (05/2010)123Appendix B: Device Differences123TABLE B-1: Device Differences123Appendix C: Device Migrations124Appendix D: Migrating from other PIC® Devices124Index125The Microchip Web Site129Customer Change Notification Service129Customer Support129Reader Response130Product Identification System131Untitled132Size: 1.31 MBPages: 132Language: EnglishOpen manual