Microchip Technology IC PIC MCU PIC16F1937-I/PT TQFP-44 MCP User Manuals

Table of Contents

• Devices Included In This Data Sheet:

  3
• High-Performance RISC CPU:

  3
• Special Microcontroller Features:

  3
• PIC16LF193X Low-Power Features:

  3
• Peripheral Features:

  3
• Peripheral Features (Continued):

  4
• PIC16(L)F193X Family Types

  4
• Pin Diagram – 28-Pin SPDIP/SOIC/SSOP (PIC16(L)F1936)

  5
• Pin Diagram – 28-Pin QFN/UQFN (PIC16(L)F1936)

  6
  • TABLE 1: 28-Pin Summary (PIC16(L)F1936)

    7
• Pin Diagram – 40-Pin PDIP (PIC16(L)F1934/7)

  8
• Pin Diagram – 40-Pin UQFN 5x5 (PIC16(L)F1934/7)

  9
• Pin Diagram – 44-Pin QFN (PIC16(L)F1934/7)

  10
• Pin Diagram – 44-Pin TQFP (PIC16(L)F1934/7)

  11
  • TABLE 2: 40/44-Pin Summary(PIC16(L)F1934/7)

    12
• Table of Contents

  13
• Most Current Data Sheet

  14
• Errata

  14
• Customer Notification System

  14
• 1.0 Device Overview

  15
  • TABLE 1-1: Device Peripheral Summary

    15
  • FIGURE 1-1: PIC16(L)F1934/6/7 Block Diagram

    16
  • TABLE 1-2: PIC16(L)F1934/6/7 Pinout Description

    17
• 2.0 Enhanced Mid-range CPU

  23
  • 2.1 Automatic Interrupt Context Saving

    23
  • 2.2 16-level Stack with Overflow and Underflow

    23
  • 2.3 File Select Registers

    23
  • 2.4 Instruction Set

    23
    • FIGURE 2-1: Core Block Diagram

      24
• 3.0 Memory Organization

  25
  • 3.1 Program Memory Organization

    25
    • TABLE 3-1: Device Sizes and Addresses

      25
    • FIGURE 3-1: Program Memory Map And Stack For 4KW parts

      26
    • FIGURE 3-2: Program Memory Map And Stack For 8KW parts

      26
    • 3.1.1 Reading Program Memory as Data

      27
      • EXAMPLE 3-1: RETLW Instruction

        27
      • EXAMPLE 3-2: Accessing Program Memory Via FSR

        28
  • 3.2 Data Memory Organization

    28
    • 3.2.1 Core Registers

      28
      • Register 3-1: STATUS: STATUS Register

        29
    • 3.2.2 Special Function Register

      30
    • 3.2.3 General Purpose RAM

      30
    • 3.2.4 Common RAM

      30
      • FIGURE 3-3: Banked Memory Partitioning

        30
    • 3.2.5 Device Memory Maps

      30
      • TABLE 3-2: Memory Map Tables

        30
      • TABLE 3-3: PIC16(L)F1934 Memory Map, Banks 0-7

        31
      • TABLE 3-4: PIC16(L)F1934 Memory Map, Banks 8-15

        32
      • TABLE 3-5: PIC16(L)F1936/1937 Memory Map, Banks 0-7

        33
      • TABLE 3-6: PIC16(L)F1936/1937 Memory Map, Banks 8-15

        34
      • TABLE 3-7: PIC16(L)F1934/6/7 Memory Map, Banks 16-23

        35
      • TABLE 3-8: PIC16(L)F1934/6/7 Memory Map, Banks 24-31

        36
      • TABLE 3-9: PIC16(L)F1936 Memory Map, Bank 15

        37
      • TABLE 3-10: PIC16(L)F1934/7 Memory Map, Bank 15

        37
      • TABLE 3-11: PIC16(L)F1934/6/7 Memory Map, Bank 31

        38
    • 3.2.6 Special Function Registers Summary

      38
      • TABLE 3-12: Special Function Register Summary

        39
  • 3.3 PCL and PCLATH

    53
    • FIGURE 3-4: Loading Of PC In Different Situations

      53
    • 3.3.1 Modifying PCL

      53
    • 3.3.2 computed goto

      53
    • 3.3.3 Computed Function Calls

      53
    • 3.3.4 Branching

      53
  • 3.4 Stack

    54
    • 3.4.1 Accessing the Stack

      54
      • FIGURE 3-5: Accessing the Stack Example 1

        54
      • FIGURE 3-6: Accessing the Stack Example 2

        55
      • FIGURE 3-7: Accessing the Stack Example 3

        55
      • FIGURE 3-8: Accessing the Stack Example 4

        56
    • 3.4.2 Overflow/Underflow Reset

      56
  • 3.5 Indirect Addressing

    56
    • FIGURE 3-9: Indirect Addressing

      57
    • 3.5.1 Traditional Data Memory

      58
      • FIGURE 3-10: Traditional Data Memory Map

        58
    • 3.5.2 Linear Data Memory

      59
      • FIGURE 3-11: Linear Data Memory Map

        59
    • 3.5.3 Program Flash Memory

      59
      • FIGURE 3-12: Program Flash Memory Map

        59
• 4.0 Device Configuration

  61
  • 4.1 Configuration Words

    61
    • Register 4-1: Configuration Word 1

      62
    • Register 4-2: Configuration Word 2

      64
  • 4.2 Code Protection

    65
    • 4.2.1 Program Memory Protection

      65
    • 4.2.2 Data EEPROM Protection

      65
  • 4.3 Write Protection

    65
  • 4.4 User ID

    65
  • 4.5 Device ID and Revision ID

    66
    • Register 4-3: DEVICEID: Device ID Register(1)

      66
• 5.0 Oscillator Module (With Fail-Safe Clock Monitor)

  67
  • 5.1 Overview

    67
    • FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram

      68
  • 5.2 Clock Source Types

    69
    • 5.2.1 External Clock Sources

      69
      • FIGURE 5-2: External Clock (EC) Mode Operation

        69
      • FIGURE 5-3: Quartz Crystal Operation (LP, XT or HS Mode)

        70
      • FIGURE 5-4: Ceramic Resonator Operation (XT or HS Mode)

        70
      • FIGURE 5-5: Quartz Crystal Operation (Timer1 Oscillator)

        71
      • FIGURE 5-6: External RC Modes

        71
    • 5.2.2 Internal Clock Sources

      72
      • FIGURE 5-7: Internal Oscillator Switch Timing

        75
  • 5.3 Clock Switching

    76
    • 5.3.1 System Clock Select (SCS) BitS

      76
    • 5.3.2 Oscillator Start-up Time-out Status (OSTS) Bit

      76
    • 5.3.3 Timer1 Oscillator

      76
    • 5.3.4 Timer1 Oscillator Ready (T1OSCR) Bit

      76
  • 5.4 Two-Speed Clock Start-up Mode

    77
    • 5.4.1 Two-Speed Start-up Mode Configuration

      77
      • TABLE 5-1: Oscillator Switching Delays

        77
    • 5.4.2 Two-speed Start-up Sequence

      78
    • 5.4.3 Checking Two-Speed Clock Status

      78
      • FIGURE 5-8: Two-Speed Start-up

        78
  • 5.5 Fail-Safe Clock Monitor

    79
    • FIGURE 5-9: FSCM Block Diagram

      79
    • 5.5.1 Fail-Safe Detection

      79
    • 5.5.2 Fail-Safe Operation

      79
    • 5.5.3 Fail-Safe Condition Clearing

      79
    • 5.5.4 Reset or Wake-up from Sleep

      79
      • FIGURE 5-10: FSCM Timing Diagram

        80
  • 5.6 Oscillator Control Registers

    81
    • Register 5-1: OSCCON: Oscillator Control Register

      81
    • Register 5-2: OSCSTAT: Oscillator Status Register

      82
    • Register 5-3: OSCTUNE: Oscillator Tuning Register

      83
    • TABLE 5-2: Summary of Registers Associated with Clock Sources

      83
    • TABLE 5-3: Summary of cONFIGURATION wORD with Clock Sources

      83
• 6.0 Resets

  85
  • FIGURE 6-1: Simplified Block Diagram Of On-Chip Reset Circuit

    85
  • 6.1 Power-on Reset (POR)

    86
    • 6.1.1 Power-up Timer (PWRT)

      86
  • 6.2 Brown-Out Reset (BOR)

    86
    • TABLE 6-1: BOR Operating Modes

      86
    • 6.2.1 BOR is Always On

      86
    • 6.2.2 BOR is Off in Sleep

      86
    • 6.2.3 BOR Controlled by Software

      86
      • FIGURE 6-2: Brown-Out Situations

        87
      • Register 6-1: BORCON: Brown-out Reset Control Register

        87
  • 6.3 MCLR

    88
    • TABLE 6-2: MCLR Configuration

      88
    • 6.3.1 MCLR Enabled

      88
    • 6.3.2 MCLR Disabled

      88
  • 6.4 Watchdog Timer (WDT) Reset

    88
  • 6.5 RESET Instruction

    88
  • 6.6 Stack Overflow/Underflow Reset

    88
  • 6.7 Programming Mode Exit

    88
  • 6.8 Power-Up Timer

    88
  • 6.9 Start-up Sequence

    88
    • FIGURE 6-3: Reset Start-Up Sequence

      89
  • 6.10 Determining the Cause of a Reset

    90
    • TABLE 6-3: Reset Status Bits and Their Significance

      90
    • TABLE 6-4: Reset Condition for Special Registers(2)

      90
  • 6.11 Power Control (PCON) Register

    91
    • Register 6-2: PCON: Power Control Register

      91
    • TABLE 6-5: Summary Of Registers Associated With Resets

      92
• 7.0 Interrupts

  93
  • FIGURE 7-1: Interrupt Logic

    93
  • 7.1 Operation

    94
  • 7.2 Interrupt Latency

    94
    • FIGURE 7-2: Interrupt Latency

      95
    • FIGURE 7-3: INT Pin Interrupt Timing

      96
  • 7.3 Interrupts During Sleep

    97
  • 7.4 INT Pin

    97
  • 7.5 Automatic Context Saving

    97
  • 7.6 Interrupt Control Registers

    98
    • 7.6.1 INTCON Register

      98
      • Register 7-1: INTCON: Interrupt Control Register

        98
    • 7.6.2 PIE1 Register

      99
      • Register 7-2: PIE1: Peripheral Interrupt Enable Register 1

        99
    • 7.6.3 PIE2 Register

      100
      • Register 7-3: PIE2: Peripheral Interrupt Enable Register 2

        100
    • 7.6.4 PIE3 Register

      101
      • Register 7-4: PIE3: Peripheral Interrupt Enable Register 3

        101
    • 7.6.5 PIR1 Register

      102
      • Register 7-5: PIR1: Peripheral Interrupt Request Register 1

        102
    • 7.6.6 PIR2 Register

      103
      • Register 7-6: PIR2: Peripheral Interrupt Request Register 2

        103
    • 7.6.7 PIR3 Register

      104
      • Register 7-7: PIR3: Peripheral Interrupt Request Register 3

        104
      • TABLE 7-1: Summary of Registers Associated with Interrupts

        105
• 8.0 Low Dropout (LDO) Voltage Regulator

  107
  • TABLE 8-1: VCAPEN<1:0> Select Bits

    107
  • TABLE 8-2: Summary of cONFIGURATION wORD with LDO

    107
• 9.0 Power-Down Mode (Sleep)

  109
  • 9.1 Wake-up from Sleep

    109
    • 9.1.1 Wake-up Using Interrupts

      110
      • FIGURE 9-1: Wake-Up From Sleep Through Interrupt

        110
      • TABLE 9-1: Summary of Registers Associated with pOWER-dOWN mODE

        110
• 10.0 Watchdog Timer

  111
  • FIGURE 10-1: Watchdog Timer Block Diagram

    111
  • 10.1 Independent Clock Source

    112
  • 10.2 WDT Operating Modes

    112
    • 10.2.1 WDT Is Always On

      112
    • 10.2.2 WDT Is Off In Sleep

      112
    • 10.2.3 WDT Controlled By Software

      112
      • TABLE 10-1: WDT Operating Modes

        112
  • 10.3 Time-Out Period

    112
  • 10.4 Clearing the WDT

    112
  • 10.5 Operation During Sleep

    112
    • TABLE 10-2: WDT Clearing Conditions

      112
  • 10.6 Watchdog Control Register

    113
    • Register 10-1: WDTCON: Watchdog Timer Control Register

      113
    • TABLE 10-3: Summary of Registers Associated with Watchdog Timer

      114
    • TABLE 10-4: Summary of cONFIGURATION wORD with Watchdog Timer

      114
• 11.0 Data EEPROM and Flash Program Memory Control

  115
  • 11.1 EEADRL and EEADRH Registers

    115
    • 11.1.1 EECON1 and EECON2 Registers

      115
  • 11.2 Using the Data EEPROM

    116
    • 11.2.1 Reading the Data EEPROM Memory

      116
      • EXAMPLE 11-1: Data EEPROM Read

        116
    • 11.2.2 Writing to the Data EEPROM Memory

      116
    • 11.2.3 Protection Against Spurious Write

      116
    • 11.2.4 Data EEPROM Operation During Code-Protect

      116
      • EXAMPLE 11-2: Data EEPROM Write

        117
      • FIGURE 11-1: Flash Program Memory Read Cycle Execution

        117
  • 11.3 Flash Program Memory Overview

    118
    • TABLE 11-1: Flash Memory Organization By Device

      118
    • 11.3.1 Reading the Flash Program Memory

      118
      • EXAMPLE 11-3: FLASH PROGRAM MEMORY Read

        119
    • 11.3.2 Erasing Flash Program Memory

      120
    • 11.3.3 Writing to Flash Program Memory

      120
      • FIGURE 11-2: Block WRITES to Flash Program Memory With 8 write latches

        121
      • EXAMPLE 11-4: Erasing One Row of Program Memory -

        122
      • EXAMPLE 11-5: Writing to Flash Program Memory

        123
  • 11.4 Modifying Flash Program Memory

    124
  • 11.5 User ID, Device ID and Configuration Word Access

    124
    • TABLE 11-2: User ID, Device ID and Configuration Word Access (cfgs = 1)

      124
  • 11.6 Write Verify

    125
    • EXAMPLE 11-6: EEPROM Write Verify

      125
    • Register 11-1: EEDATL: EEPROM Data Low Byte Register

      126
    • Register 11-2: EEDATH: EEPROM Data hIGH bYTE Register

      126
    • Register 11-3: EEADRL: EEPROM Address Low Byte Register

      126
    • Register 11-4: EEADRH: EEPROM Address hIGH bYTE Register

      126
    • Register 11-5: EECON1: EEPROM Control 1 Register

      127
    • Register 11-6: EECON2: EEPROM Control 2 Register

      128
    • TABLE 11-3: Summary of Registers Associated with Data EEPROM

      128
• 12.0 I/O Ports

  129
  • TABLE 12-1: Port Availability Per Device

    129
  • FIGURE 12-1: Generic I/O Port Operation

    129
  • EXAMPLE 12-1: Initializing PORTA

    129
  • 12.1 Alternate Pin Function

    130
    • Register 12-1: APFCON: Alternate Pin Function Control Register

      131
  • 12.2 PORTA Registers

    132
    • 12.2.1 ANSELA Register

      132
    • 12.2.2 PORTA Functions and Output Priorities

      132
      • TABLE 12-2: PORTA Output Priority

        132
      • Register 12-2: PORTA: PORTA Register

        133
      • Register 12-3: TRISA: PORTA Tri-State Register

        133
      • Register 12-4: LATA: PORTA Data Latch Register

        133
      • Register 12-5: ANSELA: PORTA Analog Select Register

        134
      • TABLE 12-3: Summary of Registers Associated with PORTA

        135
      • TABLE 12-4: Summary of cONFIGURATION wORD with PORTA

        135
  • 12.3 PORTB Registers

    136
    • 12.3.1 Weak Pull-Ups

      136
    • 12.3.2 Interrupt-on-Change

      136
    • 12.3.3 ANSELB Register

      136
    • 12.3.4 PORTB Functions and Output Priorities

      137
      • TABLE 12-5: PORTB Output Priority

        137
      • Register 12-6: PORTB: PORTB Register

        138
      • Register 12-7: TRISB: PORTB Tri-State Register

        138
      • Register 12-8: LATB: PORTB Data Latch Register

        138
      • Register 12-9: ANSELB: PORTB Analog Select Register

        139
      • Register 12-10: WPUB: WEAK PULL-uP PORTB REGISTER

        139
      • TABLE 12-6: Summary of Registers Associated with PORTB

        140
  • 12.4 PORTC Registers

    141
    • 12.4.1 PORTC Functions and Output Priorities

      141
      • TABLE 12-7: PORTC Output Priority

        141
      • Register 12-11: PORTC: PORTC Register

        142
      • Register 12-12: TRISC: PORTC Tri-State Register

        142
      • Register 12-13: LATC: PORTC Data Latch Register

        142
      • TABLE 12-8: Summary of Registers Associated with PORTC

        143
  • 12.5 PORTD Registers

    144
    • 12.5.1 ANSELD Register

      144
    • 12.5.2 PORTD Functions and Output Priorities

      144
      • TABLE 12-9: PORTD Output Priority

        144
      • Register 12-14: PORTD: PORTD Register(1)

        145
      • Register 12-15: TRISD: PORTD Tri-State Register(1)

        145
      • Register 12-16: LATD: PORTD Data Latch Register

        145
      • Register 12-17: ANSELD: PORTD Analog Select Register(2)

        146
      • TABLE 12-10: Summary of Registers Associated with PORTD(1)

        146
  • 12.6 PORTE Registers

    147
    • 12.6.1 ANSELE Register

      147
    • 12.6.2 PORTE Functions and Output Priorities

      147
      • TABLE 12-11: PORTE Output Priority

        147
      • Register 12-18: PORTE: PORTE Register

        148
      • Register 12-19: TRISE: PORTE Tri-State Register

        148
      • Register 12-20: LATE: PORTE Data Latch Register

        149
      • Register 12-21: ANSELE: PORTE Analog Select Register

        149
      • Register 12-22: WPUE: WEAK PULL-uP PORTe REGISTER

        150
      • TABLE 12-12: Summary of Registers Associated with PORTE

        150
• 13.0 Interrupt-On-Change

  151
  • 13.1 Enabling the Module

    151
  • 13.2 Individual Pin Configuration

    151
  • 13.3 Interrupt Flags

    151
  • 13.4 Clearing Interrupt Flags

    151
    • EXAMPLE 13-1:

      151
  • 13.5 Operation in Sleep

    151
    • FIGURE 13-1: Interrupt-On-Change Block Diagram

      151
  • 13.6 Interrupt-On-Change Registers

    152
    • Register 13-1: IOCBP: Interrupt-on-Change Positive Edge Register

      152
    • Register 13-2: IOCBN: Interrupt-on-Change Negative Edge Register

      152
    • Register 13-3: IOCBF: Interrupt-on-Change Flag Register

      152
    • TABLE 13-1: Summary of Registers Associated with Interrupt-on-Change

      153
• 14.0 Fixed Voltage Reference (FVR)

  155
  • 14.1 Independent Gain Amplifiers

    155
  • 14.2 FVR Stabilization Period

    155
    • FIGURE 14-1: Voltage Reference Block Diagram

      155
  • 14.3 FVR Control Registers

    156
    • Register 14-1: FVRCON: Fixed Voltage Reference Control Register

      156
    • TABLE 14-1: Summary of Registers Associated with Fixed Voltage Reference

      156
• 15.0 Analog-to-Digital Converter (ADC) Module

  157
  • FIGURE 15-1: ADC Block Diagram

    157
  • 15.1 ADC Configuration

    158
    • 15.1.1 Port Configuration

      158
    • 15.1.2 Channel Selection

      158
    • 15.1.3 ADC Voltage Reference

      158
    • 15.1.4 Conversion Clock

      158
      • TABLE 15-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies

        159
      • FIGURE 15-2: Analog-to-Digital Conversion Tad Cycles

        159
    • 15.1.5 Interrupts

      160
    • 15.1.6 Result Formatting

      160
      • FIGURE 15-3: 10-Bit A/D Conversion Result Format

        160
  • 15.2 ADC Operation

    161
    • 15.2.1 Starting a Conversion

      161
    • 15.2.2 Completion of a Conversion

      161
    • 15.2.3 Terminating a conversion

      161
    • 15.2.4 ADC Operation During Sleep

      161
    • 15.2.5 Special Event Trigger

      161
      • TABLE 15-2: Special Event Trigger

        161
    • 15.2.6 A/D Conversion Procedure

      162
      • EXAMPLE 15-1: A/D Conversion

        162
    • 15.2.7 ADC Register Definitions

      163
      • Register 15-1: ADCON0: A/D Control Register 0

        163
      • Register 15-2: ADCON1: A/D Control Register 1

        164
      • Register 15-3: ADRESH: ADC Result Register High (ADRESH) ADFM = 0

        165
      • Register 15-4: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0

        165
      • Register 15-5: ADRESH: ADC Result Register High (ADRESH) ADFM = 1

        166
      • Register 15-6: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1

        166
  • 15.3 A/D Acquisition Requirements

    167
    • EQUATION 15-1: Acquisition Time Example

      167
    • FIGURE 15-4: Analog Input Model

      168
    • FIGURE 15-5: ADC Transfer Function

      168
    • TABLE 15-3: Summary of Registers Associated with ADC

      169
• 16.0 Temperature Indicator Module

  171
  • 16.1 Circuit Operation

    171
    • EQUATION 16-1: Vout Ranges

      171
    • FIGURE 16-1: Temperature Circuit Diagram

      171
  • 16.2 Minimum Operating Vdd vs. Minimum Sensing Temperature

    171
    • TABLE 16-1: Recommended Vdd vs. Range

      171
  • 16.3 Temperature Output

    171
  • 16.4 ADC Acquisition Time

    171
• 17.0 Digital-to-Analog Converter (DAC) Module

  173
  • 17.1 Output Voltage Selection

    173
    • EQUATION 17-1: DAC Output Voltage

      173
  • 17.2 Ratiometric Output Level

    173
  • 17.3 DAC Voltage Reference Output

    173
    • FIGURE 17-1: Digital-to-Analog Converter Block Diagram

      174
    • FIGURE 17-2: Voltage Reference Output Buffer Example

      174
  • 17.4 Low-Power Voltage State

    175
    • 17.4.1 Output Clamped to Positive Voltage Source

      175
    • 17.4.2 Output Clamped to Negative Voltage Source

      175
      • FIGURE 17-3: Output Voltage Clamping Examples

        175
  • 17.5 Operation During Sleep

    175
  • 17.6 Effects of a Reset

    175
    • Register 17-1: DACCON0: Voltage Reference Control Register 0

      176
    • Register 17-2: DACCON1: Voltage Reference Control Register 1

      176
    • TABLE 17-1: Summary of Registers Associated with the DAC Module

      176
• 18.0 Comparator Module

  177
  • 18.1 Comparator Overview

    177
    • FIGURE 18-1: Single Comparator

      177
    • FIGURE 18-2: Comparator Module Simplified Block Diagram

      178
  • 18.2 Comparator Control

    179
    • 18.2.1 Comparator Enable

      179
    • 18.2.2 Comparator Output Selection

      179
    • 18.2.3 Comparator Output Polarity

      179
      • TABLE 18-1: Comparator Output State vs. Input Conditions

        179
    • 18.2.4 Comparator Speed/Power Selection

      179
  • 18.3 Comparator Hysteresis

    180
  • 18.4 Timer1 Gate Operation

    180
    • 18.4.1 Comparator Output Synchronization

      180
  • 18.5 Comparator Interrupt

    180
  • 18.6 Comparator Positive Input Selection

    180
  • 18.7 Comparator Negative Input Selection

    181
  • 18.8 Comparator Response Time

    181
  • 18.9 Interaction with ECCP Logic

    181
  • 18.10 Analog Input Connection Considerations

    181
    • FIGURE 18-3: Analog Input Model

      182
    • Register 18-1: CMxCON0: Comparator X Control Register 0

      183
    • Register 18-2: CMxCON1: Comparator Cx Control Register 1

      184
    • Register 18-3: CMOUT: Comparator Output Register

      184
    • TABLE 18-2: Summary of Registers Associated with Comparator Module

      185
• 19.0 SR Latch

  187
  • 19.1 Latch Operation

    187
  • 19.2 Latch Output

    187
  • 19.3 Effects of a Reset

    187
    • FIGURE 19-1: SR Latch Simplified Block Diagram

      188
    • TABLE 19-1: SRCLK Frequency table

      189
    • Register 19-1: SRCON0: SR Latch Control 0 Register

      189
    • Register 19-2: SRCON1: SR Latch Control 1 Register

      190
    • TABLE 19-2: Summary of Registers Associated with SR Latch Module

      190
• 20.0 Timer0 Module

  191
  • 20.1 Timer0 Operation

    191
    • 20.1.1 8-bit Timer mode

      191
    • 20.1.2 8-Bit Counter Mode

      191
      • FIGURE 20-1: Block Diagram of the Timer0

        191
    • 20.1.3 Software Programmable Prescaler

      192
    • 20.1.4 Timer0 Interrupt

      192
    • 20.1.5 8-BIT COUNTER MODE SYNCHRONIZATION

      192
    • 20.1.6 Operation During Sleep

      192
  • 20.2 Option and Timer0 Control Register

    193
    • Register 20-1: OPTION_REG: OPTION Register

      193
    • TABLE 20-1: Summary of Registers Associated with Timer0

      193
• 21.0 Timer1 Module with Gate Control

  195
  • FIGURE 21-1: Timer1 Block Diagram

    195
  • 21.1 Timer1 Operation

    196
    • TABLE 21-1: Timer1 Enable Selections

      196
  • 21.2 Clock Source Selection

    196
    • 21.2.1 Internal Clock Source

      196
    • 21.2.2 External Clock Source

      196
      • TABLE 21-2: Clock Source Selections

        196
  • 21.3 Timer1 Prescaler

    197
  • 21.4 Timer1 Oscillator

    197
  • 21.5 Timer1 Operation in Asynchronous Counter Mode

    197
    • 21.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode

      197
  • 21.6 Timer1 Gate

    197
    • 21.6.1 Timer1 Gate Enable

      197
      • TABLE 21-3: Timer1 Gate Enable Selections

        197
    • 21.6.2 Timer1 Gate Source Selection

      198
      • TABLE 21-4: Timer1 Gate Sources

        198
    • 21.6.3 Timer1 Gate Toggle Mode

      198
    • 21.6.4 Timer1 Gate Single-Pulse Mode

      198
    • 21.6.5 Timer1 Gate Value Status

      198
    • 21.6.6 Timer1 Gate Event Interrupt

      198
  • 21.7 Timer1 Interrupt

    199
  • 21.8 Timer1 Operation During Sleep

    199
  • 21.9 ECCP/CCP Capture/Compare Time Base

    199
  • 21.10 ECCP/CCP Special Event Trigger

    199
    • FIGURE 21-2: Timer1 Incrementing Edge

      199
    • FIGURE 21-3: Timer1 Gate Enable Mode

      200
    • FIGURE 21-4: Timer1 Gate Toggle Mode

      200
    • FIGURE 21-5: Timer1 Gate Single-Pulse Mode

      201
    • FIGURE 21-6: Timer1 Gate Single-Pulse and Toggle Combined Mode

      202
  • 21.11 Timer1 Control Register

    203
    • Register 21-1: T1CON: Timer1 Control Register

      203
  • 21.12 Timer1 Gate Control Register

    204
    • Register 21-2: T1GCON: Timer1 Gate Control Register

      204
    • TABLE 21-5: Summary of Registers Associated with Timer1

      205
• 22.0 Timer2/4/6 Modules

  207
  • FIGURE 22-1: Timer2/4/6 Block Diagram

    207
  • 22.1 Timer2/4/6 Operation

    208
  • 22.2 Timer2/4/6 Interrupt

    208
  • 22.3 Timer2/4/6 Output

    208
  • 22.4 Timer2/4/6 Operation During Sleep

    208
  • 22.5 Timer2/4/6 Control Register

    209
    • Register 22-1: TxCON: Timer2/timer4/timer6 Control Register

      209
    • TABLE 22-1: Summary of Registers Associated With Timer2/4/6

      210
• 23.0 Capture/Compare/PWM Modules

  211
  • TABLE 23-1: PWM Resources

    211
  • 23.1 Capture Mode

    212
    • 23.1.1 CCP pin Configuration

      212
      • FIGURE 23-1: Capture Mode Operation Block Diagram

        212
    • 23.1.2 Timer1 Mode Resource

      212
    • 23.1.3 Software Interrupt Mode

      212
    • 23.1.4 CCP Prescaler

      212
      • EXAMPLE 23-1: Changing Between Capture Prescalers

        212
    • 23.1.5 Capture During Sleep

      212
    • 23.1.6 Alternate Pin Locations

      213
      • TABLE 23-2: Summary of Registers Associated with Capture

        213
  • 23.2 Compare Mode

    214
    • FIGURE 23-2: Compare Mode Operation Block Diagram

      214
    • 23.2.1 CCP Pin Configuration

      214
    • 23.2.2 timer1 Mode Resource

      214
    • 23.2.3 Software Interrupt Mode

      214
    • 23.2.4 Special Event Trigger

      214
      • TABLE 23-3: Special Event Trigger

        214
    • 23.2.5 Compare During Sleep

      215
    • 23.2.6 Alternate Pin Locations

      215
      • TABLE 23-4: Summary of Registers Associated with cOMPARE

        215
  • 23.3 PWM Overview

    216
    • 23.3.1 Standard PWM Operation

      216
      • FIGURE 23-3: CCP PWM Output Signal

        216
      • FIGURE 23-4: Simplified PWM Block Diagram

        216
    • 23.3.2 Setup for PWM Operation

      217
    • 23.3.3 Timer2/4/6 Timer Resource

      217
    • 23.3.4 PWM period

      217
      • EQUATION 23-1: PWM Period

        217
    • 23.3.5 PWM Duty Cycle

      217
      • EQUATION 23-2: Pulse Width

        217
      • EQUATION 23-3: Duty Cycle Ratio

        217
    • 23.3.6 PWM Resolution

      218
      • EQUATION 23-4: PWM Resolution

        218
      • TABLE 23-5: Example PWM Frequencies and Resolutions (Fosc = 32 MHz)

        218
      • TABLE 23-6: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)

        218
      • TABLE 23-7: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)

        218
    • 23.3.7 Operation in Sleep Mode

      219
    • 23.3.8 Changes in System Clock Frequency

      219
    • 23.3.9 Effects of Reset

      219
    • 23.3.10 Alternate Pin Locations

      219
      • TABLE 23-8: Summary of Registers Associated with Standard PWM

        219
  • 23.4 PWM (Enhanced Mode)

    220
    • FIGURE 23-5: Example Simplified Block Diagram of the Enhanced PWM Mode

      220
    • TABLE 23-9: Example Pin Assignments for Various PWM Enhanced Modes

      221
    • FIGURE 23-6: Example PWM (enhanced Mode) Output Relationships (Active-High State)

      221
    • FIGURE 23-7: Example Enhanced PWM Output Relationships (Active-Low State)

      222
    • 23.4.1 Half-Bridge Mode

      223
      • FIGURE 23-8: Example of Half-Bridge PWM Output

        223
      • FIGURE 23-9: Example of Half-Bridge Applications

        223
    • 23.4.2 Full-Bridge Mode

      224
      • FIGURE 23-10: Example of Full-Bridge Application

        224
      • FIGURE 23-11: Example of Full-Bridge PWM Output

        225
      • FIGURE 23-12: Example of PWM Direction Change

        226
      • FIGURE 23-13: Example of PWM Direction Change at Near 100% Duty Cycle

        227
    • 23.4.3 Enhanced PWM Auto-shutdown mode

      228
      • FIGURE 23-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)

        228
    • 23.4.4 Auto-Restart Mode

      229
      • FIGURE 23-15: PWM Auto-shutdown With Auto-Restart (PxRSEN = 1)

        229
    • 23.4.5 Programmable Dead-Band Delay Mode

      230
      • FIGURE 23-16: Example of Half-Bridge PWM Output

        230
      • FIGURE 23-17: Example of Half-Bridge Applications

        230
    • 23.4.6 PWM Steering Mode

      231
      • FIGURE 23-18: Simplified Steering Block Diagram

        231
    • 23.4.7 Start-up Considerations

      232
      • FIGURE 23-19: Example of Steering Event at End of Instruction (STRxSYNC = 0)

        232
      • FIGURE 23-20: Example of Steering Event at Beginning of Instruction (STRxSYNC = 1)

        232
      • TABLE 23-10: Summary of Registers Associated with Enhanced PWM

        233
  • 23.5 CCP Control Register

    234
    • Register 23-1: CCPXCON: CCPx Control Register

      234
    • Register 23-2: CCPTMRS0: PWM Timer Selection Control Register 0

      235
    • Register 23-3: CCPTMRS1: PWM Timer Selection Control Register 1

      235
    • Register 23-4: CCPxAS: CCPx Auto-Shutdown Control Register

      236
    • Register 23-5: PWMxCON: Enhanced PWM Control Register

      237
    • Register 23-6: PSTRxCON: PWM Steering Control Register(1)

      238
• 24.0 Master Synchronous Serial Port Module

  239
  • 24.1 Master SSP (MSSP) Module Overview

    239
    • FIGURE 24-1: MSSP Block Diagram (SPI mode)

      239
    • FIGURE 24-2: MSSP Block Diagram (I2C™ Master mode)

      240
    • FIGURE 24-3: MSSP Block Diagram (I2C™ Slave mode)

      241
  • 24.2 SPI Mode Overview

    242
    • FIGURE 24-4: SPI Master and Multiple Slave Connection

      243
    • 24.2.1 SPI Mode ReGISTERS

      243
    • 24.2.2 spi mODE oPERATION

      244
      • FIGURE 24-5: SPI Master/Slave Connection

        244
    • 24.2.3 SPI Master Mode

      245
      • FIGURE 24-6: SPI Mode Waveform (Master Mode)

        245
    • 24.2.4 SPI SLAVE MODE

      246
    • 24.2.5 SLAVE SELECT SYNCHRONIZATION

      246
      • FIGURE 24-7: SPI Daisy-Chain Connection

        247
      • FIGURE 24-8: slave Select Synchronous Waveform

        247
      • FIGURE 24-9: SPI Mode Waveform (Slave Mode With CKE = 0)

        248
      • FIGURE 24-10: SPI Mode Waveform (SLAve Mode With CKE = 1)

        248
    • 24.2.6 SPI OPERATION IN Sleep MODE

      249
      • TABLE 24-1: Summary of Registers Associated with SPI Operation

        249
  • 24.3 I2C Mode Overview

    250
    • FIGURE 24-11: I2C Master/ Slave Connection

      250
    • 24.3.1 CLOCK STRETCHING

      251
    • 24.3.2 ARBITRATION

      251
  • 24.4 I2C™ Mode Operation

    251
    • 24.4.1 Byte Format

      251
    • 24.4.2 Definition of I2C terminology

      251
    • 24.4.3 SDA and SCL PINS

      251
    • 24.4.4 SDA Hold Time

      251
      • TABLE 24-2: I2C Bus terms

        252
    • 24.4.5 Start Condition

      252
    • 24.4.6 STOP condition

      252
    • 24.4.7 Restart condition

      252
    • 24.4.8 START/STOP Condition Interrupt masking

      252
      • FIGURE 24-12: I2C START and STOP Conditions

        253
      • FIGURE 24-13: I2C Restart Condition

        253
    • 24.4.9 Acknowledge Sequence

      254
  • 24.5 I2C Slave Mode Operation

    254
    • 24.5.1 slave mode addresses

      254
    • 24.5.2 Slave Reception

      255
      • FIGURE 24-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)

        256
      • FIGURE 24-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)

        257
      • FIGURE 24-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)

        258
      • FIGURE 24-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)

        259
    • 24.5.3 SLAVE Transmission

      260
      • FIGURE 24-18: I2C Slave, 7-Bit Address, TRANSMISSION (AHEN = 0)

        261
      • FIGURE 24-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1)

        263
    • 24.5.4 Slave mode 10-bit Address Reception

      264
    • 24.5.5 10-bit Addressing With Address Or Data Hold

      264
      • FIGURE 24-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)

        265
      • FIGURE 24-21: I2C Slave, 10-Bit Address, Reception (SeN = 0, AHEN = 1, DHEN = 0)

        266
      • FIGURE 24-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)

        267
    • 24.5.6 Clock Stretching

      268
    • 24.5.7 Clock Synchronization and the CKP bit

      268
      • FIGURE 24-23: Clock Synchronization Timing

        268
    • 24.5.8 General call address support

      269
      • FIGURE 24-24: SLAVE MODE GENERAl call address sequence

        269
    • 24.5.9 SSP Mask Register

      269
  • 24.6 I2C Master Mode

    270
    • 24.6.1 I2C Master Mode Operation

      270
    • 24.6.2 Clock Arbitration

      271
      • FIGURE 24-25: Baud Rate Generator Timing with Clock Arbitration

        271
    • 24.6.3 WCOL Status Flag

      271
    • 24.6.4 I2C Master Mode Start Condition Timing

      272
      • FIGURE 24-26: First Start Bit Timing

        272
    • 24.6.5 I2C Master Mode REPEATED Start Condition Timing

      273
      • FIGURE 24-27: Repeat Start Condition Waveform

        273
    • 24.6.6 I2C Master Mode Transmission

      274
      • FIGURE 24-28: I2C Master Mode Waveform (Reception, 7-Bit Address)

        275
    • 24.6.7 I2C Master Mode Reception

      276
      • FIGURE 24-29: I2C Master Mode Waveform (Reception, 7-Bit Address)

        277
    • 24.6.8 Acknowledge Sequence Timing

      278
    • 24.6.9 Stop Condition Timing

      278
      • FIGURE 24-30: Acknowledge Sequence Waveform

        278
      • FIGURE 24-31: Stop Condition Receive or Transmit Mode

        278
    • 24.6.10 Sleep Operation

      279
    • 24.6.11 Effects of a Reset

      279
    • 24.6.12 Multi-Master Mode

      279
    • 24.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration

      279
      • FIGURE 24-32: Bus Collision Timing for Transmit and Acknowledge

        279
      • FIGURE 24-33: Bus Collision During Start Condition (SDA Only)

        280
      • FIGURE 24-34: Bus Collision During Start Condition (SCL = 0)

        281
      • FIGURE 24-35: BRG Reset Due to Sda Arbitration During Start Condition

        281
      • FIGURE 24-36: Bus Collision During a Repeated Start Condition (Case 1)

        282
      • FIGURE 24-37: Bus Collision During Repeated Start Condition (Case 2)

        282
      • FIGURE 24-38: Bus Collision During a Stop Condition (Case 1)

        283
      • FIGURE 24-39: Bus Collision During a Stop Condition (Case 2)

        283
      • TABLE 24-3: Summary of Registers Associated with I2C™ Operation

        284
  • 24.7 Baud Rate Generator

    285
    • FIGURE 24-40: Baud Rate Generator Block Diagram

      285
    • TABLE 24-4: MSSP Clock Rate w/BRG

      285
    • Register 24-1: SSPSTAT: SSP STATUS Register

      286
    • Register 24-2: SSPCON1: SSP Control Register 1

      287
    • Register 24-3: SSPCON2: SSP Control Register 2

      288
    • Register 24-4: SSPCON3: SSP Control Register 3

      289
    • Register 24-5: SSPMSK: SSP Mask Register

      290
    • Register 24-6: SSPADD: MSSP Address and Baud Rate Register (I2C Mode)

      290
• 25.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

  291
  • FIGURE 25-1: EUSART Transmit Block Diagram

    291
  • FIGURE 25-2: EUSART Receive Block Diagram

    292
  • 25.1 EUSART Asynchronous Mode

    293
    • 25.1.1 EUSART Asynchronous Transmitter

      293
      • FIGURE 25-3: Asynchronous Transmission

        294
      • FIGURE 25-4: Asynchronous Transmission (Back-to-Back)

        294
      • TABLE 25-1: Summary of Registers Associated with Asynchronous Transmission

        295
    • 25.1.2 EUSART Asynchronous Receiver

      296
      • FIGURE 25-5: Asynchronous Reception

        298
      • TABLE 25-2: Summary of Registers Associated with Asynchronous Reception

        299
  • 25.2 Clock Accuracy with Asynchronous Operation

    300
    • Register 25-1: TXSTA: Transmit STATUS AND CONTROL REGISTER

      300
    • Register 25-2: RCSTA: Receive STATUS AND CONTROL REGISTER(1)

      301
    • Register 25-3: BAUDCON: BAUD RATE CONTROL REGISTER

      302
  • 25.3 EUSART Baud Rate Generator (BRG)

    303
    • EXAMPLE 25-1: Calculating Baud Rate Error

      303
    • TABLE 25-3: Baud Rate Formulas

      304
    • TABLE 25-4: Summary of Registers Associated with the bAUD rATE gENERATOR

      304
    • TABLE 25-5: BAUD Rates for Asynchronous Modes

      305
    • 25.3.1 Auto-Baud Detect

      308
      • TABLE 25-6: BRG Counter Clock Rates

        308
      • FIGURE 25-6: Automatic Baud Rate Calibration

        308
    • 25.3.2 Auto-baud Overflow

      309
    • 25.3.3 Auto-Wake-up on Break

      309
      • FIGURE 25-7: Auto-Wake-up bit (WUE) timing during normal operation

        310
      • FIGURE 25-8: Auto-Wake-up bit (WUE) timings during Sleep

        310
    • 25.3.4 BREAK Character Sequence

      311
    • 25.3.5 Receiving a BREAK Character

      311
      • FIGURE 25-9: Send Break Character Sequence

        311
  • 25.4 EUSART Synchronous Mode

    312
    • 25.4.1 Synchronous Master Mode

      312
      • FIGURE 25-10: Synchronous Transmission

        313
      • FIGURE 25-11: Synchronous Transmission (Through TXEN)

        313
      • TABLE 25-7: Summary of Registers Associated with Synchronous Master Transmission

        313
      • FIGURE 25-12: Synchronous Reception (Master Mode, SREN)

        315
      • TABLE 25-8: Summary of Registers Associated with Synchronous Master Reception

        315
    • 25.4.2 Synchronous slave Mode

      316
      • TABLE 25-9: Summary of Registers Associated with Synchronous Slave Transmission

        316
      • TABLE 25-10: Summary of Registers Associated with Synchronous Slave Reception

        317
  • 25.5 EUSART Operation During Sleep

    318
    • 25.5.1 Synchronous Receive During Sleep

      318
    • 25.5.2 Synchronous Transmit During Sleep

      318
• 26.0 Capacitive Sensing (CPS) Module

  319
  • FIGURE 26-1: Capacitive Sensing Block Diagram

    319
  • 26.1 Analog MUX

    320
  • 26.2 Capacitive Sensing Oscillator

    320
  • 26.3 Voltage References

    320
  • 26.4 Power Ranges

    320
    • TABLE 26-1: Power Range Selection

      320
  • 26.5 Timer Resources

    321
  • 26.6 Fixed Time Base

    321
    • 26.6.1 Timer0

      321
    • 26.6.2 Timer1

      321
      • TABLE 26-2: TIMER1 ENABLE FUNCTION

        321
  • 26.7 Software Control

    321
    • 26.7.1 Nominal Frequency (No Capacitive Load)

      321
    • 26.7.2 Reduced Frequency (additional capacitive load)

      321
    • 26.7.3 Frequency threshold

      322
  • 26.8 Operation during Sleep

    322
    • Register 26-1: CPSCON0: Capacitive Sensing Control Register 0

      323
    • Register 26-2: CPSCON1: Capacitive Sensing Control Register 1

      324
    • TABLE 26-3: Summary of Registers Associated with Capacitive Sensing

      325
• 27.0 Liquid Crystal Display (LCD) Driver Module

  327
  • FIGURE 27-1: LCD Driver Module Block Diagram

    327
  • 27.1 LCD Registers

    328
    • TABLE 27-1: LCD Segment and Data Registers

      328
    • Register 27-1: LCDCON: Liquid Crystal Display (LCD) Control Register

      329
    • Register 27-2: LCDPS: LCD Phase Register

      330
    • Register 27-3: LCDREF: LCD Reference Voltage Control Register

      331
    • Register 27-4: LCDCST: LCD Contrast Control Register

      332
    • Register 27-5: LCDSEn: LCD Segment Enable Registers

      333
    • Register 27-6: LCDDATAn: LCD Data Registers

      333
  • 27.2 LCD Clock Source Selection

    334
    • 27.2.1 LCD Prescaler

      334
      • FIGURE 27-2: LCD Clock Generation

        334
  • 27.3 LCD Bias Voltage Generation

    335
    • TABLE 27-2: LCD Bias Voltages

      335
    • FIGURE 27-3: LCD Bias VOltage Generation Block DIagram

      335
  • 27.4 LCD Bias Internal Reference Ladder

    336
    • 27.4.1 Bias Mode Interaction

      336
      • TABLE 27-3: LCD Internal ladder power modes (1/3 Bias)

        336
    • 27.4.2 Power Modes

      336
    • 27.4.3 Automatic power mode switching

      337
      • FIGURE 27-4: LCD Internal Reference Ladder power mode switching Diagram – Type A

        337
      • FIGURE 27-5: LCD Internal Reference Ladder power mode switching Diagram – Type A Waveform (1/2 MUX, 1/2 Bias Drive)

        338
      • FIGURE 27-6: LCD Internal Reference Ladder power mode switching Diagram – Type B Waveform (1/2 MUX, 1/2 Bias Drive)

        339
      • Register 27-7: LCDRL: LCD Reference Ladder Control Registers

        340
    • 27.4.4 Contrast Control

      341
      • FIGURE 27-7: Internal reference and Contrast control Block Diagram

        341
    • 27.4.5 Internal Reference

      341
    • 27.4.6 VLCD<3:1> pins

      341
  • 27.5 LCD Multiplex Types

    342
    • TABLE 27-4: Common Pin Usage

      342
  • 27.6 Segment Enables

    342
  • 27.7 Pixel Control

    342
  • 27.8 LCD Frame Frequency

    342
    • TABLE 27-5: Frame Frequency Formulas

      342
    • TABLE 27-6: Approximate Frame Frequency (in Hz) Using Fosc @ 8 MHz, Timer1 @ 32.768 kHz or LFINTOSC

      342
    • TABLE 27-7: LCD Segment Mapping Worksheet

      343
  • 27.9 LCD Waveform Generation

    344
    • FIGURE 27-8: Type-A/Type-B Waveforms in Static Drive

      344
    • FIGURE 27-9: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive

      345
    • FIGURE 27-10: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive

      346
    • FIGURE 27-11: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive

      347
    • FIGURE 27-12: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive

      348
    • FIGURE 27-13: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive

      349
    • FIGURE 27-14: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive

      350
    • FIGURE 27-15: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive

      351
    • FIGURE 27-16: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive

      352
    • FIGURE 27-17: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive

      353
    • FIGURE 27-18: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive

      354
  • 27.10 LCD Interrupts

    355
    • 27.10.1 LCD Interrupt on Module Shutdown

      355
    • 27.10.2 LCD Frame Interrupts

      355
      • FIGURE 27-19: Waveforms and Interrupt Timing in Quarter-Duty Cycle Drive (Example – Type-B, Non-Static)

        356
  • 27.11 Operation During Sleep

    357
    • TABLE 27-8: LCD Module Status During Sleep

      357
    • FIGURE 27-20: Sleep Entry/Exit when SLPEN = 1

      358
  • 27.12 Configuring the LCD Module

    359
  • 27.13 Disabling the LCD Module

    359
  • 27.14 LCD Current Consumption

    359
    • 27.14.1 oscillator selection

      359
    • 27.14.2 LCD Bias source

      359
    • 27.14.3 capacitance of the LCD segments

      359
      • TABLE 27-9: sUMMARY OF Registers Associated with LCD Operation

        360
• 28.0 In-Circuit Serial Programming™ (ICSP™)

  361
  • 28.1 High-Voltage Programming Entry Mode

    361
    • FIGURE 28-1: Vpp Limiter Example Circuit

      361
  • 28.2 Low-Voltage Programming Entry Mode

    362
  • 28.3 Common Programming Interfaces

    362
    • FIGURE 28-2: ICD RJ-11 Style Connector Interface

      362
    • FIGURE 28-3: PICkit™ Style Connector Interface

      362
    • FIGURE 28-4: Typical connection for ICSP™ programming

      363
• 29.0 Instruction Set Summary

  365
  • 29.1 Read-Modify-Write Operations

    365
    • TABLE 29-1: Opcode Field Descriptions

      365
    • TABLE 29-2: Abbreviation Descriptions

      365
    • FIGURE 29-1: General Format for Instructions

      366
    • TABLE 29-3: PIC16(L)F1934/6/7 Enhanced Instruction Set

      367
    • TABLE 29-3: PIC16(L)F1938/9 Enhanced Instruction Set (Continued)

      368
  • 29.2 Instruction Descriptions

    369
• 30.0 Electrical Specifications

  379
  • Absolute Maximum Ratings(†)

    379
    • FIGURE 30-1: PIC16F1934/36/37 Voltage Frequency Graph, -40°C £ Ta £ +125°C

      380
    • FIGURE 30-2: PIC16LF1934/36/37 Voltage Frequency Graph, -40°C £ Ta £ +125°C

      380
    • FIGURE 30-3: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature

      381
  • 30.1 DC Characteristics: PIC16(L)F1934/6/7-I/E (Industrial, Extended)

    382
    • FIGURE 30-4: POR and POR Rearm with Slow Rising Vdd

      383
  • 30.2 DC Characteristics: PIC16(L)F1934/6/7-I/E (Industrial, Extended)

    384
  • 30.3 DC Characteristics: PIC16(L)F1934/6/7-I/E (Power-Down)

    387
  • 30.4 DC Characteristics: PIC16(L)F1934/6/7-I/E

    389
  • 30.5 Memory Programming Requirements

    391
  • 30.6 Thermal Considerations

    392
  • 30.7 Timing Parameter Symbology

    393
    • FIGURE 30-5: Load Conditions

      393
  • 30.8 AC Characteristics: PIC16(L)F1934/6/7-I/E

    394
    • FIGURE 30-6: Clock Timing

      394
    • TABLE 30-1: Clock Oscillator Timing Requirements

      394
    • TABLE 30-2: Oscillator Parameters

      395
    • TABLE 30-3: PLL Clock Timing Specifications (Vdd = 2.7V to 5.5V)

      395
    • FIGURE 30-7: CLKOUT and I/O Timing

      396
    • TABLE 30-4: CLKOUT and I/O Timing Parameters

      397
    • FIGURE 30-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

      397
    • FIGURE 30-9: Brown-Out Reset Timing and Characteristics

      398
    • TABLE 30-5: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters

      399
    • FIGURE 30-10: Timer0 and Timer1 External Clock Timings

      399
    • TABLE 30-6: Timer0 and Timer1 External Clock Requirements

      400
    • FIGURE 30-11: Capture/Compare/PWM Timings (CCP)

      400
    • TABLE 30-7: Capture/Compare/PWM Requirements (CCP)

      400
    • TABLE 30-8: PIC16(L)F1934/6/7 A/D Converter (ADC) Characteristics:

      401
    • TABLE 30-9: PIC16(L)F1934/6/7 A/D Conversion Requirements

      401
    • FIGURE 30-12: PIC16(L)F1934/6/7 A/D Conversion Timing (Normal Mode)

      402
    • FIGURE 30-13: PIC16(L)F1934/6/7 A/D Conversion Timing (Sleep Mode)

      402
    • TABLE 30-10: Comparator Specifications

      403
    • TABLE 30-11: Digital-to-Analog Converter (DAC) Specifications

      403
    • FIGURE 30-14: USART Synchronous Transmission (Master/Slave) Timing

      403
    • TABLE 30-12: USART Synchronous Transmission Requirements

      404
    • FIGURE 30-15: USART Synchronous Receive (Master/Slave) Timing

      404
    • TABLE 30-13: USART Synchronous Receive Requirements

      404
    • FIGURE 30-16: SPI Master Mode Timing (CKE = 0, SMP = 0)

      405
    • FIGURE 30-17: SPI Master Mode Timing (CKE = 1, SMP = 1)

      405
    • FIGURE 30-18: SPI Slave Mode Timing (CKE = 0)

      406
    • FIGURE 30-19: SPI Slave Mode Timing (CKE = 1)

      406
    • TABLE 30-14: SPI Mode requirements

      407
    • FIGURE 30-20: I2C™ Bus Start/Stop Bits Timing

      407
    • TABLE 30-15: I2C™ Bus Start/Stop Bits Requirements

      408
    • FIGURE 30-21: I2C™ Bus Data Timing

      408
    • TABLE 30-16: I2C™ Bus Data Requirements

      409
    • TABLE 30-17: Cap Sense Oscillator Specifications

      410
    • FIGURE 30-22: Cap Sense Oscillator

      410
• 31.0 DC and AC Characteristics Graphs and Charts

  411
  • FIGURE 31-1: PIC16F1934/6/7 Reset Voltage, BOR = 1.9V

    411
  • FIGURE 31-2: PIC16F1934/6/7 Hysteresis, BOR = 1.9V

    411
  • FIGURE 31-3: PIC16F1934/6/7 reset Voltage, BOR = 2.5V

    412
  • FIGURE 31-4: PIC16F1934/6/7 Hysteresis, BOR = 2.5V

    412
  • FIGURE 31-5: PIC16F1934/6/7 POR release

    413
  • FIGURE 31-6: PIC16F1934/6/7 Comparator Hysteresis, High-Power Mode

    413
  • FIGURE 31-7: PIC16F1934/6/7 Comparator Hysteresis, Low-Power Mode

    414
  • FIGURE 31-8: PIC16F1934/6/7 Comparator Offset, High-Power Mode, Vdd = 5.5V

    414
  • FIGURE 31-9: PIC16F1934/6/7 Comparator Response Time, High-Power Mode

    415
  • FIGURE 31-10: Typical Comparator Response Time Over Temperature, High-Power Mode

    415
  • FIGURE 31-11: Voh vs. Ioh Over Temperature (Vdd = 5.0V)

    416
  • FIGURE 31-12: Vol vs. Iol Over Temperature (Vdd = 5.0V)

    416
  • FIGURE 31-13: Voh vs. Ioh Over Temperature (Vdd = 3.0V)

    416
  • FIGURE 31-14: Vol vs. Iol Over Temperature (Vdd = 3.0V)

    417
  • FIGURE 31-15: Voh vs. Ioh Over Temperature (Vdd = 1.8V)

    417
  • FIGURE 31-16: Vol vs. Iol Over Temperature (Vdd = 1.8V)

    417
  • FIGURE 31-17: PIC16LF1937 HF INTOSC Mode, Fosc = 8 MHz

    418
  • FIGURE 31-18: PIC16F1937 MF INTOSC Mode, Fosc = 500 kHz

    418
  • FIGURE 31-19: PIC16LF1937 HF INTOSC Mode, Fosc = 16 MHz

    418
  • FIGURE 31-20: PIC16F1937 HF INTOSC Mode, Fosc = 16 MHz

    419
  • FIGURE 31-21: PIC16F1937 HF INTOSC Mode, Fosc = 8 MHz

    419
  • FIGURE 31-22: PIC16F1937 LF INTOSC Mode, Fosc = 32 kHz

    419
  • FIGURE 31-23: PIC16LF1937 LF INTOSC Mode, Fosc = 32 kHz

    420
  • FIGURE 31-24: PIC16LF1937 MF INTOSC Mode, Fosc = 500 kHz

    420
  • FIGURE 31-25: PIC16LF1937 LP Oscillator Mode, Fosc = 32 kHz

    420
  • FIGURE 31-26: PIC16F1937 LP Oscillator Mode, Fosc = 32 kHz

    421
  • FIGURE 31-27: PIC16LF1937 HS Oscillator Mode, Fosc = 32 MHz

    421
  • FIGURE 31-28: PIC16F1937 HS Oscillator Mode, Fosc = 32 MHz

    421
  • FIGURE 31-29: PIC16LF1937 EXTRC Mode, Fosc = 4 MHz

    422
  • FIGURE 31-30: PIC16LF1937 XT Oscillator, Fosc = 1 MHz

    422
  • FIGURE 31-31: PIC16F1937 XT Oscillator, Fosc = 1 MHz

    422
  • FIGURE 31-32: PIC16LF1937 XT Oscillator, Fosc = 4 MHz

    423
  • FIGURE 31-33: PIC16F1937 XT Oscillator, Fosc = 4 MHz

    423
  • FIGURE 31-34: PIC16LF1937 EC Oscillator, High-Power Mode, Fosc = 32 MHz

    423
  • FIGURE 31-35: PIC16F1937 EC Oscillator, High-Power Mode, Fosc = 32 MHz

    424
  • FIGURE 31-36: PIC16LF1937 EC Oscillator, Medium-Power Mode, Fosc = 4 MHz

    424
  • FIGURE 31-37: PIC16F1937 EC Oscillator, Medium-Power Mode, Fosc = 4 MHz

    424
  • FIGURE 31-38: PIC16LF1937 EC Oscillator, Low-Power Mode, Fosc = 500 kHz

    425
  • FIGURE 31-39: PIC16F1937 EC Oscillator, low-Power Mode, Fosc = 500 kHz

    425
  • FIGURE 31-40: PIC16F1937 EXTRC Mode, Fosc = 4 MHz

    425
  • FIGURE 31-41: PIC16LF1937 LCD, Low power

    426
  • FIGURE 31-42: PIC16LF1937 LCD, Medium Power

    426
  • FIGURE 31-43: PIC16LF1937 LCD, High Power

    427
  • FIGURE 31-44: PIC16LF1937 A/D Current

    427
  • FIGURE 31-45: PIC16F1937 A/D Current

    427
  • FIGURE 31-46: PIC16LF1937 HF INTOSC

    428
  • FIGURE 31-47: PIC16F1937 HF INTOSC

    428
  • FIGURE 31-48: PIC16LF1937 Comparator 1, High Power

    428
  • FIGURE 31-49: PIC16F1937 Comparator 1, High Power

    429
  • FIGURE 31-50: PIC16LF1937 Comparator 1, Low Power

    429
  • FIGURE 31-51: PIC16F1937 Comparator 1, Low Power

    430
  • FIGURE 31-52: PIC16LF1937 Cap Sense, High Power

    430
  • FIGURE 31-53: PIC16F1937 Cap Sense, High Power

    431
  • FIGURE 31-54: PIC16LF1937 Cap Sense, Medium Power

    431
  • FIGURE 31-55: PIC16F1937 Cap Sense, Medium Power

    431
  • FIGURE 31-56: PIC16LF1937 Comparator 2, High Power

    432
  • FIGURE 31-57: PIC16F1937 Comparator 2, High Power

    432
  • FIGURE 31-58: PIC16LF1937 Comparator 2, low Power

    432
  • FIGURE 31-59: PIC16F1937 Comparator 2, Low Power

    433
  • FIGURE 31-60: PIC16LF1937 Cap Sense, Low Power

    433
  • FIGURE 31-61: PIC16F1937 Cap Sense, Low Power

    433
  • FIGURE 31-62: PIC16LF1937 Timer 1 Oscillator

    434
  • FIGURE 31-63: PIC16F1937 Timer 1 Oscillator

    434
  • FIGURE 31-64: PIC16LF1937 BOR Current

    434
  • FIGURE 31-65: PIC16F1937 BOR Current

    435
  • FIGURE 31-66: PIC16LF1937 FVR_ADC

    435
  • FIGURE 31-67: PIC16F1937 FVR_ADC

    436
  • FIGURE 31-68: PIC16LF1937 WDT

    436
  • FIGURE 31-69: PIC16F1937 WDT

    437
  • FIGURE 31-70: PIC16LF1937 FVR_DAC

    437
  • FIGURE 31-71: PIC16F1937 FVR_DAC

    437
  • FIGURE 31-72: PIC16LF1937 Base Ipd

    438
  • FIGURE 31-73: PIC16F1937 Base Ipd

    438
  • 32.0 Development Support

    439
• 33.0 Packaging Information

  443
  • 33.1 Package Marking Information

    443
  • Package Marking Information (Continued)

    444
  • Package Marking Information (Continued)

    445
  • 33.2 Package Details

    446
• Appendix A: Data Sheet Revision History

  459
  • Revision A (12/2008)

    459
  • Revision B (04/2009)

    459
  • Revision C (10/2009)

    459
  • Revision D (12/2009)

    459
  • Revision E (5/2011)

    459
• Appendix B: Migrating From Other PIC® Devices

  459
  • TABLE B-1: Feature Comparison

    459
• INDEX

  461
  • The Microchip Web Site

    469
  • Customer Change Notification Service

    469
  • Customer Support

    469
  • Reader Response

    470
• Product Identification System

  471
• Worldwide Sales and Service

  472