Data SheetTable of Contents16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Advanced Analog11.0 Device Overview13FIGURE 1-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 Block Diagram14TABLE 1-1: Pinout I/O Descriptions (Continued)152.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers192.1 Basic Connection Requirements192.2 Decoupling Capacitors19FIGURE 2-1: Recommended Minimum Connection202.3 CPU Logic Filter Capacitor Connection (Vcap)202.4 Master Clear (MCLR) Pin20FIGURE 2-2: Example of MCLR Pin Connections202.5 ICSP Pins212.6 External Oscillator Pins21FIGURE 2-3: Suggested Placement of the Oscillator Circuit21TABLE 2-1: Crystal Recommendations21TABLE 2-2: Resonator Recommendations222.7 Oscillator Value Conditions on Device Start-up222.8 Configuration of Analog and Digital Pins During ICSP Operations222.9 Unused I/Os223.0 CPU233.1 Overview233.2 Data Addressing Overview233.3 DSP Engine Overview233.4 Special MCU Features24FIGURE 3-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 CPU Core Block Diagram24FIGURE 3-2: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 Programmer’s Model253.5 CPU Resources263.6 CPU Control Registers27Register 3-1: SR: CPU Status Register (Continued)27Register 3-2: CORCON: Core Control Register293.7 Arithmetic Logic Unit (ALU)303.8 DSP Engine30TABLE 3-1: DSP Instructions Summary30FIGURE 3-3: DSP Engine Block Diagram314.0 Memory Organization354.1 Program Address Space35FIGURE 4-1: Program Memory Map for dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 Devices35FIGURE 4-2: Program Memory Organization364.2 Data Address Space37FIGURE 4-3: Data Memory Map for dsPIC33FJ32GP302/304 Devices with 4 Kb RAM38FIGURE 4-4: Data Memory Map for dsPIC33FJ128GP202/204 and dsPIC33FJ64GP202/ 204 Devices with 8 Kb RAM39FIGURE 4-5: Data Memory Map for dsPIC33FJ128GP802/804 And dsPIC33FJ64GP802/ 804 Devices with 16 Kb RAM404.3 Memory Resources414.4 Special Function Register Maps42TABLE 4-1: CPU Core Registers Map (Continued)42TABLE 4-2: Change Notification Register Map for dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 and dsPIC33FJ32GP30244TABLE 4-3: Change Notification Register Map for dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 and dsPIC33FJ32GP30444TABLE 4-4: Interrupt Controller Register Map45TABLE 4-5: Timer Register Map46TABLE 4-6: Input Capture Register Map46TABLE 4-7: Output Compare Register Map47TABLE 4-8: I2C1 Register Map47TABLE 4-9: UART1 Register Map47TABLE 4-10: UART2 Register Map48TABLE 4-11: SPI1 Register Map48TABLE 4-12: SPI2 Register Map48TABLE 4-13: ADC1 Register Map for dsPIC33FJ64GP202/802, dsPIC33FJ128GP202/802 and dsPIC33FJ32GP30249TABLE 4-14: ADC1 Register Map for dsPIC33FJ64GP204/804, dsPIC33FJ128GP204/804 and dsPIC33FJ32GP30449TABLE 4-15: DAC1 Register Map for dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/80449TABLE 4-16: DMA Register Map (Continued)50TABLE 4-17: ECAN1 Register Map When C1CTRL1.WIN = 0 or 1 (For dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804)52TABLE 4-18: ECAN1 Register Map When C1CTRL1.WIN = 0 (For dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804)52TABLE 4-19: ECAN1 Register Map When C1CTRL1.WIN = 1(For dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804) (Continued)53TABLE 4-20: DCI Register Map54TABLE 4-21: PERIPHERAL pin Select Input Register Map55TABLE 4-22: PERIPHERAL Pin Select Output Register Map for dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 and dsPIC33FJ32GP30256TABLE 4-23: Peripheral Pin Select Output Register Map for dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 and dsPIC33FJ32GP30456TABLE 4-24: Parallel Master/Slave Port Register Map for dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 and dsPIC33FJ32GP30257TABLE 4-25: Parallel Master/Slave Port Register Map for dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 and dsPIC33FJ32GP30457TABLE 4-26: Real-Time Clock and Calendar Register Map58TABLE 4-27: CRC Register Map58TABLE 4-28: Dual Comparator Register Map58TABLE 4-29: PORTA Register Map for dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 and dsPIC33FJ32Gp30258TABLE 4-30: PORTA Register Map for dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 and dsPIC33FJ32GP30459TABLE 4-31: PORTB Register Map59TABLE 4-32: PORTC Register Map for dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 and dsPIC33FJ32GP30459TABLE 4-33: System Control Register Map60TABLE 4-34: Security Register Map(1)60TABLE 4-35: NVM Register Map60TABLE 4-36: PMD Register Map60FIGURE 4-6: CALL Stack Frame614.5 Instruction Addressing Modes61TABLE 4-37: Fundamental Addressing Modes Supported624.6 Modulo Addressing63FIGURE 4-7: Modulo Addressing Operation Example634.7 Bit-Reversed Addressing64FIGURE 4-8: Bit-Reversed Address Example65TABLE 4-38: Bit-Reversed Address Sequence (16-Entry)654.8 Interfacing Program and Data Memory Spaces66TABLE 4-39: Program Space Address Construction66FIGURE 4-9: Data Access from Program Space Address Generation67FIGURE 4-10: Accessing Program Memory with Table Instructions68FIGURE 4-11: Program Space Visibility Operation695.0 Flash Program Memory715.1 Table Instructions and Flash Programming71FIGURE 5-1: Addressing for Table Registers715.2 RTSP Operation725.3 Programming Operations72EQUATION 5-1: Programming Time72EQUATION 5-2: Minimum Row Write Time72EQUATION 5-3: Maximum Row Write Time725.4 Control Registers725.5 Flash Resources725.6 Flash Control Registers73Register 5-1: NVMCON: Flash Memory Control Register73Register 5-2: NVMKEY: NonVolatile Memory Key RegisteR74EXAMPLE 5-1: Erasing a Program Memory Page75EXAMPLE 5-2: Loading the Write Buffers76EXAMPLE 5-3: Initiating a Programming Sequence766.0 Resets77FIGURE 6-1: Reset System Block Diagram776.1 Reset Resources786.2 Reset Control Registers79Register 6-1: RCON: Reset Control Register(1) (Continued)796.3 System Reset81TABLE 6-1: Oscillator Delay81FIGURE 6-2: System Reset Timing82TABLE 6-2: Oscillator Delay836.4 Power-on Reset (POR)836.4.1 Brown-out Reset (BOR) and Power-up timer (PWRT)83FIGURE 6-3: Brown-out Situations846.5 External Reset (EXTR)846.6 Software RESET Instruction (SWR)846.7 Watchdog Time-out Reset (WDTO)846.8 Trap Conflict Reset846.9 Configuration Mismatch Reset856.10 Illegal Condition Device Reset856.11 Using the RCON Status Bits85TABLE 6-3: Reset Flag Bit Operation857.0 Interrupt Controller877.1 Interrupt Vector Table877.2 Reset Sequence87FIGURE 7-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 Interrupt Vector Table88TABLE 7-1: Interrupt Vectors (Continued)897.3 Interrupt Control and Status Registers917.4 Interrupts Resources917.5 CPU Registers92Register 7-1: SR: CPU STATUS Register(1)92Register 7-2: CORCON: CORE Control Register(1)92Register 7-3: INTCON1: Interrupt Control Register 1 (Continued)93Register 7-4: INTCON2: Interrupt Control Register 295Register 7-5: IFS0: Interrupt Flag Status Register 0 (Continued)96Register 7-6: IFS1: Interrupt Flag Status Register 1 (Continued)98Register 7-7: IFS2: Interrupt Flag Status Register 2100Register 7-8: IFS3: Interrupt Flag Status Register 3101Register 7-9: IFS4: Interrupt Flag Status Register 4102Register 7-10: IEC0: Interrupt Enable Control Register 0 (Continued)103Register 7-11: IEC1: Interrupt Enable Control Register 1 (Continued)105Register 7-12: IEC2: Interrupt Enable Control Register 2107Register 7-13: IEC3: Interrupt Enable Control Register 3108Register 7-14: IEC4: Interrupt Enable Control Register 4109Register 7-15: IPC0: Interrupt Priority Control Register 0110Register 7-16: IPC1: Interrupt Priority Control Register 1111Register 7-17: IPC2: Interrupt Priority Control Register 2112Register 7-18: IPC3: Interrupt Priority Control Register 3113Register 7-19: IPC4: Interrupt Priority Control Register 4114Register 7-20: IPC5: Interrupt Priority Control Register 5115Register 7-21: IPC6: Interrupt Priority Control Register 6116Register 7-22: IPC7: Interrupt Priority Control Register 7117Register 7-23: IPC8: Interrupt Priority Control Register 8118Register 7-24: IPC9: Interrupt Priority Control Register 9119Register 7-25: IPC11: Interrupt Priority Control Register 11120Register 7-26: IPC14: Interrupt Priority Control Register 14121Register 7-27: IPC15: Interrupt Priority Control Register 15122Register 7-28: IPC16: Interrupt Priority Control Register 16123Register 7-29: IPC17: Interrupt Priority Control Register 17124Register 7-30: IPC19: Interrupt Priority Control Register 19125Register 7-31: INTTREG: Interrupt Control and Status Register1267.6 Interrupt Setup Procedures1278.0 Direct Memory Access (DMA)129TABLE 8-1: DMA Channel to Peripheral Associations129FIGURE 8-1: Top Level System Architecture Using a Dedicated Transaction Bus1308.1 DMA Resources1318.2 DMAC Registers1318.3 DMA Control Registers132Register 8-1: DMAxCON: DMA Channel x Control Register132Register 8-2: DMAxREQ: DMA Channel x IRQ Select Register133Register 8-3: DMAxSTA: DMA Channel x RAM Start Address Register A(1)134Register 8-4: DMAxSTB: DMA Channel x RAM Start Address Register B(1)134Register 8-5: DMAxPAD: DMA Channel x Peripheral Address Register(1)135Register 8-6: DMAxCNT: DMA Channel x Transfer Count Register(1)135Register 8-7: DMACS0: DMA Controller Status Register 0 (Continued)136Register 8-8: DMACS1: DMA Controller Status Register 1138Register 8-9: DSADR: Most Recent DMA RAM Address1399.0 Oscillator Configuration141FIGURE 9-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 Oscillator System Diagram1419.1 CPU Clocking System142EQUATION 9-1: Device Operating Frequency142EQUATION 9-2: Fosc Calculation143EQUATION 9-3: XT with PLL Mode Example143FIGURE 9-2: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 PLL Block Diagram143TABLE 9-1: Configuration Bit Values for Clock Selection1449.2 Oscillator Resources1449.3 Oscillator Control Registers145Register 9-1: OSCCON: Oscillator Control Register(1,3) (Continued)145Register 9-2: CLKDIV: Clock Divisor Register(2)147Register 9-3: PLLFBD: PLL Feedback Divisor Register(1)148Register 9-4: OSCTUN: FRC Oscillator Tuning Register(2)149Register 9-5: ACLKCON: Auxiliary Control Register(1)1509.4 Clock Switching Operation1519.5 Fail-Safe Clock Monitor (FSCM)15110.0 Power-Saving Features15310.1 Clock Frequency and Clock Switching15310.2 Instruction-Based Power-Saving Modes153EXAMPLE 10-1: PWRSAV Instruction Syntax15310.3 Doze Mode15410.4 Peripheral Module Disable15410.5 Power-Saving Resources15510.6 Power-Saving Control Registers156Register 10-1: PMD1: Peripheral Module Disable Control Register 1156Register 10-2: PMD2: Peripheral Module Disable Control Register 2157Register 10-3: PMD3: Peripheral Module Disable Control Register 315811.0 I/O Ports15911.1 Parallel I/O (PIO) Ports159FIGURE 11-1: Block Diagram of a Typical Shared Port Structure15911.2 Open-Drain Configuration16011.3 Configuring Analog Port Pins16011.4 I/O Port Write/Read Timing16011.5 Input Change Notification160EXAMPLE 11-1: Port Write/Read Example16011.6 Peripheral Pin Select161FIGURE 11-2: Remappable MUX Input for U1RX161TABLE 11-1: Selectable Input Sources (Maps Input to Function)(1)162FIGURE 11-3: Multiplexing of Remappable Output for RPn163TABLE 11-2: Output Selection for Remappable Pin (RPn)16311.7 I/O Helpful Tips16511.8 I/O Resources16511.9 Peripheral Pin Select Registers166Register 11-1: RPINR0: Peripheral Pin Select Input Register 0166Register 11-2: RPINR1: Peripheral Pin Select Input Register 1167Register 11-3: RPINR3: Peripheral Pin Select Input Register 3168Register 11-4: RPINR4: Peripheral Pin Select Input Register 4169Register 11-5: RPINR7: Peripheral Pin Select Input Register 7170Register 11-6: RPINR10: Peripheral Pin Select Input Register 10171Register 11-7: RPINR11: Peripheral Pin Select Input Register 11172Register 11-8: RPINR18: Peripheral Pin Select Input Register 18173Register 11-9: RPINR19: Peripheral Pin Select Input Register 19174Register 11-10: RPINR20: Peripheral Pin Select Input Register 20175Register 11-11: RPINR21: Peripheral Pin Select Input Register 21176Register 11-12: RPINR22: Peripheral Pin Select Input Register 22177Register 11-13: RPINR23: Peripheral Pin Select Input Register 23178Register 11-14: RPINR24: Peripheral Pin Select Input Register 24179Register 11-15: RPINR25: Peripheral Pin Select Input Register 25180Register 11-16: RPINR26: Peripheral Pin Select Input Register 26(1)180Register 11-17: RPOR0: Peripheral Pin Select Output Register 0181Register 11-18: RPOR1: Peripheral Pin Select Output Register 1181Register 11-19: RPOR2: Peripheral Pin Select Output Register 2182Register 11-20: RPOR3: Peripheral Pin Select Output Register 3182Register 11-21: RPOR4: Peripheral Pin Select Output Register 4183Register 11-22: RPOR5: Peripheral Pin Select Output Register 5183Register 11-23: RPOR6: Peripheral Pin Select Output Register 6184Register 11-24: RPOR7: Peripheral Pin Select Output Register 7184Register 11-25: RPOR8: Peripheral Pin Select Output Register 8(1)185Register 11-26: RPOR9: Peripheral Pin Select Output Register 9(1)185Register 11-27: RPOR10: Peripheral Pin Select Output Register 10(1)186Register 11-28: RPOR11: Peripheral Pin Select Output Register 11(1)186Register 11-29: RPOR12: Peripheral Pin Select Output Register 12(1)18712.0 Timer1189TABLE 12-1: Timer Mode Settings189FIGURE 12-1: 16-bit Timer1 Module Block Diagram18912.1 Timer Resources19012.2 Timer1 Control Register191Register 12-1: T1CON: Timer1 Control Register19113.0 Timer2/3 and Timer4/5 Feature193FIGURE 13-1: Type B Timer Block Diagram (x = 2 or 4)193FIGURE 13-2: Type C Timer Block Diagram (X = 3 or 5)193TABLE 13-1: Timer Mode Settings19413.1 16-bit Operation19413.2 32-bit Operation194TABLE 13-2: 32-bit Timer194FIGURE 13-3: 32-bit Timer Block Diagram19513.3 Timer Resources19513.4 Timerx/y Control Registers196Register 13-1: TxCON: Timer Control Register (x = 2 or 4, y = 3 or 5)196Register 13-2: TXCON: Timer Control Register (X = 3 or 5)19714.0 Input Capture199FIGURE 14-1: Input Capture Block Diagram19914.1 Input Capture Resources20014.2 Input Capture Registers201Register 14-1: ICxCON: Input Capture x Control Register (x = 1, 2, 7 or 8)20115.0 Output Compare203FIGURE 15-1: Output Compare Module Block Diagram20315.1 Output Compare Modes204TABLE 15-1: Output Compare Modes204FIGURE 15-2: Output Compare Operation20415.2 Output Compare Resources20515.3 Output Compare Control Register206Register 15-1: OCxCON: Output Compare x Control Register (x = 1, 2, 3 or 4)20616.0 Serial Peripheral Interface (SPI)207FIGURE 16-1: SPI Module Block Diagram20716.1 SPI Helpful Tips20816.2 SPI Resources20816.3 SPI Control Registers209Register 16-1: SPIxSTAT: SPIx Status and Control Register209Register 16-2: SPIxCON1: SPIx Control Register 1 (Continued)210Register 16-3: SPIxCON2: SPIx Control Register 221217.0 Inter-Integrated Circuit™ (I2C™)21317.1 Operating Modes213FIGURE 17-1: I2C™ Block Diagram (x = 1)21417.2 I2C Resources21517.3 I2C Registers215Register 17-1: I2CxCON: I2Cx Control Register (Continued)216Register 17-2: I2CxSTAT: I2Cx Status Register (Continued)218Register 17-3: I2CxMSK: I2Cx Slave Mode Address Mask Register22018.0 Universal Asynchronous Receiver Transmitter (UART)221FIGURE 18-1: UART Simplified Block Diagram22118.1 UART Helpful Tips22218.2 UART Resources22218.3 UART Control Registers223Register 18-1: UxMODE: UARTx Mode Register (Continued)223Register 18-2: UxSTA: UARTx Status and Control Register (Continued)22519.0 Enhanced CAN (ECAN™) Module22719.1 Overview22719.2 Frame Types228FIGURE 19-1: ECAN™ Module Block Diagram22919.3 Modes of Operation23019.4 ECAN Resources23119.5 ECAN Control Registers232Register 19-1: CiCTRL1: ECAN™ Control Register 1232Register 19-2: CiCTRL2: ECAN™ Control Register 2233Register 19-3: CiVEC: ECAN™ Interrupt Code Register234Register 19-4: CiFCTRL: ECAN™ FIFO Control Register235Register 19-5: CiFIFO: ECAN™ FIFO Status Register236Register 19-6: CiINTF: ECAN™ Interrupt Flag Register237Register 19-7: CiINTE: ECAN™ Interrupt Enable Register238Register 19-8: CiEC: ECAN™ Transmit/Receive Error Count Register239Register 19-9: CiCFG1: ECAN™ Baud Rate Configuration Register 1239Register 19-10: CiCFG2: ECAN™ Baud Rate Configuration Register 2240Register 19-11: CiFEN1: ECAN™ Acceptance Filter Enable Register241Register 19-12: CiBUFPNT1: ECAN™ Filter 0-3 Buffer Pointer Register241Register 19-13: CiBUFPNT2: ECAN™ Filter 4-7 Buffer Pointer Register242Register 19-14: CiBUFPNT3: ECAN™ Filter 8-11 Buffer Pointer Register242Register 19-15: CiBUFPNT4: ECAN™ Filter 12-15 Buffer Pointer Register243Register 19-16: CiRXFnSID: ECAN™ Acceptance Filter Standard Identifier Register n (n = 0-15)244Register 19-17: CiRXFnEID: ECAN™ Acceptance Filter Extended Identifier Register n (n = 0-15)245Register 19-18: CiFMSKSEL1: ECAN™ Filter 7-0 Mask Selection Register245Register 19-19: CiFMSKSEL2: ECAN™ Filter 15-8 Mask Selection Register246Register 19-20: CiRXMnSID: ECAN™ Acceptance Filter Mask Standard Identifier Register n (n = 0-2)247Register 19-21: CiRXMnEID: ECAN™ Acceptance Filter Mask Extended Identifier Register n (n = 0-2)247Register 19-22: CiRXFUL1: ECAN™ Receive Buffer Full Register 1248Register 19-23: CiRXFUL2: ECAN™ Receive Buffer Full Register 2248Register 19-24: CiRXOVF1: ECAN™ Receive Buffer Overflow Register 1249Register 19-25: CiRXOVF2: ECAN™ Receive Buffer Overflow Register 2249Register 19-26: CiTRmnCON: ECAN™ TX/RX Buffer m Control Register (m = 0,2,4,6; n = 1,3,5,7)25019.6 ECAN Message Buffers25120.0 Data Converter Interface (DCI) Module25520.1 Module Introduction255FIGURE 20-1: DCI Module Block Diagram25520.2 DCI Resources25620.3 DCI Control Registers257Register 20-1: DCICON1: DCI Control Register 1257Register 20-2: DCICON2: DCI Control Register 2258Register 20-3: DCICON3: DCI Control Register 3259Register 20-4: DCISTAT: DCI Status Register260Register 20-5: RSCON: DCI Receive Slot Control Register261Register 20-6: TSCON: DCI Transmit Slot Control Register26121.0 10-bit/12-bit Analog-to- Digital Converter (ADC)26321.1 Key Features26321.2 ADC Initialization26321.3 ADC and DMA263FIGURE 21-1: ADC1 Module Block Diagram for dsPIC33FJ32GP304, dsPIC33FJ64GP204/804 and dsPIC33FJ128GP204/804 Devices264FIGURE 21-2: ADC1 Module Block Diagram for dsPIC33FJ32GP302, dsPIC33FJ64GP202/802 and dsPIC33FJ128GP202/802 Devices265FIGURE 21-3: ADC Conversion Clock Period Block Diagram26621.4 ADC Helpful Tips26721.5 ADC Resources26721.6 ADC Control Registers268Register 21-1: AD1CON1: ADC1 Control Register 1 (Continued)268Register 21-2: AD1CON2: ADC1 Control Register 2270Register 21-3: AD1CON3: ADC1 Control Register 3271Register 21-4: AD1CON4: ADC1 Control Register 4272Register 21-5: AD1CHS123: ADC1 Input Channel 1, 2, 3 Select Register273Register 21-6: AD1CHS0: ADC1 Input Channel 0 Select Register274Register 21-7: AD1CSSL: ADC1 Input Scan Select Register Low(1,2)275Register 21-8: AD1PCFGL: ADC1 Port Configuration Register Low(1,2,3)27522.0 Audio Digital-to-Analog Converter (DAC)27722.1 Key Features27722.2 DAC Module Operation27722.3 DAC Output Format27722.4 DAC Clock278FIGURE 22-1: Block Diagram of Audio Digital-to-Analog (DAC) Converter278FIGURE 22-2: Audio DAC Output for Ramp Input (Unsigned)27822.5 DAC Resources27922.6 DAC Control Registers280Register 22-1: DAC1CON: DAC Control Register280Register 22-2: DAC1STAT: DAC Status Register281Register 22-3: DAC1DFLT: DAC Default Data Register282Register 22-4: DAC1LDAT: DAC Left Data Register282Register 22-5: DAC1RDAT: DAC Right Data Register28223.0 Comparator Module283FIGURE 23-1: Comparator I/O Operating Modes28323.1 Comparator Resources28423.2 Comparator Control Register285Register 23-1: CMCON: Comparator Control Register (Continued)28523.3 Comparator Voltage Reference287FIGURE 23-2: Comparator Voltage Reference Block Diagram287Register 23-2: CVRCON: Comparator Voltage Reference Control Register28824.0 Real-Time Clock and Calendar (RTCC)289FIGURE 24-1: RTCC Block Diagram28924.1 RTCC Module Registers290TABLE 24-1: RTCVAL Register Mapping290TABLE 24-2: ALRMVAL Register Mapping290EXAMPLE 24-1: Setting the RTCWREN Bit29024.2 RTCC Resources29124.3 RTCC Registers292Register 24-1: RCFGCAL: RTCC Calibration and Configuration RegistER(1) (Continued)292Register 24-2: PADCFG1: Pad Configuration Control Register294Register 24-3: ALCFGRPT: Alarm Configuration Register295Register 24-4: RTCVAL (When RTCPTR<1:0> = 11): Year Value Register(1)296Register 24-5: RTCVAL (When RTCPTR<1:0> = 10): Month and Day Value Register(1)296Register 24-6: RTCVAL (When RTCPTR<1:0> = 01): WKDYHR: Weekday and Hours Value Register(1)297Register 24-7: RTCVAL (When RTCPTR<1:0> = 00): Minutes and SEconds Value Register297Register 24-8: ALRMVAL (When ALRMPTR<1:0> = 10): Alarm Month and Day Value Register(1)298Register 24-9: ALRMVAL (When ALRMPTR<1:0> = 01): Alarm Weekday and Hours Value Register(1)298Register 24-10: ALRMVAL (When ALRMPTR<1:0> = 00): Alarm Minutes and Seconds Value Register29925.0 Programmable Cyclic Redundancy Check (CRC) Generator30125.1 Overview301EQUATION 25-1: CRC equation301TABLE 25-1: Example CRC Setup301FIGURE 25-1: CRC Shifter Details301FIGURE 25-2: CRC Generator Reconfigured for x16 + x12 + x5 + 130225.2 User Interface30225.3 Operation in Power-Saving Modes30225.4 Programmable CRC Resources30325.5 Programmable CRC Registers304Register 25-1: CRCCON: CRC Control Register304Register 25-2: CRCXOR: CRC XOR Polynomial Register30526.0 Parallel Master Port (PMP)307FIGURE 26-1: PMP Module Overview30726.1 PMP Resources30826.2 PMP Control Registers309Register 26-1: PMCON: Parallel Master Port Control Register (Continued)309Register 26-2: PMMODE: Parallel Port Mode Register311Register 26-3: PMADDR: Parallel Port Address Register312Register 26-4: PMAEN: Parallel Port Enable Register312Register 26-5: PMSTAT: Parallel Port Status Register313Register 26-6: PADCFG1: Pad Configuration Control Register31427.0 Special Features31527.1 Configuration Bits315TABLE 27-1: Device Configuration Register Map315TABLE 27-2: dsPIC Configuration Bits Description (Continued)31627.2 On-Chip Voltage Regulator319FIGURE 27-1: Connections for the On-Chip Voltage Regulator(1,2,3)31927.3 BOR: Brown-out Reset31927.4 Watchdog Timer (WDT)320FIGURE 27-2: WDT Block Diagram32027.5 JTAG Interface32127.6 In-Circuit Serial Programming™ (ICSP)™32127.7 In-Circuit Debugger32127.8 Code Protection and CodeGuard™ Security321TABLE 27-3: Code Flash Security Segment Sizes for 32 KB Devices322TABLE 27-4: Code Flash Security Segment Sizes for 64 KB Devices323TABLE 27-5: Code Flash Security Segment Sizes for 128 KB Devices32428.0 Instruction Set Summary325TABLE 28-1: Symbols used in Opcode Descriptions (Continued)326TABLE 28-2: Instruction Set Overview (Continued)32829.0 Development Support33329.1 MPLAB Integrated Development Environment Software33329.2 MPLAB C Compilers for Various Device Families33429.3 HI-TECH C for Various Device Families33429.4 MPASM Assembler33429.5 MPLINK Object Linker/ MPLIB Object Librarian33429.6 MPLAB Assembler, Linker and Librarian for Various Device Families33429.7 MPLAB SIM Software Simulator33529.8 MPLAB REAL ICE In-Circuit Emulator System33529.9 MPLAB ICD 3 In-Circuit Debugger System33529.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express33529.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express33629.12 MPLAB PM3 Device Programmer33629.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits33630.0 Electrical Characteristics33730.1 DC Characteristics338TABLE 30-1: Operating MIPS vs. Voltage338TABLE 30-2: Thermal Operating Conditions338TABLE 30-3: Thermal Packaging Characteristics338TABLE 30-4: DC Temperature and Voltage specifications339TABLE 30-5: DC Characteristics: Operating Current (Idd)340TABLE 30-6: DC Characteristics: Idle Current (Iidle)341TABLE 30-7: DC Characteristics: Power-Down Current (Ipd)342TABLE 30-8: DC Characteristics: Doze Current (Idoze)343TABLE 30-9: DC Characteristics: I/O Pin Input Specifications (Continued)344TABLE 30-10: DC Characteristics: I/O Pin Output Specifications347TABLE 30-11: Electrical Characteristics: BOR348TABLE 30-12: DC Characteristics: Program Memory348TABLE 30-13: Internal Voltage Regulator Specifications34830.2 AC Characteristics and Timing Parameters349TABLE 30-14: Temperature and Voltage Specifications – AC349FIGURE 30-1: Load Conditions for Device Timing Specifications349TABLE 30-15: Capacitive Loading Requirements on Output Pins349FIGURE 30-2: External Clock Timing350TABLE 30-16: External Clock Timing Requirements350TABLE 30-17: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)351TABLE 30-18: AC Characteristics: Internal RC Accuracy351TABLE 30-19: Internal RC accuracy351FIGURE 30-3: CLKO and I/O Timing Characteristics352TABLE 30-20: I/O Timing Requirements352FIGURE 30-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics353TABLE 30-21: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements354FIGURE 30-5: Timer1, 2, 3 and 4 External Clock Timing Characteristics355TABLE 30-22: Timer1 External Clock Timing Requirements(1)355TABLE 30-23: Timer2 and Timer 4 External Clock Timing Requirements356TABLE 30-24: Timer3 and Timer5 External Clock Timing Requirements356FIGURE 30-6: Input Capture (CAPx) Timing Characteristics357TABLE 30-25: Input Capture Timing Requirements357FIGURE 30-7: Output Compare Module (OCx) Timing Characteristics357TABLE 30-26: Output Compare Module Timing Requirements357FIGURE 30-8: OC/PWM Module Timing Characteristics358TABLE 30-27: Simple OC/PWM MODE Timing Requirements358TABLE 30-28: SPIx Maximum Data/CLock Rate Summary359FIGURE 30-9: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 0) TIMING CHARACTERISTICS359FIGURE 30-10: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 1) TIMING CHARACTERISTICS359TABLE 30-29: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements360FIGURE 30-11: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS361TABLE 30-30: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements361FIGURE 30-12: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS362TABLE 30-31: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements362FIGURE 30-13: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS363TABLE 30-32: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements364FIGURE 30-14: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS365TABLE 30-33: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements366FIGURE 30-15: SPIx SLAVE MODE (Full-Duplex CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS367TABLE 30-34: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements368FIGURE 30-16: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS369TABLE 30-35: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements370FIGURE 30-17: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)371FIGURE 30-18: I2Cx Bus Data Timing Characteristics (Master Mode)371TABLE 30-36: I2Cx Bus Data Timing Requirements (Master Mode)372FIGURE 30-19: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)373FIGURE 30-20: I2Cx Bus Data Timing Characteristics (Slave Mode)373TABLE 30-37: I2Cx Bus Data Timing Requirements (Slave Mode)374FIGURE 30-21: DCI Module (Multi-Channel, I2S Modes) Timing Characteristics375TABLE 30-38: DCI Module (Multi-Channel, I2S Modes) Timing Requirements376FIGURE 30-22: DCI Module (AC-Link Mode) Timing Characteristics377TABLE 30-39: DCI Module (AC-Link Mode) Timing Requirements378FIGURE 30-23: ECAN™ Module I/O Timing Characteristics379TABLE 30-40: ECAN™ Module I/O Timing Requirements379TABLE 30-41: ADC Module Specifications380TABLE 30-42: ADC Module Specifications (12-bit Mode)381TABLE 30-43: ADC Module Specifications (10-bit Mode)382FIGURE 30-24: ADC Conversion (12-bit Mode) Timing Characteristics (ASAM = 0, SSRC<2:0> = 000)383TABLE 30-44: ADC Conversion (12-bit Mode) Timing Requirements384FIGURE 30-25: ADC Conversion (10-bit Mode) Timing Characteristics (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)385FIGURE 30-26: ADC Conversion (10-bit Mode) Timing Characteristics (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)385TABLE 30-45: ADC Conversion (10-bit Mode) Timing Requirements386TABLE 30-46: Audio DAC Module Specifications386TABLE 30-47: Comparator Timing Specifications387TABLE 30-48: Comparator Module Specifications387TABLE 30-49: Comparator Reference Voltage Settling Time Specifications387TABLE 30-50: Comparator Reference Voltage Specifications387FIGURE 30-27: Parallel Slave Port Timing Diagram388TABLE 30-51: Parallel Slave Port Time Specifications388FIGURE 30-28: Parallel Master Port Read Timing Diagram389TABLE 30-52: Parallel Master Port Read Timing Requirements389FIGURE 30-29: Parallel Master Port Write Timing Diagram390TABLE 30-53: Parallel Master Port Write Timing Requirements390TABLE 30-54: DMA Read/Write Timing Requirements39031.0 High Temperature Electrical Characteristics39131.1 High Temperature DC Characteristics392TABLE 31-1: Operating MIPS vs. Voltage392TABLE 31-2: Thermal Operating Conditions392TABLE 31-3: DC Temperature and Voltage Specifications392TABLE 31-4: DC Characteristics: Power-down Current (Ipd)393TABLE 31-5: DC Characteristics: Doze Current (Idoze)393TABLE 31-6: DC Characteristics: I/O Pin Output Specifications394TABLE 31-7: DC Characteristics: Program Memory39531.2 AC Characteristics and Timing Parameters396TABLE 31-8: Temperature and Voltage Specifications – AC396FIGURE 31-1: Load Conditions for Device Timing Specifications396TABLE 31-9: PLL Clock Timing Specifications396TABLE 31-10: SPIx Master Mode (CKE = 0) Timing Requirements397TABLE 31-11: SPIx Module Master Mode (CKE = 1) Timing Requirements397TABLE 31-12: SPIx Module Slave Mode (CKE = 0) Timing Requirements398TABLE 31-13: SPIx Module Slave Mode (CKE = 1) Timing Requirements398TABLE 31-14: ADC Module Specifications399TABLE 31-15: ADC Module Specifications (12-bit Mode)399TABLE 31-16: ADC Module Specifications (10-bit Mode)400TABLE 31-17: ADC Conversion (12-bit Mode) Timing Requirements401TABLE 31-18: ADC Conversion (10-bit mode) Timing Requirements40132.0 DC and AC Device Characteristics Graphs403FIGURE 32-1: Voh – 2x Driver Pins403FIGURE 32-2: Voh – 4x Driver Pins403FIGURE 32-3: Voh – 8x Driver Pins403FIGURE 32-4: Voh – 16x Driver Pins403FIGURE 32-5: Vol – 2x Driver Pins404FIGURE 32-6: Vol – 4x Driver Pins404FIGURE 32-7: Vol – 8x Driver Pins404FIGURE 32-8: Vol – 16x Driver Pins404FIGURE 32-9: Typical Ipd Current @ Vdd = 3.3V, +85ºC405FIGURE 32-10: Typical Idd Current @ Vdd = 3.3V, +85ºC405FIGURE 32-11: Typical Idoze Current @ Vdd = 3.3V, +85ºC405FIGURE 32-12: Typical Iidle Current @ Vdd = 3.3V, +85ºC405FIGURE 32-13: Typical FRC Frequency @ Vdd = 3.3V406FIGURE 32-14: Typical LPRC Frequency @ Vdd = 3.3V40633.0 Packaging Information40733.1 Package Details408Appendix A: Revision History417TABLE A-1: Major Section Updates417TABLE A-2: Major Section Updates (Continued)418TABLE A-3: Major Section Updates421TABLE A-4: Major Section Updates (Continued)422TABLE A-5: Major Section Updates425TABLE A-6: Major Section Updates425INDEX427Worldwide Sales and Service436Size: 6.04 MBPages: 436Language: EnglishOpen manual