Data SheetTable of ContentsTABLE 1: Silicon DEVREV Values1TABLE 2: Silicon Issue Summary2Silicon Errata Issues31. Module: SPI3EXAMPLE 1:32. Module: SPI33. Module: UART3EXAMPLE 2:34. Module: UART35. Module: CPU46. Module: CPU47. Module: Oscillator4Data Sheet Clarifications5Appendix A: Revision History6Worldwide Sales and Service8Size: 204 KBPages: 8Language: EnglishOpen manual
Data SheetTable of ContentsOperating Conditions1Core: 16-Bit dsPIC33F CPU1Clock Management1Power Management1PWM1Advanced Analog Features1Timers/Output Compare/Input Capture1Communication Interfaces1Input/Output1Qualification and Class B Support1Debugger Development Support1dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 Product Families2TABLE 1: dsPIC33FJ16(GP/MC)101/102 Device Features2TABLE 2: dsPIC33FJ32(GP/MC)101/102/104 Device Features3Pin Diagrams4Pin Diagrams (Continued)5Pin Diagrams (Continued)6Pin Diagrams (Continued)7Pin Diagrams (Continued)8Pin Diagrams (Continued)9Pin Diagrams (Continued)10Pin Diagrams (Continued)11Pin Diagrams (Continued)12Pin Diagrams (Continued)13Pin Diagrams (Continued)14Pin Diagrams (Continued)15Pin Diagrams (Continued)16Pin Diagrams (Continued)17Pin Diagrams (Continued)18Pin Diagrams (Continued)19Pin Diagrams (Continued)20Pin Diagrams (Continued)21Pin Diagrams (Continued)22Table of Contents23Most Current Data Sheet24Errata24Customer Notification System24Referenced Sources251.0 Device Overview27FIGURE 1-1: dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 Block Diagram28TABLE 1-1: Pinout I/O Descriptions292.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers332.1 Basic Connection Requirements332.2 Decoupling Capacitors33FIGURE 2-1: Recommended Minimum Connection342.2.1 Tank Capacitors342.3 CPU Logic Filter Capacitor Connection (Vcap)342.4 Master Clear (MCLR) Pin34FIGURE 2-2: Example of MCLR Pin Connections342.5 ICSP Pins352.6 External Oscillator Pins35FIGURE 2-3: Suggested Placement of the Oscillator Circuit352.7 Oscillator Value Conditions on Device Start-up362.8 Configuration of Analog and Digital Pins During ICSP Operations362.9 Unused I/Os363.0 CPU373.1 Data Addressing Overview373.2 DSP Engine Overview373.3 Special MCU Features38FIGURE 3-1: dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 CPU Core Block Diagram38FIGURE 3-2: dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 Programmer’s Model393.4 CPU Control Registers40Register 3-1: SR: CPU Status Register40Register 3-2: CORCON: Core Control Register423.5 Arithmetic Logic Unit (ALU)433.5.1 Multiplier433.5.2 Divider433.6 DSP Engine43TABLE 3-1: DSP Instructions Summary43FIGURE 3-3: DSP Engine Block Diagram443.6.1 Multiplier453.6.2 Data Accumulators and Adder/Subtracter453.6.3 Accumulator ‘Write Back’463.6.4 Barrel Shifter474.0 Memory Organization494.1 Program Address Space49FIGURE 4-1: Program Memory Map for dsPIC33FJ16(GP/MC)101/102 Devices49FIGURE 4-2: Program Memory Map for dsPIC33FJ32(GP/MC)101/102/104 Devices504.1.1 Program Memory Organization514.1.2 Interrupt and Trap Vectors51FIGURE 4-3: Program Memory Organization514.2 Data Address Space524.2.1 Data Space Width524.2.2 Data Memory Organization and Alignment524.2.3 SFR Space524.2.4 Near Data Space52FIGURE 4-4: Data Memory Map for dsPIC33FJ16(GP/MC)101/102 Devices with 1-Kbyte RAM53FIGURE 4-5: Data Memory Map for dsPIC33FJ32(GP/MC)101/102/104 Devices with 2-KBYTE RAM544.2.5 X and Y Data Spaces55TABLE 4-1: CPU Core Register Map56TABLE 4-2: Change Notification Register Map FOR dsPIC33FJXXGP101 Devices58TABLE 4-3: Change Notification Register Map FOR dsPIC33FJXXMC101 Devices58TABLE 4-4: Change Notification Register Map for dsPIC33FJXX(GP/MC)102 Devices58TABLE 4-5: Change Notification Register Map for dsPIC33FJ32(GP/MC)104 Devices58TABLE 4-6: Interrupt Controller Register Map59TABLE 4-7: Timers Register Map for dsPIC33FJ16(GP/MC)10X Devices60TABLE 4-8: Timers Register Map for dsPIC33FJ32(GP/MC)10X Devices60TABLE 4-9: Input Capture Register Map61TABLE 4-10: Output Compare Register Map61TABLE 4-11: 6-Output PWM1 Register Map for dsPIC33FJXXMC10X Devices61TABLE 4-12: I2C1 Register Map62TABLE 4-13: UART1 Register Map62TABLE 4-14: SPI1 Register Map62TABLE 4-15: ADC1 Register Map for dsPIC33FJXX(GP/MC)101 Devices63TABLE 4-16: ADC1 Register Map for dsPIC33FJXX(GP/MC)102 Devices64TABLE 4-17: ADC1 Register Map for dsPIC33FJ32(GP/MC)104 Devices65TABLE 4-18: CTMU Register Map66TABLE 4-19: Real-Time Clock and Calendar Register Map66TABLE 4-20: pad Configuration Register Map66TABLE 4-21: Comparator Register Map67TABLE 4-22: Peripheral Pin Select Input Register Map67TABLE 4-23: Peripheral Pin Select Output Register Map for dsPIC33FJXXGP101 Devices68TABLE 4-24: Peripheral Pin Select Output Register Map for dsPIC33FJXXMC101 Devices68TABLE 4-25: Peripheral Pin Select Output Register Map for dsPIC33FJXX(GP/MC)102 Devices68TABLE 4-26: Peripheral Pin Select Output Register Map for dsPIC33FJ32(GP/MC)104 Devices69TABLE 4-27: PORTA Register Map for dsPIC33FJ16(GP/MC)101/102 Devices69TABLE 4-28: PORTA Register Map for dsPIC33FJ32(GP/MC)101/102 Devices69TABLE 4-29: PORTA Register Map for dsPIC33FJ32(GP/MC)104 Devices70TABLE 4-30: PORTB Register Map for dsPIC33FJ16GP101 Devices70TABLE 4-31: PORTB Register Map for dsPIC33FJ16MC101 Devices70TABLE 4-32: PORTB Register Map for dsPIC33FJ16(GP/MC)102 Devices70TABLE 4-33: PORTB Register Map for dsPIC33FJ32GP101 Devices71TABLE 4-34: PORTB Register Map for dsPIC33FJ32MC101 Devices71TABLE 4-35: PORTB Register Map for dsPIC33FJ32(GP/MC)102 and dsPIC33FJ32(GP/MC)104 Devices71TABLE 4-36: PORTC Register Map for dsPIC33FJ32(GP/MC)104 Devices71TABLE 4-37: System Control Register Map72TABLE 4-38: NVM Register Map72TABLE 4-39: PMD Register Map724.2.6 Software Stack73FIGURE 4-6: CALL Stack Frame734.2.7 Data Ram Protection Feature734.3 Instruction Addressing Modes734.3.1 File Register Instructions734.3.2 MCU Instructions73TABLE 4-40: Fundamental Addressing Modes Supported744.3.3 Move and Accumulator Instructions744.3.4 MAC Instructions744.3.5 Other Instructions744.4 Modulo Addressing754.4.1 Start and End Address754.4.2 W Address Register Selection75FIGURE 4-7: Modulo Addressing Operation Example754.4.3 Modulo Addressing Applicability764.5 Bit-Reversed Addressing764.5.1 Bit-Reversed Addressing Implementation76FIGURE 4-8: Bit-Reversed Address Example77TABLE 4-41: Bit-Reversed Address Sequence (16-Entry)774.6 Interfacing Program and Data Memory Spaces784.6.1 Addressing Program Space78TABLE 4-42: Program Space Address Construction78FIGURE 4-9: Data Access from Program Space Address Generation794.6.2 Data Access from Program Memory Using Table Instructions80FIGURE 4-10: Accessing Program Memory with Table Instructions804.6.3 Reading Data from Program Memory Using Program Space Visibility81FIGURE 4-11: Program Space Visibility Operation815.0 Flash Program Memory835.1 Table Instructions and Flash Programming83FIGURE 5-1: Addressing for Table Registers835.2 RTSP Operation845.3 Programming Operations84EQUATION 5-1: Programming Time84EQUATION 5-2: Minimum Row Write Time84EQUATION 5-3: Maximum Row Write Time845.3.1 Programming Algorithm for Flash Program Memory845.4 Control Registers84Register 5-1: NVMCON: Flash Memory Control Register85Register 5-2: NVMKEY: Nonvolatile Memory Key Register856.0 Resets87FIGURE 6-1: Reset System Block Diagram876.1 Reset Control Register88Register 6-1: RCON: Reset Control Register(1)886.2 System Reset90TABLE 6-1: Oscillator Delay90FIGURE 6-2: System Reset Timing91TABLE 6-2: Oscillator Parameters916.3 POR926.4 BOR and PWRT92FIGURE 6-3: Brown-out Reset Situations926.5 External Reset (EXTR)936.5.1 External Supervisory Circuit936.5.2 Internal Supervisory Circuit936.6 Software RESET Instruction (SWR)936.7 Watchdog Timer Time-out Reset (WDTO)936.8 Trap Conflict Reset936.9 Configuration Mismatch Reset936.10 Illegal Condition Device Reset936.10.1 Illegal Opcode Reset936.10.2 Uninitialized W Register Reset946.10.3 Security Reset946.11 Using the RCON Status Bits94TABLE 6-3: Reset Flag Bit Operation947.0 Interrupt Controller957.1 Interrupt Vector Table957.1.1 Alternate Interrupt Vector Table957.2 Reset Sequence95FIGURE 7-1: dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 Interrupt Vector Table96TABLE 7-1: Interrupt Vectors97TABLE 7-2: Trap Vectors987.3 Interrupt Control and Status Registers987.3.1 INTCON1 and INTCON2987.3.2 IFSx Registers987.3.3 IECx Registers987.3.4 IPCx Registers987.3.5 INTTREG987.3.6 Status/Control Registers98Register 7-1: SR: CPU Status Register(1)99Register 7-2: CORCON: Core Control Register(1)99Register 7-3: INTCON1: Interrupt Control Register 1100Register 7-4: INTCON2: Interrupt Control Register 2102Register 7-5: IFS0: Interrupt Flag Status Register 0103Register 7-6: IFS1: Interrupt Flag Status Register 1105Register 7-7: IFS2: Interrupt Flag Status Register 2106Register 7-8: IFS3: Interrupt Flag Status Register 3106Register 7-9: IFS4: Interrupt Flag Status Register 4107Register 7-10: IEC0: Interrupt Enable Control Register 0108Register 7-11: IEC1: Interrupt Enable Control Register 1109Register 7-12: IEC2: Interrupt Enable Control Register 2110Register 7-13: IEC3: Interrupt Enable Control Register 3110Register 7-14: IEC4: Interrupt Enable Control Register 4111Register 7-15: IPC0: Interrupt Priority Control Register 0112Register 7-16: IPC1: Interrupt Priority Control Register 1113Register 7-17: IPC2: Interrupt Priority Control Register 2114Register 7-18: IPC3: Interrupt Priority Control Register 3115Register 7-19: IPC4: Interrupt Priority Control Register 4116Register 7-20: IPC5: Interrupt Priority Control Register 5117Register 7-21: IPC6: Interrupt Priority Control Register 6117Register 7-22: IPC7: Interrupt Priority Control Register 7118Register 7-23: IPC9: Interrupt Priority Control Register 9119Register 7-24: IPC14: Interrupt Priority Control Register 14119Register 7-25: IPC15: Interrupt Priority Control Register 15120Register 7-26: IPC16: Interrupt Priority Control Register 16121Register 7-27: IPC19: Interrupt Priority Control Register 19122Register 7-28: INTTREG: Interrupt Control and Status Register1237.4 Interrupt Setup Procedures1247.4.1 Initialization1247.4.2 Interrupt Service Routine1247.4.3 Trap Service Routine1247.4.4 Interrupt Disable1248.0 Oscillator Configuration125FIGURE 8-1: Oscillator System Diagram1258.1 CPU Clocking System1268.1.1 System Clock Sources1268.1.2 System Clock Selection126EQUATION 8-1: Device Operating Frequency1268.1.3 PLL Configuration127EQUATION 8-2: MS with PLL Mode Example127TABLE 8-1: Configuration Bit Values for Clock Selection1278.2 Oscillator Control Registers128Register 8-1: OSCCON: Oscillator Control Register(1)128Register 8-2: CLKDIV: Clock Divisor Register130Register 8-3: OSCTUN: FRC Oscillator Tuning Register1318.3 Clock Switching Operation1328.3.1 Enabling Clock Switching1328.3.2 Oscillator Switching Sequence1328.4 Fail-Safe Clock Monitor (FSCM)1329.0 Power-Saving Features1339.1 Clock Frequency and Clock Switching1339.2 Instruction-Based Power-Saving Modes1339.2.1 Sleep Mode133EXAMPLE 9-1: PWRSAV Instruction Syntax1339.2.2 Idle Mode1349.2.3 Interrupts Coincident with Power Save Instructions1349.3 Doze Mode1349.4 Peripheral Module Disable1349.5 PMD Control Registers135Register 9-1: PMD1: Peripheral Module Disable Control Register 1135Register 9-2: PMD2: Peripheral Module Disable Control Register 2136Register 9-3: PMD3: Peripheral Module Disable Control Register 3137Register 9-4: PMD4: Peripheral Module Disable Control Register 413710.0 I/O Ports13910.1 Parallel I/O (PIO) Ports139FIGURE 10-1: Block Diagram of a Typical Shared Port Structure14010.1.1 Open-Drain Configuration14110.2 Configuring Analog Port Pins14110.2.1 I/O Port Write/Read Timing14110.3 Input Change Notification (ICN)141EXAMPLE 10-1: Port Write/Read Example14110.4 Peripheral Pin Select (PPS)14210.4.1 Available Pins14210.4.2 Controlling Peripheral Pin Select142FIGURE 10-2: Remappable MUX Input for U1RX142TABLE 10-1: Selectable Input Sources (Maps Input to Function)(1)143FIGURE 10-3: Multiplexing of Remappable Output for Rpn144TABLE 10-2: Output Selection for Remappable Pin (RPn)14410.4.3 Controlling Configuration Changes14510.5 I/O Helpful Tips14610.6 I/O Resources14610.6.1 Key Resources14610.7 Peripheral Pin Select Registers147Register 10-1: RPINR0: Peripheral Pin Select Input Register 0147Register 10-2: RPINR1: Peripheral Pin Select Input Register 1148Register 10-3: RPINR3: Peripheral Pin Select Input Register 3149Register 10-4: RPINR4: Peripheral Pin Select Input Register 4150Register 10-5: RPINR7: Peripheral Pin Select Input Register 7151Register 10-6: RPINR8: Peripheral Pin Select Input Register 8152Register 10-7: RPINR11: Peripheral Pin Select Input Register 11153Register 10-8: RPINR18: Peripheral Pin Select Input Register 18154Register 10-9: RPINR20: Peripheral Pin Select Input Register 20155Register 10-10: RPINR21: Peripheral Pin Select Input Register 21156Register 10-11: RPOR0: Peripheral Pin Select Output Register 0157Register 10-12: RPOR1: Peripheral Pin Select Output Register 1157Register 10-13: RPOR2: Peripheral Pin Select Output Register 2158Register 10-14: RPOR3: Peripheral Pin Select Output Register 3158Register 10-15: RPOR4: Peripheral Pin Select Output Register 4159Register 10-16: RPOR5: Peripheral Pin Select Output Register 5159Register 10-17: RPOR6: Peripheral Pin Select Output Register 6160Register 10-18: RPOR7: Peripheral Pin Select Output Register 7160Register 10-19: RPOR8: Peripheral Pin Select Output Register 8161Register 10-20: RPOR9: Peripheral Pin Select Output Register 9161Register 10-21: RPOR10: Peripheral Pin Select Output Register 10162Register 10-22: RPOR11: Peripheral Pin Select Output Register 11162Register 10-23: RPOR12: Peripheral Pin Select Output Register 1216311.0 Timer1165FIGURE 11-1: 16-bit Timer1 Module Block Diagram16511.1 Timer1 Control Register166Register 11-1: T1CON: Timer1 Control Register16612.0 Timer2/3 and Timer4/516712.1 32-Bit Operation16712.2 16-Bit Operation167FIGURE 12-1: Timer2/3 and Timer4/5 (32-bit) Block Diagram(1,3,4)168FIGURE 12-2: Timer2 and Timer4 (16-bit) Block Diagram(1)169FIGURE 12-3: Timer3 and Timer5 (16-bit) Block diagram(1)16912.3 Timer2/3 and Timer4/5 Control Registers170Register 12-1: T2CON: Timer2 Control Register170Register 12-2: T3CON: Timer3 Control Register171Register 12-3: T4CON: Timer4 Control Register(1)172Register 12-4: T5CON: Timer5 Control Register(1)17313.0 Input Capture175FIGURE 13-1: Input Capture x Block Diagram17513.1 Input Capture Control Register176Register 13-1: ICxCON: Input Capture x Control Register17614.0 Output Compare177FIGURE 14-1: Output Compare x Module Block Diagram17714.1 Output Compare Modes178TABLE 14-1: Output Compare x Modes178FIGURE 14-2: Output Compare x Operation17814.2 Output Compare Control Register179Register 14-1: OCxCON: Output Compare x Control Register17915.0 Motor Control PWM Module18115.1 PWM1: 6-Channel PWM Module181FIGURE 15-1: 6-Channel PWM Module Block Diagram (PWM1)18215.2 PWM Faults183TABLE 15-1: Internal Pull-down resistors on PWM Fault pins18315.2.1 PWM Faults at Reset18315.3 Write-Protected Registers183EXAMPLE 15-1: Assembly Code for Write-protected register unlock and Fault Clearing sequence184EXAMPLE 15-2: C Code for Write-protected register unlock and Fault Clearing sequence18415.4 PWM Control Registers185Register 15-1: PxTCON: PWMx Time Base Control Register185Register 15-2: PxTMR: PWMx Timer Count Value Register186Register 15-3: PxTPER: PWMx Time Base Period Register186Register 15-4: PxSECMP: PWMx Special Event Compare Register187Register 15-5: PWMXCON1: PWMx Control Register 1(1)188Register 15-6: PWMxCON2: PWMx Control Register 2189Register 15-7: PxDTCON1: PWMx Dead-Time Control Register 1190Register 15-8: PxDTCON2: PWMx Dead-Time Control Register 2191Register 15-9: PxFLTACON: PWMx Fault A Control Register(1,2,3,4)192Register 15-10: PxFLTBCON: PWMx Fault B Control Register(1,2,3,4)193Register 15-11: PxOVDCON: PWMx Override Control Register194Register 15-12: PxDC1: PWMx Duty Cycle 1 Register195Register 15-13: PxDC2: PWMx Duty Cycle 2 Register195Register 15-14: PxDC3: PWMx Duty Cycle 3 Register195Register 15-15: PWMxKEY: PWMx Unlock Register19616.0 Serial Peripheral Interface (SPI)197FIGURE 16-1: SPIx Module Block Diagram19716.1 SPI Helpful Tips19816.2 SPI Resources19816.2.1 Key Resources19816.3 SPI Control Registers199Register 16-1: SPIxSTAT: SPIx Status and Control Register199Register 16-2: SPIxCON1: SPIx Control Register 1200Register 16-3: SPIxCON2: SPIx Control Register 220217.0 Inter-Integrated Circuit™ (I2C™)20317.1 Operating Modes20317.2 I2C Registers203FIGURE 17-1: I2C™ Block Diagram (x = 1)20417.3 I2C Control Registers205Register 17-1: I2CxCON: I2Cx Control Register205Register 17-2: I2CxSTAT: I2Cx Status Register207Register 17-3: I2CxMSK: I2Cx Slave Mode Address Mask Register20918.0 Universal Asynchronous Receiver Transmitter (UART)211FIGURE 18-1: UARTx Simplified Block Diagram21118.1 UART Helpful Tips21218.2 UART Resources21218.2.1 Key Resources21218.3 UART Control Registers213Register 18-1: UxMODE: UARTx Mode Register213Register 18-2: UxSTA: UARTx Status and Control Register21519.0 10-Bit Analog-to-Digital Converter (ADC)21719.1 Key Features21719.2 ADC Initialization217FIGURE 19-1: ADC1 Block Diagram for dsPIC33FJXX(GP/MC)101 Devices218FIGURE 19-2: ADC1 Block Diagram for dsPIC33FJXX(GP/MC)102 Devices219FIGURE 19-3: ADC1 Block Diagram for dsPIC33FJ32(GP/MC)104 Devices220FIGURE 19-4: ADC1 Conversion Clock Period Block Diagram22119.3 ADC Helpful Tips22119.4 ADC Resources22119.4.1 Key Resources22119.5 ADC Control Registers222Register 19-1: AD1CON1: ADC1 Control Register 1222Register 19-2: AD1CON2: ADC1 Control Register 2224Register 19-3: AD1CON3: ADC1 Control Register 3225Register 19-4: AD1CHS123: ADC1 Input Channel 1, 2, 3 Select Register226Register 19-5: AD1CHS0: ADC1 INPUT Channel 0 select Register227Register 19-6: AD1CSSL: ADC1 Input Scan Select Register Low(1,2,3)228Register 19-7: AD1PCFGL: ADC1 Port Configuration Register Low(1,2,3)22920.0 Comparator Module231FIGURE 20-1: Comparator I/O Operating Modes231FIGURE 20-2: Comparator Voltage Reference Block Diagram232FIGURE 20-3: User-Programmable Blanking Function Block Diagram232FIGURE 20-4: Digital Filter Interconnect Block Diagram23320.1 Comparator Control Registers234Register 20-1: CMSTAT: Comparator Status Register234Register 20-2: CMxCON: Comparator x Control Register235Register 20-3: CMxMSKSRC: Comparator x Mask Source Select Register237Register 20-4: CMxMSKCON: Comparator x Mask Gating Control Register239Register 20-5: CMxFLTR: Comparator x Filter Control Register241Register 20-6: CVRCON: Comparator Voltage Reference Control Register24221.0 Real-Time Clock and Calendar (RTCC)243FIGURE 21-1: RTCC Block Diagram24321.1 RTCC Module Registers24421.1.1 Register Mapping244TABLE 21-1: RTCVAL Register Mapping244TABLE 21-2: ALRMVAL Register Mapping24421.1.2 Write Lock244EXAMPLE 21-1: Setting the RTCWREN Bit24421.2 RTCC Control Registers245Register 21-1: RCFGCAL: RTCC Calibration and Configuration Register(1)245Register 21-2: PADCFG1: Pad Configuration Control Register247Register 21-3: ALCFGRPT: Alarm Configuration Register248Register 21-4: RTCVAL (when RTCPTR<1:0> = 11): RTCC YEAR VALUE Register(1)249Register 21-5: RTCVAL (when RTCPTR<1:0> = 10): RTCC MONTH AND DAY VALUE Register(1)249Register 21-6: RTCVAL (when RTCPTR<1:0> = 01): RTCC Weekday and Hours Value Register(1)250Register 21-7: RTCVAL (when RTCPTR<1:0> = 00): RTCC Minutes and Seconds Value Register251Register 21-8: ALRMVAL (when ALRMPTR<1:0> = 10): Alarm Month and Day Value Register(1)252Register 21-9: ALRMVAL (when ALRMPTR<1:0> = 01): Alarm Weekday and Hours Value Register(1)253Register 21-10: ALRMVAL (when ALRMPTR<1:0> = 00): Alarm Minutes and Seconds Value Register25422.0 Charge Time Measurement Unit (CTMU)255FIGURE 22-1: CTMU Block Diagram25622.1 CTMU Control Registers257Register 22-1: CTMUCON1: CTMU Control Register 1257Register 22-2: CTMUCON2: CTMU Control Register 2258Register 22-3: CTMUICON: CTMU Current Control Register25923.0 Special Features26123.1 Configuration Bits261TABLE 23-1: Configuration Shadow Register Map262TABLE 23-2: Configuration FLASH WORDS for dsPIC33FJ16(GP/MC)10X Devices(1)262TABLE 23-3: Configuration FLASH WORDS for dsPIC33FJ32(GP/MC)10X Devices(1)262TABLE 23-4: dsPIC33F Configuration Bits Description263Register 23-1: DEVID: Device ID Register265Register 23-2: DEVREV: Device Revision Register26523.2 On-Chip Voltage Regulator266FIGURE 23-1: Connections for the On-Chip Voltage Regulator(1,2,3)26623.3 BOR: Brown-out Reset26623.4 Watchdog Timer (WDT)26723.4.1 Prescaler/Postscaler26723.4.2 Sleep and Idle Modes26723.4.3 Enabling WDT267FIGURE 23-2: WDT Block Diagram26723.5 In-Circuit Serial Programming™ (ICSP™)26823.6 In-Circuit Debugger26824.0 Instruction Set Summary269TABLE 24-1: Symbols used in Opcode Descriptions270TABLE 24-2: Instruction Set Overview27225.0 Development Support27725.1 MPLAB X Integrated Development Environment Software27725.2 MPLAB XC Compilers27825.3 MPASM Assembler27825.4 MPLINK Object Linker/ MPLIB Object Librarian27825.5 MPLAB Assembler, Linker and Librarian for Various Device Families27825.6 MPLAB X SIM Software Simulator27925.7 MPLAB REAL ICE In-Circuit Emulator System27925.8 MPLAB ICD 3 In-Circuit Debugger System27925.9 PICkit 3 In-Circuit Debugger/ Programmer27925.10 MPLAB PM3 Device Programmer27925.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits28025.12 Third-Party Development Tools28026.0 Electrical Characteristics281Absolute Maximum Ratings(1)28126.1 DC Characteristics282TABLE 26-1: Operating MIPS vs. Voltage282TABLE 26-2: Thermal Operating Conditions282TABLE 26-3: Thermal Packaging Characteristics282TABLE 26-4: DC Temperature and Voltage specifications283TABLE 26-5: Electrical Characteristics: Brown-out Reset (BOR)283TABLE 26-6: DC Characteristics: Operating Current (Idd)284TABLE 26-7: DC Characteristics: Idle Current (Iidle)286TABLE 26-8: DC Characteristics: Power-Down Current (Ipd)288TABLE 26-9: DC Characteristics: Doze Current (Idoze)289TABLE 26-10: DC Characteristics: I/O Pin Input Specifications290TABLE 26-11: DC Characteristics: I/O Pin Output Specifications292TABLE 26-12: DC Characteristics: Program Memory293TABLE 26-13: Internal Voltage Regulator Specifications29326.2 AC Characteristics and Timing Parameters294TABLE 26-14: Temperature and Voltage Specifications – AC294FIGURE 26-1: Load Conditions for Device Timing Specifications294TABLE 26-15: Capacitive Loading Requirements on Output Pins294FIGURE 26-2: External Clock Timing295TABLE 26-16: External Clock Timing Requirements295TABLE 26-17: PLL Clock Timing Specifications296TABLE 26-18: AC Characteristics: Internal Fast RC (FRC) Accuracy296TABLE 26-19: Internal Low-Power RC (LPRC) Accuracy296FIGURE 26-3: CLKO and I/O Timing Characteristics297TABLE 26-20: I/O Timing Requirements297FIGURE 26-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics298TABLE 26-21: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Timing Requirements298FIGURE 26-5: Timer1/2/3 External Clock Timing Characteristics299TABLE 26-22: Timer1 External Clock Timing Requirements(1)299TABLE 26-23: Timer2/4 External Clock Timing Requirements300TABLE 26-24: Timer3/5 External Clock Timing Requirements300FIGURE 26-6: Input Capture x (ICx) Timing Characteristics301TABLE 26-25: Input Capture x (ICx) Timing Requirements301FIGURE 26-7: Output Compare x (OCx) Timing Characteristics302TABLE 26-26: Output Compare x (OCx) Module Timing Requirements302FIGURE 26-8: OCx/PWMx Module Timing Characteristics302TABLE 26-27: Simple OCx/PWMx MODE Timing Requirements302FIGURE 26-9: Motor Control PWMx Module Fault Timing Characteristics303FIGURE 26-10: Motor Control PWMx Module Timing Characteristics303TABLE 26-28: Motor Control PWMx Module Timing Requirements303TABLE 26-29: SPIx Maximum Data/Clock Rate Summary for dsPIC33FJ16(GP/MC)10X304FIGURE 26-11: SPIx MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS for dsPIC33FJ16(GP/MC)10X304FIGURE 26-12: SPIx MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS for dsPIC33FJ16(GP/MC)10X305TABLE 26-30: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements for dsPIC33FJ16(GP/MC)10X305FIGURE 26-13: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS for dsPIC33FJ16(GP/MC)10X306TABLE 26-31: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements for dsPIC33FJ16(GP/MC)10X306FIGURE 26-14: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS for dsPIC33FJ16(GP/MC)10X307TABLE 26-32: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements for dsPIC33FJ16(GP/MC)10X307FIGURE 26-15: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS for dsPIC33FJ16(GP/MC)10X308TABLE 26-33: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements for dsPIC33FJ16(GP/MC)10X309FIGURE 26-16: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS for dsPIC33FJ16(GP/MC)10X310TABLE 26-34: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements for dsPIC33FJ16(GP/MC)10X311FIGURE 26-17: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS for dsPIC33FJ16(GP/MC)10X312TABLE 26-35: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements for dsPIC33FJ16(GP/MC)10X313FIGURE 26-18: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS for dsPIC33FJ16(GP/MC)10X314TABLE 26-36: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements for dsPIC33FJ16(GP/MC)10X315TABLE 26-37: SPIx Maximum Data/CLock Rate Summary for dsPIC33FJ32(GP/MC)10X316FIGURE 26-19: SPIx MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS for dsPIC33FJ32(GP/MC)10X316FIGURE 26-20: SPIx MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS for dsPIC33FJ32(GP/MC)10X317TABLE 26-38: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements for dsPIC33FJ32(GP/MC)10X317FIGURE 26-21: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS for dsPIC33FJ32(GP/MC)10X318TABLE 26-39: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements for dsPIC33FJ32(GP/MC)10X318FIGURE 26-22: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS for dsPIC33FJ32(GP/MC)10X319TABLE 26-40: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements for dsPIC33FJ32(GP/MC)10X319FIGURE 26-23: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS for dsPIC33FJ32(GP/MC)10X320TABLE 26-41: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements for dsPIC33FJ32(GP/MC)10X321FIGURE 26-24: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS for dsPIC33FJ32(GP/MC)10X322TABLE 26-42: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements for dsPIC33FJ32(GP/MC)10X323FIGURE 26-25: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS for dsPIC33FJ32(GP/MC)10X324TABLE 26-43: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements for dsPIC33FJ32(GP/MC)10X325FIGURE 26-26: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS for dsPIC33FJ32(GP/MC)10X326TABLE 26-44: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements for dsPIC33FJ32(GP/MC)10X327FIGURE 26-27: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)328FIGURE 26-28: I2Cx Bus Data Timing Characteristics (Master mode)328TABLE 26-45: I2Cx Bus Data Timing Requirements (Master Mode)329FIGURE 26-29: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)330FIGURE 26-30: I2Cx Bus Data Timing Characteristics (slave mode)330TABLE 26-46: I2Cx Bus Data Timing Requirements (Slave Mode)331TABLE 26-47: ADC Module Specifications332TABLE 26-48: 10-bit ADC Module Specifications333FIGURE 26-31: ADC Conversion Timing Characteristics (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)334FIGURE 26-32: ADC Conversion Timing Characteristics (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)334TABLE 26-49: 10-bit ADC CONVERSION Timing Requirements335TABLE 26-50: Comparator Timing Specifications336TABLE 26-51: Comparator Module Specifications336TABLE 26-52: Comparator Voltage Reference Settling Time Specifications336TABLE 26-53: Comparator Voltage Reference Specifications337TABLE 26-54: CTMU Current Source Specifications337FIGURE 26-33: Forward Voltage Versus Temperature33827.0 High-Temperature Electrical Characteristics339Absolute Maximum Ratings(1)33927.1 High-Temperature DC Characteristics340TABLE 27-1: Operating MIPS vs. Voltage340TABLE 27-2: Thermal Operating Conditions340TABLE 27-3: DC Characteristics: Operating Current (Idd))340TABLE 27-4: DC Characteristics: Operating Current (Idd))341TABLE 27-5: DC Characteristics: Idle Current (Iidle))341TABLE 27-6: DC Characteristics: Power-down Current (Ipd)341TABLE 27-7: DC Characteristics: Doze Current (Idoze)342TABLE 27-8: DC Characteristics: Program Memory342TABLE 27-9: AC Characteristics: Internal Fast RC (FRC) Accuracy342TABLE 27-10: Internal Low-Power RC (LPRC) Accuracy34228.0 Packaging Information34328.1 Package Marking Information34328.1 Package Marking Information (Continued)34428.1 Package Marking Information (Continued)34528.2 Package Details346Appendix A: Revision History373Revision A (January 2011)373Revision B (February 2011)373TABLE A-1: Major Section Updates373Revision C (June 2011)374TABLE A-2: Major Section Updates374Revision D (April 2012)376TABLE A-3: Major Section Updates376Revision E (September 2012)379Revision F (January 2014)379INDEX381The Microchip Web Site387Customer Change Notification Service387Customer Support387Product Identification System389Worldwide Sales and Service392Size: 3.88 MBPages: 392Language: EnglishOpen manual
