Data SheetTable of ContentsTABLE 1: Silicon DEVREV Values2TABLE 2: Silicon Issue Summary5Silicon Errata Issues71. Module: CPU72. Module: CPU73. Module: SPI74. Module: SPI75. Module: UART86. Module: Power System87. Module: ADC88. Module: PTG89. Module: Op Amp910. Module: Op Amp9TABLE 3: AC/DC Characteristics: Op amp9TABLE 4: AC/DC Characteristics: ADC911. Module: PWM1012. Module: Flash10EXAMPLE 1: Work Around Code1013. Module: QEI1114. Module: QEI1115. Module: PWM1116. Module: ADC1217. Module: ADC1218. Module: Output Compare1219. Module: CAN1220. Module: PWM13FIGURE 1: Timing Diagrams for Center Aligned and Edge Aligned Modes1321. Module: PWM14EXAMPLE 2: Work around Code1422. Module: PWM1423. Module: CPU1524. Module: PWM15FIGURE 2: PWM Timing Diagram1525. Module: PWM1626. Module: PWM1627. Module: CTMU1628. Module: Input Capture1629. Module: JTAG1630. Module: I/O1731. Module: JTAG1732. Module: QEI1733. Module: QEI18FIGURE 3: CORRECT AND INCORRECT POSITION COUNT CAPTURES1834. Module: QEI1835. Module: PWM19FIGURE 4: PWM Generator Timing Diagram19EXAMPLE 3: Work Around Code19EXAMPLE 4: Work Around Code2036. Module: PWM20EXAMPLE 5: Work Around Code20TABLE 5: Maximum External Current Reset Signal Width2037. Module: Op Amp/Comparator2038. Module: PWM21FIGURE 5: Illustration of 1 Tosc Glitch When PWM Override is Turned Off2139. Module: PWM2240. Module: PWM2241. Module: CAN22EXAMPLE 6: Work around Code22Data Sheet Clarifications23Appendix A: Revision History24Worldwide Sales and Service26Size: 416 KBPages: 26Language: EnglishOpen manual
Data SheetTable of ContentsOperating Conditions1Core: 16-Bit dsPIC33E/PIC24E CPU1Clock Management1Power Management1High-Speed PWM1Advanced Analog Features1Timers/Output Compare/Input Capture1Communication Interfaces1Direct Memory Access (DMA)1Input/Output1Qualification and Class B Support1Debugger Development Support1dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X Product Families2TABLE 1: dsPIC33EPXXXGP50X and PIC24EPXXXGP20X General Purpose Families2TABLE 2: dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Motor Control Families3Pin Diagrams5Pin Diagrams (Continued)6Pin Diagrams (Continued)7Pin Diagrams (Continued)8Pin Diagrams (Continued)9Pin Diagrams (Continued)10Pin Diagrams (Continued)11Pin Diagrams (Continued)12Pin Diagrams (Continued)13Pin Diagrams (Continued)14Pin Diagrams (Continued)15Pin Diagrams (Continued)16Pin Diagrams (Continued)17Pin Diagrams (Continued)18Pin Diagrams (Continued)19Pin Diagrams (Continued)20Pin Diagrams (Continued)21Table of Contents22Most Current Data Sheet23Errata23Customer Notification System23Referenced Sources241.0 Device Overview25FIGURE 1-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X Block Diagram25TABLE 1-1: Pinout I/O Descriptions262.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers and Microcontrollers292.1 Basic Connection Requirements292.2 Decoupling Capacitors29FIGURE 2-1: Recommended Minimum connection302.3 CPU Logic Filter Capacitor Connection (Vcap)302.4 Master Clear (MCLR) Pin30FIGURE 2-2: Example of MCLR Pin Connections302.5 ICSP Pins312.6 External Oscillator Pins31FIGURE 2-3: Suggested Placement of the Oscillator Circuit312.7 Oscillator Value Conditions on Device Start-up322.8 Unused I/Os322.9 Application Examples32FIGURE 2-4: Boost Converter Implementation32FIGURE 2-5: Single-Phase Synchronous Buck converter33FIGURE 2-6: Multiphase Synchronous Buck converter33FIGURE 2-7: Interleaved PFC34FIGURE 2-8: BEMF voltage measured using the ADC Module343.0 CPU353.1 Registers353.2 Instruction Set353.3 Data Space Addressing353.4 Addressing Modes35FIGURE 3-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X CPU Block Diagram363.5 Programmer’s Model37TABLE 3-1: Programmer’s Model Register Descriptions37FIGURE 3-2: Programmer’s Model383.6 CPU Resources393.7 CPU Control Registers40Register 3-1: SR: CPU Status Register40Register 3-2: CORCON: Core Control Register423.8 Arithmetic Logic Unit (ALU)443.9 DSP Engine (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only)44TABLE 3-2: DSP Instructions Summary444.0 Memory Organization454.1 Program Address Space45FIGURE 4-1: Program Memory Map for dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X and PIC24EP32GP/MC20X Devices45FIGURE 4-2: Program Memory Map for dsPIC33EP64GP50X, dsPIC33EP64MC20X/50X and PIC24EP64GP/MC20X Devices46FIGURE 4-3: Program Memory Map for dsPIC33EP128GP50X, dsPIC33EP128MC20X/50X and PIC24EP128GP/MC20X Devices47FIGURE 4-4: Program Memory Map for dsPIC33EP256GP50X, dsPIC33EP256MC20X/50X and PIC24EP256GP/MC20X Devices48FIGURE 4-5: Program Memory Map for dsPIC33EP512GP50X, dsPIC33EP512MC20X/50X and PIC24EP512GP/MC20X Devices49FIGURE 4-6: Program Memory Organization504.2 Data Address Space51FIGURE 4-7: Data Memory Map for dsPIC33EP32MC20X/50X and dsPIC33EP32GP50X Devices52FIGURE 4-8: Data Memory Map for dsPIC33EP64MC20X/50X and dsPIC33EP64GP50X Devices53FIGURE 4-9: Data Memory Map for dsPIC33EP128MC20X/50X and dsPIC33EP128GP50X Devices54FIGURE 4-10: Data Memory Map for dsPIC33EP256MC20X/50X and dsPIC33EP256GP50X Devices55FIGURE 4-11: Data Memory Map for dsPIC33EP512MC20X/50X and dsPIC33EP512GP50X Devices56FIGURE 4-12: Data Memory Map for PIC24EP32GP/MC20X/50X Devices57FIGURE 4-13: Data Memory Map for PIC24EP64GP/MC20X/50X Devices58FIGURE 4-14: Data Memory Map for PIC24EP128GP/MC20X/50X Devices59FIGURE 4-15: Data Memory Map for PIC24EP256GP/MC20X/50X Devices60FIGURE 4-16: Data Memory Map for PIC24EP512GP/MC20X/50X Devices614.3 Memory Resources624.4 Special Function Register Maps63TABLE 4-1: CPU Core Register Map for dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only63TABLE 4-2: CPU Core Register Map for PIC24EPXXXGP/MC20X Devices Only65TABLE 4-3: Interrupt Controller Register Map for PIC24EPXXXGP20X Devices Only66TABLE 4-4: Interrupt Controller Register Map for PIC24EPXXXMC20X Devices Only67TABLE 4-5: Interrupt Controller Register Map for dsPIC33EPXXXGP50X Devices Only69TABLE 4-6: Interrupt Controller Register Map for dsPIC33EPXXXMC20X Devices Only71TABLE 4-7: Interrupt Controller Register Map for dsPIC33EPXXXMC50X Devices Only73TABLE 4-8: Timer1 through Timer5 Register Map75TABLE 4-9: Input Capture 1 through Input Capture 4 Register Map76TABLE 4-10: Output Compare 1 through Output Compare 4 Register Map77TABLE 4-11: PTG Register Map78TABLE 4-12: PWM Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only79TABLE 4-13: PWM Generator 1 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only79TABLE 4-14: PWM Generator 2 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only80TABLE 4-15: PWM Generator 3 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only80TABLE 4-16: QEI1 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only81TABLE 4-17: I2C1 and I2C2 Register Map82TABLE 4-18: UART1 and UART2 Register Map82TABLE 4-19: SPI1 and SPI2 Register Map83TABLE 4-20: ADC1 Register Map84TABLE 4-21: ECAN1 Register Map When WIN (C1CTRL1<0>) = 0 or 1 FOR dsPIC33EPXXXMC/GP50X Devices Only85TABLE 4-22: ECAN1 Register Map When WIN (C1CTRL1<0>) = 0 For dsPIC33EPXXXMC/GP50X Devices Only85TABLE 4-23: ECAN1 Register Map When WIN (C1CTRL1<0>) = 1 For dsPIC33EPXXXMC/GP50X Devices Only86TABLE 4-24: CRC Register Map88TABLE 4-25: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC202/502 and PIC24EPXXXGP/MC202 Devices Only88TABLE 4-26: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC203/503 and PIC24EPXXXGP/MC203 Devices Only88TABLE 4-27: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC204/504 and PIC24EPXXXGP/MC204 Devices Only89TABLE 4-28: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC206/506 and PIC24EPXXXGP/MC206 Devices Only89TABLE 4-29: Peripheral Pin Select Input Register Map for PIC24EPXXXMC20X Devices Only90TABLE 4-30: Peripheral Pin Select Input Register Map for PIC24EPXXXGP20X Devices Only90TABLE 4-31: Peripheral Pin Select Input Register Map for dsPIC33EPXXXGP50X Devices Only91TABLE 4-32: Peripheral Pin Select Input Register Map for dsPIC33EPXXXMC50X Devices Only91TABLE 4-33: Peripheral Pin Select Input Register Map for dsPIC33EPXXXMC20X Devices Only92TABLE 4-34: NVM Register Map93TABLE 4-35: System Control Register Map93TABLE 4-36: Reference Clock Register Map93TABLE 4-37: PMD Register Map for PIC24EPXXXGP20X Devices Only94TABLE 4-38: PMD Register Map for PIC24EPXXXMC20X Devices Only94TABLE 4-39: PMD Register Map for dsPIC33EPXXXGP50X Devices Only95TABLE 4-40: PMD Register Map for dsPIC33EPXXXMC50X Devices Only95TABLE 4-41: PMD Register Map for dsPIC33EPXXXMC20X Devices Only96TABLE 4-42: Op Amp/Comparator Register Map97TABLE 4-43: CTMU Register Map97TABLE 4-44: JTAG INTERFACE Register Map97TABLE 4-45: DMAC Register Map98TABLE 4-46: PORTA Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only99TABLE 4-47: PORTB Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only99TABLE 4-48: PORTC Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only99TABLE 4-49: PORTD Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only100TABLE 4-50: PORTE Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only100TABLE 4-51: PORTF Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only100TABLE 4-52: PORTG Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only101TABLE 4-53: PORTA Register Map For PIC24EPXXXGP/MC204 and dsPIC33EPXXXGP/MC204/504 Devices Only102TABLE 4-54: PORTB Register Map For PIC24EPXXXGP/MC204 and dsPIC33EPXXXGP/MC204/504 Devices Only102TABLE 4-55: PORTC Register Map For PIC24EPXXXGP/MC204 and dsPIC33EPXXXGP/MC204/504 Devices Only102TABLE 4-56: PORTA Register Map For PIC24EPXXXGP/MC203 and dsPIC33EPXXXGP/MC203/503 Devices Only103TABLE 4-57: PORTB Register Map For PIC24EPXXXGP/MC203 and dsPIC33EPXXXGP/MC203/503 Devices Only103TABLE 4-58: PORTC Register Map For PIC24EPXXXGP/MC203 and dsPIC33EPXXXGP/MC203/503 Devices Only103TABLE 4-59: PORTA Register Map For PIC24EPXXXGP/MC202 and dsPIC33EPXXXGP/MC202/502 Devices Only104TABLE 4-60: PORTB Register Map For PIC24EPXXXGP/MC202 and dsPIC33EPXXXGP/MC202/502 Devices Only104EXAMPLE 4-1: Extended Data Space (EDS) Read Address Generation105EXAMPLE 4-2: Extended Data Space (EDS) Write Address Generation106EXAMPLE 4-3: Paged Data Memory Space107TABLE 4-61: Overflow and Underflow Scenarios at Page 0, EDS and PSV Space Boundaries(2,3,4)108FIGURE 4-17: EDS Memory Map109TABLE 4-62: Data Memory Bus Arbiter Priority110FIGURE 4-18: Arbiter Architecture110FIGURE 4-19: CALL Stack Frame1114.5 Instruction Addressing Modes112TABLE 4-63: Fundamental Addressing Modes Supported1124.6 Modulo Addressing (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only)114FIGURE 4-20: Modulo Addressing Operation Example1144.7 Bit-Reversed Addressing (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only)115FIGURE 4-21: Bit-Reversed Addressing Example116TABLE 4-64: Bit-Reversed Addressing Sequence (16-Entry)1164.8 Interfacing Program and Data Memory Spaces117TABLE 4-65: Program Space Address Construction117FIGURE 4-22: Data Access from Program Space Address Generation117FIGURE 4-23: Accessing Program Memory with Table Instructions1185.0 Flash Program Memory1195.1 Table Instructions and Flash Programming119FIGURE 5-1: Addressing for Table Registers1195.2 RTSP Operation1205.3 Programming Operations1205.4 Flash Memory Resources1205.5 Control Registers120Register 5-1: NVMCON: Nonvolatile Memory (NVM) Control Register121Register 5-2: NVMADRH: Nonvolatile Memory Address Register High122Register 5-3: NVMADRL: Nonvolatile Memory Address Register Low122Register 5-4: NVMKEY: Nonvolatile Memory Key1226.0 Resets123FIGURE 6-1: Reset System Block Diagram1236.1 Reset Resources124Register 6-1: RCON: Reset Control Register(1)1257.0 Interrupt Controller1277.1 Interrupt Vector Table1277.2 Reset Sequence127FIGURE 7-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X Interrupt Vector Table128TABLE 7-1: Interrupt Vector Details1297.3 Interrupt Resources1317.4 Interrupt Control and Status Registers131Register 7-1: SR: CPU Status Register(1)132Register 7-2: CORCON: Core Control Register(1)133Register 7-3: INTCON1: Interrupt Control Register 1134Register 7-4: INTCON2: Interrupt Control Register 2136Register 7-5: INTCON3: Interrupt Control Register 3137Register 7-6: INTCON4: Interrupt Control Register 4137Register 7-7: INTTREG: Interrupt Control and Status Register1388.0 Direct Memory Access (DMA)139FIGURE 8-1: DMA Controller Module139TABLE 8-1: DMA Channel to Peripheral Associations140FIGURE 8-2: DMA Controller Block Diagram1418.1 DMA Resources1418.2 DMAC Registers141Register 8-1: DMAxCON: DMA Channel x Control Register142Register 8-2: DMAxREQ: DMA Channel x IRQ Select Register143Register 8-3: DMAxSTAH: DMA Channel x Start Address Register A (High)144Register 8-4: DMAxSTAL: DMA Channel x Start Address Register A (Low)144Register 8-5: DMAxSTBH: DMA Channel x Start Address Register B (High)145Register 8-6: DMAxSTBL: DMA Channel x Start Address Register B (Low)145Register 8-7: DMAxPAD: DMA Channel x Peripheral Address Register(1)146Register 8-8: DMAxCNT: DMA Channel x Transfer Count Register(1)146Register 8-9: DSADRH: DMA Most Recent RAM High Address Register147Register 8-10: DSADRL: DMA Most Recent RAM Low Address Register147Register 8-11: DMAPWC: DMA Peripheral Write Collision Status Register148Register 8-12: DMARQC: DMA Request Collision Status Register149Register 8-13: DMALCA: DMA Last Channel Active Status Register150Register 8-14: DMAPPS: DMA Ping-Pong Status Register1519.0 Oscillator Configuration153FIGURE 9-1: Oscillator System Diagram1539.1 CPU Clocking System154EQUATION 9-1: Device Operating Frequency154FIGURE 9-2: PLL Block Diagram154EQUATION 9-2: Fpllo Calculation154EQUATION 9-3: Fvco Calculation154TABLE 9-1: Configuration Bit Values for Clock Selection1559.2 Oscillator Resources1559.3 Oscillator Control Registers156Register 9-1: OSCCON: Oscillator Control Register(1)156Register 9-2: CLKDIV: Clock Divisor Register158Register 9-3: PLLFBD: PLL Feedback Divisor Register160Register 9-4: OSCTUN: FRC Oscillator Tuning Register161Register 9-5: REFOCON: Reference Oscillator Control Register16210.0 Power-Saving Features16310.1 Clock Frequency and Clock Switching16310.2 Instruction-Based Power-Saving Modes163EXAMPLE 10-1: PWRSAV Instruction Syntax16310.3 Doze Mode16510.4 Peripheral Module Disable16510.5 Power-Saving Resources165Register 10-1: PMD1: Peripheral Module Disable Control Register 1166Register 10-2: PMD2: Peripheral Module Disable Control Register 2168Register 10-3: PMD3: Peripheral Module Disable Control Register 3169Register 10-4: PMD4: Peripheral Module Disable Control Register 4169Register 10-5: PMD6: Peripheral Module Disable control Register 6170Register 10-6: PMD7: Peripheral Module Disable control Register 717111.0 I/O Ports17311.1 Parallel I/O (PIO) Ports173FIGURE 11-1: Block Diagram of a Typical Shared Port Structure17311.2 Configuring Analog and Digital Port Pins17411.3 Input Change Notification (ICN)174EXAMPLE 11-1: Port Write/Read Example17411.4 Peripheral Pin Select (PPS)175FIGURE 11-2: Remappable Input for U1RX176EXAMPLE 11-2: Connecting IC1 to the HOME1 QEI1 Digital Filter Input on Pin 43 of the dsPIC33EPXXXMC206 Device176TABLE 11-1: Selectable Input Sources (Maps Input to Function)177TABLE 11-2: Input Pin Selection for Selectable Input sources178FIGURE 11-3: Multiplexing Remappable Output for RPn180TABLE 11-3: Output Selection for Remappable Pins (RPn)18011.5 I/O Helpful Tips18111.6 I/O Ports Resources18211.7 Peripheral Pin Select Registers183Register 11-1: RPINR0: Peripheral Pin Select Input Register 0183Register 11-2: RPINR1: Peripheral Pin Select Input Register 1184Register 11-3: RPINR3: Peripheral Pin Select Input Register 3184Register 11-4: RPINR7: Peripheral Pin Select Input Register 7185Register 11-5: RPINR8: Peripheral Pin Select Input Register 8186Register 11-6: RPINR11: Peripheral Pin Select Input Register 11187Register 11-7: RPINR12: Peripheral Pin Select Input Register 12 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)188Register 11-8: RPINR14: Peripheral Pin Select Input Register 14 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)189Register 11-9: RPINR15: Peripheral Pin Select Input Register 15 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)190Register 11-10: RPINR18: Peripheral Pin Select Input Register 18191Register 11-11: RPINR19: Peripheral Pin Select Input Register 19191Register 11-12: RPINR22: Peripheral Pin Select Input Register 22192Register 11-13: RPINR23: Peripheral Pin Select Input Register 23193Register 11-14: RPINR26: Peripheral Pin Select Input Register 26 (dsPIC33EPXXXGP/MC50X Devices Only)193Register 11-15: RPINR37: Peripheral Pin Select Input Register 37 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)194Register 11-16: RPINR38: Peripheral Pin Select Input Register 38 (dsPIC33EPXXXMC20X and PIC24EPXXXMC20X Devices Only)195Register 11-17: RPINR39: Peripheral Pin Select Input Register 39 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)196Register 11-18: RPOR0: Peripheral Pin Select Output Register 0197Register 11-19: RPOR1: Peripheral Pin Select Output Register 1197Register 11-20: RPOR2: Peripheral Pin Select Output Register 2198Register 11-21: RPOR3: Peripheral Pin Select Output Register 3198Register 11-22: RPOR4: Peripheral Pin Select Output Register 4199Register 11-23: RPOR5: Peripheral Pin Select Output Register 5199Register 11-24: RPOR6: Peripheral Pin Select Output Register 6200Register 11-25: RPOR7: Peripheral Pin Select Output Register 7200Register 11-26: RPOR8: Peripheral Pin Select Output Register 8201Register 11-27: RPOR9: Peripheral Pin Select Output Register 920112.0 Timer1203TABLE 12-1: Timer Mode Settings203FIGURE 12-1: 16-bit Timer1 Module Block Diagram20312.1 Timer1 Resources20412.2 Timer1 Control Register205Register 12-1: T1CON: Timer1 Control Register20513.0 Timer2/3 and Timer4/5207FIGURE 13-1: Type B Timer block Diagram (x = 2 and 4)208FIGURE 13-2: Type C Timer Block Diagram (x = 3 and 5)208FIGURE 13-3: Type B/Type C Timer Pair Block Diagram (32-Bit Timer)20913.1 Timerx/y Resources20913.2 Timer Control Registers210Register 13-1: TxCON: (TIMER2 and Timer4) Control Register210Register 13-2: TyCON: (TIMER3 and TIMER5) Control Register21114.0 Input Capture213FIGURE 14-1: Input Capture x Module Block Diagram21314.1 Input Capture Resources21414.2 Input Capture Registers215Register 14-1: ICxCON1: Input Capture X Control Register 1215Register 14-2: ICxCON2: Input Capture X Control Register 221615.0 Output Compare219FIGURE 15-1: Output Compare x Module Block Diagram21915.1 Output Compare Resources22015.2 Output Compare Control Registers221Register 15-1: OCxCON1: Output Compare x Control Register 1221Register 15-2: OCxCON2: Output Compare x Control Register 222316.0 High-Speed PWM Module (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X Devices Only)22516.1 PWM Faults225EXAMPLE 16-1: PWMx Write-Protected Register Unlock Sequence226FIGURE 16-1: High-Speed PWMx Module Architectural Overview227FIGURE 16-2: High-Speed PWMx Module Register Interconnection Diagram22816.2 PWM Resources22916.3 PWMx Control Registers230Register 16-1: PTCON: PWMx Time Base Control Register230Register 16-2: PTCON2: PWMx Primary Master Clock Divider Select Register 2232Register 16-3: PTPER: PWMx Primary Master Time Base Period Register233Register 16-4: SEVTCMP: PWMx Primary Special Event Compare Register233Register 16-5: CHOP: PWMx Chop Clock Generator Register234Register 16-6: MDC: PWMx Master Duty Cycle Register234Register 16-7: PWMCONx: PWMx Control Register235Register 16-8: PDCx: PWMx Generator Duty Cycle Register237Register 16-9: PHASEx: PWMx Primary Phase-Shift Register237Register 16-10: DTRx: PWMx Dead-Time Register238Register 16-11: ALTDTRx: PWMx Alternate Dead-Time Register238Register 16-12: TRGCONx: PWMx Trigger Control Register239Register 16-13: IOCONx: PWMx I/O Control Register(2)240Register 16-14: TRIGx: PWMx Primary Trigger Compare Value Register242Register 16-15: FCLCONx: PWMx Fault Current-Limit Control Register(1)243Register 16-16: LEBCONx: PWMx Leading-Edge Blanking Control Register245Register 16-17: LEBDLYx: PWMx Leading-Edge Blanking Delay Register246Register 16-18: AUXCONx: PWMx Auxiliary Control Register24717.0 Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)249FIGURE 17-1: QEI Block Diagram25017.1 QEI Resources25117.2 QEI Control Registers252Register 17-1: QEI1CON: QEI1 Control Register252Register 17-2: QEI1IOC: QEI1 I/O Control Register254Register 17-3: QEI1STAT: QEI1 Status register256Register 17-4: POS1CNTH: Position Counter 1 High Word Register258Register 17-5: POS1CNTL: Position Counter 1 Low Word Register258Register 17-6: POS1HLD: Position Counter 1 Hold Register258Register 17-7: VEL1CNT: Velocity Counter 1 Register259Register 17-8: INDX1CNTH: Index Counter 1 High Word Register259Register 17-9: INDX1CNTL: Index Counter 1 Low Word Register259Register 17-10: INDX1HLD: Index Counter 1 Hold Register260Register 17-11: QEI1ICH: QEI1 Initialization/Capture High Word Register260Register 17-12: QEI1ICL: QEI1 Initialization/Capture Low Word Register260Register 17-13: QEI1LECH: qei1 Less Than or Equal Compare High Word Register261Register 17-14: QEI1LECL: qei1 Less Than or Equal Compare Low Word Register261Register 17-15: QEI1GECH: QEI1 Greater Than or Equal Compare High Word Register262Register 17-16: QEI1GECL: QEI1 Greater Than or Equal Compare Low Word Register262Register 17-17: INT1TMRH: Interval 1 Timer High Word Register263Register 17-18: INT1TMRL: Interval 1 Timer Low Word Register263Register 17-19: INT1HLDH: Interval 1 Timer Hold High Word Register264Register 17-20: INT1HLDL: Interval 1 Timer Hold Low Word Register26418.0 Serial Peripheral Interface (SPI)265FIGURE 18-1: SPIx Module Block Diagram26618.1 SPI Helpful Tips26718.2 SPI Resources26718.3 SPIx Control Registers268Register 18-1: SPIxSTAT: SPIx Status and Control Register268Register 18-2: SPIxCON1: SPIx Control Register 1270Register 18-3: SPIxCON2: SPIx Control Register 227219.0 Inter-Integrated Circuit™ (I2C™)273FIGURE 19-1: I2Cx Block Diagram (x = 1 or 2)27419.1 I2C Resources27519.2 I2C Control Registers276Register 19-1: I2CxCON: I2Cx Control Register276Register 19-2: I2CxSTAT: I2Cx Status Register278Register 19-3: I2CxMSK: I2Cx Slave Mode Address Mask Register28020.0 Universal Asynchronous Receiver Transmitter (UART)281FIGURE 20-1: UARTx Simplified Block Diagram28120.1 UART Helpful Tips28220.2 UART Resources28220.3 UARTx Control Registers283Register 20-1: UxMODE: UARTx Mode Register283Register 20-2: UxSTA: UARTx Status and Control Register28521.0 Enhanced CAN (ECAN™) Module (dsPIC33EPXXXGP/ MC50X Devices Only)28721.1 Overview287FIGURE 21-1: ECAN™ Module Block Diagram28821.2 Modes of Operation28921.3 ECAN Resources28921.4 ECAN Control Registers290Register 21-1: CxCTRL1: ECANx CONTROL REGISTER 1290Register 21-2: CxCTRL2: ECANx Control Register 2291Register 21-3: CxVEC: ECANx Interrupt Code Register292Register 21-4: CxFCTRL: ECANx FIFO Control Register293Register 21-5: CxFIFO: ECANx FIFO Status Register294Register 21-6: CxINTF: ECANx Interrupt Flag Register295Register 21-7: CxINTE: ECANx Interrupt Enable Register297Register 21-8: CxEC: ECANx Transmit/Receive Error Count Register298Register 21-9: CxCFG1: ECANx Baud Rate Configuration Register 1298Register 21-10: CxCFG2: ECANx Baud Rate Configuration Register 2299Register 21-11: CxFEN1: ECANx Acceptance Filter Enable Register 1300Register 21-12: CxBUFPNT1: ECANx Filter 0-3 Buffer Pointer Register 1300Register 21-13: CxBUFPNT2: ECANx Filter 4-7 Buffer Pointer Register 2301Register 21-14: CxBUFPNT3: ECANx Filter 8-11 Buffer Pointer Register 3301Register 21-15: CxBUFPNT4: ECANx Filter 12-15 Buffer Pointer Register 4302Register 21-16: CxRXFnSID: ECANx Acceptance Filter n Standard Identifier Register (n = 0-15)303Register 21-17: CxRXFnEID: ECANx Acceptance Filter n Extended Identifier Register (n = 0-15)304Register 21-18: CxFMSKSEL1: ECANx Filter 7-0 Mask Selection Register 1304Register 21-19: CxFMSKSEL2: ECANx Filter 15-8 Mask Selection Register 2305Register 21-20: CxRXMnSID: ECANx Acceptance Filter Mask n Standard Identifier Register (n = 0-2)306Register 21-21: CxRXMnEID: ECANx Acceptance Filter Mask n Extended Identifier Register (n = 0-2)306Register 21-22: CxRXFUL1: ECANx Receive Buffer Full Register 1307Register 21-23: CxRXFUL2: ECANx Receive Buffer Full Register 2307Register 21-24: CxRXOVF1: ECANx Receive Buffer Overflow Register 1308Register 21-25: CxRXOVF2: ECANx Receive Buffer Overflow Register 2308Register 21-26: CxTRmnCON: ECANx TX/RX Buffer mn Control Register (m = 0,2,4,6; n = 1,3,5,7)30921.5 ECAN Message Buffers31022.0 Charge Time Measurement Unit (CTMU)315FIGURE 22-1: CTMU Block Diagram31622.1 CTMU Resources31622.2 CTMU Control Registers317Register 22-1: CTMUCON1: CTMU Control Register 1317Register 22-2: CTMUCON2: CTMU Control Register 2318Register 22-3: CTMUICON: CTMU Current Control Register31923.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC)32123.1 Key Features321FIGURE 23-1: ADC Module Block Diagram with Connection Options for ANx pins and Op Amps322FIGURE 23-2: ADC Conversion Clock Period Block Diagram32323.2 ADC Helpful Tips32423.3 ADC Resources32423.4 ADC Control Registers325Register 23-1: AD1CON1: ADC1 Control Register 1325Register 23-2: AD1CON2: ADC1 Control Register 2327Register 23-3: AD1CON3: ADC1 Control Register 3329Register 23-4: AD1CON4: ADC1 Control Register 4330Register 23-5: AD1CHS123: ADC1 Input Channel 1, 2, 3 Select Register331Register 23-6: AD1CHS0: ADC1 Input Channel 0 Select Register333Register 23-7: AD1CSSH: ADC1 Input Scan Select Register High(1)335Register 23-8: AD1CSSL: ADC1 Input Scan Select Register Low(1,2)33624.0 Peripheral Trigger Generator (PTG) Module33724.1 Module Introduction337FIGURE 24-1: PTG Block Diagram33824.2 PTG Resources33924.3 PTG Control Registers340Register 24-1: PTGCST: PTG control/Status Register340Register 24-2: PTGCON: PTG control Register342Register 24-3: PTGBTE: PTG Broadcast Trigger Enable Register(1,2)343Register 24-4: PTGT0LIM: PTG Timer0 Limit Register(1)345Register 24-5: PTGT1LIM: PTG Timer1 Limit Register(1)345Register 24-6: PTGSDLIM: PTG Step Delay Limit Register(1,2)346Register 24-7: PTGC0LIM: PTG Counter 0 Limit Register(1)346Register 24-8: PTGC1LIM: PTG Counter 1 Limit Register(1)347Register 24-9: PTGHOLD: PTG Hold Register(1)347Register 24-10: PTGADJ: PTG Adjust Register(1)348Register 24-11: PTGL0: PTG Literal 0 Register(1)348Register 24-12: PTGQPTR: PTG Step Queue Pointer Register(1)349Register 24-13: PTGQUEx: PTG Step Queue Register x (x = 0-7)(1,3)34924.4 Step Commands and Format350TABLE 24-1: PTG Step Command Format350TABLE 24-1: PTG STEP Command Format (continued)351TABLE 24-1: PTG STEP Command Format (continued)352TABLE 24-2: PTG Output Descriptions35325.0 Op Amp/Comparator Module355FIGURE 25-1: Op Amp/Comparator x Module Block Diagram (Modules 1, 2 and 3)355FIGURE 25-2: Comparator Module Block Diagram (Module 4)356FIGURE 25-3: Op Amp/Comparator Voltage Reference Block Diagram356FIGURE 25-4: User-Programmable Blanking Function Block Diagram357FIGURE 25-5: Digital Filter Interconnect Block Diagram35725.1 Op Amp Application Considerations358FIGURE 25-6: Op Amp Configuration A35825.2 Op Amp/Comparator Resources359FIGURE 25-7: Op Amp Configuration B35925.3 Op Amp/Comparator Registers360Register 25-1: CMSTAT: Op Amp/Comparator Status Register360Register 25-2: CMxCON: Comparator x Control Register (x = 1, 2 or 3)362Register 25-3: CM4CON: Comparator 4 Control Register364Register 25-4: CMxMSKSRC: Comparator x Mask Source Select Control Register366Register 25-5: CMxMSKCON: Comparator x Mask Gating Control Register368Register 25-6: CMxFLTR: Comparator x Filter Control Register370Register 25-7: CVRCON: Comparator Voltage Reference Control Register37126.0 Programmable Cyclic Redundancy Check (CRC) Generator373FIGURE 26-1: CRC Block Diagram373FIGURE 26-2: CRC Shift Engine Detail37426.1 Overview374TABLE 26-1: CRC SETUP Examples FOR 16 and 32-bit polynomial37426.2 Programmable CRC Resources37426.3 Programmable CRC Registers375Register 26-1: CRCCON1: CRC Control Register 1375Register 26-2: CRCCON2: CRC Control Register 2376Register 26-3: CRCXORH: CRC XOR Polynomial HIGH Register377Register 26-4: CRCXORL: CRC XOR Polynomial Low Register37727.0 Special Features37927.1 Configuration Bits379TABLE 27-1: Configuration Byte Register Map380TABLE 27-2: Configuration Bits Description381Register 27-1: DEVID: Device ID Register383Register 27-2: DEVREV: Device Revision Register38327.2 User ID Words384TABLE 27-3: User ID Words Register Map38427.3 On-Chip Voltage Regulator384FIGURE 27-1: Connections for the On-Chip Voltage Regulator(1,2,3)38427.4 Brown-out Reset (BOR)38427.5 Watchdog Timer (WDT)385FIGURE 27-2: WDT Block diagram38527.6 JTAG Interface38627.7 In-Circuit Serial Programming38627.8 In-Circuit Debugger38627.9 Code Protection and CodeGuard™ Security38628.0 Instruction Set Summary387TABLE 28-1: Symbols used in Opcode Descriptions388TABLE 28-2: Instruction Set Overview39029.0 Development Support39729.1 MPLAB X Integrated Development Environment Software39729.2 MPLAB XC Compilers39829.3 MPASM Assembler39829.4 MPLINK Object Linker/ MPLIB Object Librarian39829.5 MPLAB Assembler, Linker and Librarian for Various Device Families39829.6 MPLAB X SIM Software Simulator39929.7 MPLAB REAL ICE In-Circuit Emulator System39929.8 MPLAB ICD 3 In-Circuit Debugger System39929.9 PICkit 3 In-Circuit Debugger/ Programmer39929.10 MPLAB PM3 Device Programmer39929.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits40029.12 Third-Party Development Tools40030.0 Electrical Characteristics40130.1 DC Characteristics402TABLE 30-1: Operating MIPS vs. Voltage402TABLE 30-2: Thermal Operating Conditions402TABLE 30-3: Thermal Packaging Characteristics402TABLE 30-4: DC Temperature and Voltage specifications403TABLE 30-5: Filter Capacitor (Cefc) Specifications403TABLE 30-6: DC Characteristics: Operating Current (Idd)404TABLE 30-7: DC Characteristics: Idle Current (iidle)405TABLE 30-8: DC Characteristics: Power-Down Current (Ipd)406TABLE 30-9: DC Characteristics: Watchdog Timer Delta Current (DIwdt)(1)407TABLE 30-10: DC Characteristics: doze Current (Idoze)407TABLE 30-11: DC Characteristics: I/O Pin Input Specifications408TABLE 30-12: DC Characteristics: I/O Pin Output Specifications411TABLE 30-13: Electrical Characteristics: BOR411TABLE 30-14: DC Characteristics: Program Memory41230.2 AC Characteristics and Timing Parameters413TABLE 30-15: Temperature and Voltage Specifications – AC413FIGURE 30-1: Load Conditions for Device Timing Specifications413TABLE 30-16: Capacitive Loading Requirements on Output Pins413FIGURE 30-2: External Clock Timing414TABLE 30-17: External Clock Timing Requirements414TABLE 30-18: PLL Clock Timing Specifications415TABLE 30-19: Internal FRC Accuracy415TABLE 30-20: Internal LPRC accuracy415FIGURE 30-3: I/O Timing Characteristics416TABLE 30-21: I/O Timing Requirements416FIGURE 30-4: BOR and Master Clear Reset Timing Characteristics416TABLE 30-22: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements417FIGURE 30-5: Timer1-Timer5 External Clock Timing Characteristics418TABLE 30-23: Timer1 External Clock Timing Requirements(1)418TABLE 30-24: Timer2 and Timer4 (Type B Timer) External Clock Timing Requirements419TABLE 30-25: Timer3 and Timer5 (Type C Timer) External Clock Timing Requirements419FIGURE 30-6: INPUT CAPTURE x (ICx) TIMING Characteristics420Table 30-26: Input Capture x Module Timing Requirements420FIGURE 30-7: Output Compare x Module (OCx) Timing Characteristics421TABLE 30-27: Output Compare x Module timing requirements421FIGURE 30-8: OCx/PWMx Module Timing Characteristics421TABLE 30-28: OCx/PWMx MODE Timing Requirements421FIGURE 30-9: High-Speed PWMx Module Fault Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)422FIGURE 30-10: High-Speed PWMx Module Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)422TABLE 30-29: High-Speed PWMx Module Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)422FIGURE 30-11: TimerQ (QEI Module) External Clock Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)423TABLE 30-30: QEI module External Clock Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)423FIGURE 30-12: QEA/QEB Input Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)424TABLE 30-31: Quadrature Decoder Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)424FIGURE 30-13: QEI Module Index Pulse Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)425TABLE 30-32: QEI INDEX PULSE Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)425TABLE 30-33: SPI2 Maximum Data/Clock Rate Summary426FIGURE 30-14: SPI2 MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS426FIGURE 30-15: SPI2 MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS427TABLE 30-34: SPI2 Master Mode (Half-Duplex, Transmit Only) Timing Requirements427FIGURE 30-16: SPI2 MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS428TABLE 30-35: SPI2 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements428FIGURE 30-17: SPI2 MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS429TABLE 30-36: SPI2 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements429FIGURE 30-18: SPI2 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS430TABLE 30-37: SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements431FIGURE 30-19: SPI2 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS432TABLE 30-38: SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements433FIGURE 30-20: SPI2 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS434TABLE 30-39: SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements435FIGURE 30-21: SPI2 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS436TABLE 30-40: SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements437TABLE 30-41: SPI1 Maximum Data/Clock Rate Summary438FIGURE 30-22: SPI1 MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS438FIGURE 30-23: SPI1 MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS439TABLE 30-42: SPI1 Master Mode (Half-Duplex, Transmit Only) Timing Requirements439FIGURE 30-24: SPI1 MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS440TABLE 30-43: SPI1 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements440FIGURE 30-25: SPI1 MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS441TABLE 30-44: SPI1 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements441FIGURE 30-26: SPI1 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS442TABLE 30-45: SPI1 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements443FIGURE 30-27: SPI1 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS444TABLE 30-46: SPI1 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements445FIGURE 30-28: SPI1 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS446TABLE 30-47: SPI1 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements447FIGURE 30-29: SPI1 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS448TABLE 30-48: SPI1 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements449FIGURE 30-30: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)450FIGURE 30-31: I2Cx Bus Data Timing Characteristics (Master mode)450TABLE 30-49: I2Cx Bus Data Timing Requirements (Master Mode)451FIGURE 30-32: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)452FIGURE 30-33: I2Cx Bus Data Timing Characteristics (slave mode)452TABLE 30-50: I2Cx Bus Data Timing Requirements (Slave Mode)453FIGURE 30-34: ECANx Module I/O Timing Characteristics454TABLE 30-51: ECANx Module I/O Timing Requirements454FIGURE 30-35: UARTx Module I/O Timing Characteristics454TABLE 30-52: UARTx Module I/O Timing Requirements454TABLE 30-53: Op Amp/Comparator Specifications455TABLE 30-54: Op Amp/Comparator Voltage Reference Settling Time Specifications457TABLE 30-55: Op Amp/Comparator Voltage Reference Specifications457TABLE 30-56: CTMU Current Source Specifications458TABLE 30-57: ADC Module Specifications459TABLE 30-58: ADC Module Specifications (12-bit Mode)460TABLE 30-59: ADC Module Specifications (10-bit Mode)461FIGURE 30-36: ADC Conversion (12-bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000, SSRCG = 0)462TABLE 30-60: ADC Conversion (12-bit Mode) Timing Requirements463FIGURE 30-37: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 0, ssrc<2:0> = 000, SSRCG = 0)464FIGURE 30-38: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 1, ssrc<2:0> = 111, SSRCG = 0, SAMC<4:0> = 00010)464TABLE 30-61: ADC CONVERSION (10-bit mode) TIMING Requirements465TABLE 30-62: DMA Module Timing Requirements46531.0 High-Temperature Electrical Characteristics46731.1 High-Temperature DC Characteristics468TABLE 31-1: Operating MIPS vs. Voltage468TABLE 31-2: Thermal Operating Conditions468TABLE 31-3: DC Temperature and Voltage Specifications468TABLE 31-4: DC Characteristics: Power-down Current (Ipd)469TABLE 31-5: DC Characteristics: IDLE CURRENT (Iidle)469TABLE 31-6: DC Characteristics: Operating Current (Idd)469TABLE 31-7: DC Characteristics: Doze Current (Idoze)469TABLE 31-8: DC Characteristics: I/O Pin Output Specifications47031.2 AC Characteristics and Timing Parameters471TABLE 31-9: Temperature and Voltage Specifications – AC471FIGURE 31-1: Load Conditions for Device Timing Specifications471TABLE 31-10: PLL Clock Timing Specifications471TABLE 31-11: Internal RC accuracy472TABLE 31-12: ADC Module Specifications (12-bit Mode)473TABLE 31-13: ADC Module Specifications (10-bit Mode)47332.0 DC and AC Device Characteristics Graphs475FIGURE 32-1: Voh – 4x Driver Pins475FIGURE 32-2: Voh – 8x Driver Pins475FIGURE 32-3: Vol – 4x Driver Pins475FIGURE 32-4: Vol – 8x Driver Pins475FIGURE 32-5: Typical Ipd Current @ Vdd = 3.3V476FIGURE 32-6: Typical/Maximum Idd Current @ Vdd = 3.3V476FIGURE 32-7: Typical Idoze Current @ Vdd = 3.3V476FIGURE 32-8: Typical Iidle Current @ Vdd = 3.3V476FIGURE 32-9: Typical FRC Frequency @ Vdd = 3.3V477FIGURE 32-10: Typical LPRC Frequency @ Vdd = 3.3V477FIGURE 32-11: Typical CTMU Temperature DIODE Forward Voltage47733.0 Packaging Information47933.1 Package Marking Information47933.1 Package Marking Information (Continued)48033.1 Package Marking Information (Continued)48133.2 Package Details482Appendix A: Revision History507TABLE A-1: Major Section Updates507TABLE A-2: Major Section Updates509TABLE A-3: Major Section Updates512TABLE A-4: Major Section Updates513TABLE A-5: Major Section Updates514TABLE A-6: Major Section Updates516INDEX517The Microchip Web Site525Customer Change Notification Service525Customer Support525Size: 8.98 MBPages: 530Language: EnglishOpen manual
