Data SheetTable of Contents1.0 Electrical Characteristics52.0 Typical Performance Curves9FIGURE 2-1: Undervoltage Lockout vs. Temperature.9FIGURE 2-2: Undervoltage Lockout Hysteresis vs. Temperature.9FIGURE 2-3: Input Quiescent Current vs. Temperature.9FIGURE 2-4: Shutdown Current vs. Temperature (MCP1631/MCP1631V).9FIGURE 2-5: Oscillator Input Threshold vs. Temperature.9FIGURE 2-6: Oscillator Disable Input Threshold vs. Temperature.9FIGURE 2-7: VEXT P-Channel Driver RDSON vs. Temperature.10FIGURE 2-8: VEXT N-Channel Driver RDSON vs. Temperature.10FIGURE 2-9: VEXT Rise Time vs. Temperature.10FIGURE 2-10: VEXT Fall Time vs. Temperature.10FIGURE 2-11: Amplifier A1 Offset Voltage vs. Temperature.10FIGURE 2-12: Amplifier A1 Output Voltage Low vs. Temperature.10FIGURE 2-13: Amplifier A1 Sink Current vs. Temperature.11FIGURE 2-14: Amplifier A1 Source Current vs. Temperature.11FIGURE 2-15: Amplifier A2 Offset Voltage vs. Temperature.11FIGURE 2-16: Amplifier A2 Output Voltage Low vs. Temperature.11FIGURE 2-17: Amplifier A2 Sink Current vs. Temperature.11FIGURE 2-18: Amplifier A2 Source Current vs. Temperature.11FIGURE 2-19: Amplifier A3 Offset Voltage vs. Temperature.12FIGURE 2-20: Amplifier A3 Output Voltage Low vs. Temperature.12FIGURE 2-21: Amplifier A3 Sink Current vs. Temperature.12FIGURE 2-22: Amplifier A3 Source Current vs. Temperature.12FIGURE 2-23: MCP1631 and MCP1631HV CS Maximum Voltage (V) vs. Temperature.12FIGURE 2-24: MCP1631V and MCP1631VHV VRAMP Max Voltage (V).12FIGURE 2-25: Overvoltage Threshold High (V) vs. Temperature.13FIGURE 2-26: Overvoltage Threshold Low (V) vs. Temperature.13FIGURE 2-27: Overvoltage Threshold Hysteresis (V) vs. Temperature.13FIGURE 2-28: Shutdown Input Voltage Threshold (V) vs. Temperature.13FIGURE 2-29: LDO Quiescent Current vs. Input Voltage.13FIGURE 2-30: LDO Quiescent Current vs. Junction Temperature.13FIGURE 2-31: LDO Output Voltage vs. Load Current.14FIGURE 2-32: LDO Dropout Voltage vs. Load Current.14FIGURE 2-33: LDO Load Regulation vs. Temperature.14FIGURE 2-34: LDO Line Regulation vs. Temperature.14FIGURE 2-35: LDO PSRR vs. Frequency.14FIGURE 2-36: LDO Output Noise vs. Frequency.143.0 Pin Descriptions15TABLE 3-1: pin function table153.1 Power Ground (PGND)153.2 Shutdown Input (SHDN)153.3 Oscillator Input (OSCIN)153.4 Oscillator Disable (OSCDIS)153.5 Overvoltage Input (OVIN)153.6 External Reference Voltage Input (VREF)153.7 Analog Ground (AGND)163.8 No Connection (NC)163.9 Input Voltage (VIN)163.10 Analog supply Input (AVDD_IN)163.11 Analog Supply Output (AVDD_OUT)163.12 Voltage Sense Input (VSIN)163.13 Current Sense Input (ISIN)163.14 Voltage Sense Output (VSOUT)163.15 Current Sense Output (ISOUT)163.16 Error Amplifier Output (COMP)163.17 Feedback (FB)163.18 Current Sense or Voltage Ramp (CS/VRAMP)163.19 Power VDD (PVDD)163.20 External Driver (VEXT)163.21 Exposed PAD 4x4 QFN (EP)164.0 Detailed Description174.1 Device Overview174.2 Pulse Width Modulator (PWM)174.3 VEXT MOSFET Driver174.4 Current Sense Amplifier (A2)174.5 Voltage Sense Amplifier (A3)174.6 Overvoltage Comparator(C2)174.7 Shutdown Input174.8 Protection175.0 Application Information195.1 Typical Applications195.2 Battery Charger Design Overview195.3 Programmable Single Ended Primary Inductive (SEPIC) Current Source195.4 Mixed Signal Design195.5 Safety Features195.6 OSC Disable Feature20FIGURE 5-1: +5V ac-dc or USB Input Application.20FIGURE 5-2: +5.5V to +16.0V Input.21FIGURE 5-3: Wide Range High Voltage Input.226.0 Packaging Information236.1 Package Marking Information (Not to Scale)23Size: 566 KBPages: 34Language: EnglishOpen manual
Data SheetTable of ContentsPreface5Introduction5Document Layout5Conventions Used in this Guide6Recommended Reading7The Microchip Web Site7Customer Support7Document Revision History7Chapter 1. Product Overview91.1 Introduction91.2 What is the MCP1631HV Multi-Chemistry Battery Charger Reference Design?101.3 What the MCP1631HV Multi-Chemistry Battery Charger Reference Design kit includes10Chapter 2. Installation and Operation112.1 Introduction112.2 Features112.3 Getting Started11Appendix A. Schematic and Layout17A.1 Introduction17A.2 Board – Schematic18A.3 Board – Top Silk Layer19A.4 Board – Bottom Silk Layer20A.5 Board – Top Metal Layer21A.6 Board – Mid1 Metal Layer22A.7 Board – Mid2 Metal Layer23A.8 Board – Bottom Metal Layer24Appendix B. Bill Of Materials (BOM)25Appendix C. Software27C.1 Device SOFTWARE Flowchart27C.2 Selected Software Constants and Definitions38C.3 PIC16F883 Port Usage41C.4 mikroElektronika’s mikroC™ Compiler Startup42C.5 MPLAB® and PICkit™ 2 Debugging Exercise43C.6 Lab Exercises44Appendix D. Design Example51D.1 Design Example51Worldwide Sales and Service54Size: 690 KBPages: 54Language: EnglishOpen manual
Data SheetTable of ContentsHigh-Performance RISC CPU:1Special Microcontroller Features:1Low-Power Features:1Peripheral Features:1Pin Diagrams – PIC16F882/883/886, 28-Pin PDIP, SOIC, SSOP3TABLE 1: 28-Pin PDIP, SOIC, SSOP Allocation Table (PIC16F882/883/886)4Pin Diagrams – PIC16F882/883/886, 28-Pin QFN5TABLE 2: 28-Pin QFN Allocation Table (PIC16F882/883/886)6Pin Diagrams – PIC16F884/887, 40-Pin PDIP7TABLE 3: 40-Pin PDIP Allocation Table (PIC16F884/887)8Pin Diagrams – PIC16F884/887, 44-Pin QFN9TABLE 4: 44-Pin QFN Allocation Table (PIC16F884/887)10Pin Diagrams – PIC16F884/887, 44-Pin TQFP11TABLE 5: 44-Pin TQFP Allocation Table (PIC16F884/887)12Most Current Data Sheet13Errata13Customer Notification System131.0 Device Overview15FIGURE 1-1: PIC16F882/883/886 Block Diagram16FIGURE 1-2: PIC16F884/PIC16F887 Block Diagram17TABLE 1-1: PIC16F882/883/886 Pinout Description18TABLE 1-2: PIC16F884/887 Pinout Description202.0 Memory Organization232.1 Program Memory Organization23FIGURE 2-1: Program Memory Map and Stack for the PIC16F88223FIGURE 2-2: Program Memory Map and Stack for the PIC16F883/PIC16F88423FIGURE 2-3: Program Memory Map and Stack for the PIC16F886/PIC16F887232.2 Data Memory Organization242.2.1 General Purpose Register File242.2.2 Special Function Registers24FIGURE 2-4: PIC16F882 Special Function Registers25FIGURE 2-5: PIC16F883/PIC16F884 Special Function Registers26FIGURE 2-6: PIC16F886/PIC16F887 Special Function Registers27TABLE 2-1: PIC16F882/883/884/886/887 Special Function Registers Summary Bank 028TABLE 2-2: PIC16F882/883/884/886/887 Special Function Registers Summary Bank 129TABLE 2-3: PIC16F882/883/884/886/887 Special Function Registers Summary Bank 230TABLE 2-4: PIC16F882/883/884/886/887 Special Function Registers Summary Bank 330Register Definitions: STATUS31Register 2-1: STATUS: STATUS Register31Register Definitions: Option Register32Register 2-2: OPTION_REG: OPTION Register32Register 2-3: INTCON: Interrupt Control Register33Register Definitions: PIE134Register 2-4: PIE1: Peripheral Interrupt Enable Register 134Register Definitions: PIE235Register 2-5: PIE2: Peripheral Interrupt Enable Register 235Register Definitions: PIR136Register 2-6: PIR1: Peripheral Interrupt Request Register 136Register Definitions: PIR237Register 2-7: PIR2: Peripheral Interrupt Request Register 237Register Definitions: PCON38Register 2-8: PCON: Power Control Register382.3 PCL and PCLATH39FIGURE 2-7: Loading of PC in Different Situations392.3.1 Modifying PCL392.3.2 Stack392.4 Indirect Addressing, INDF and FSR Registers39EXAMPLE 2-1: Indirect Addressing39FIGURE 2-8: Direct/Indirect Addressing PIC16F882/883/884/886/887403.0 I/O Ports413.1 PORTA and the TRISA Registers41EXAMPLE 3-1: Initializing PORTA41Register 3-1: PORTA: PORTA Register41Register 3-2: TRISA: PORTA Tri-State Register413.2 Additional Pin Functions423.2.1 ANSEL Register42Register 3-3: ANSEL: Analog Select Register423.2.2 Ultra Low-Power Wake-up43EXAMPLE 3-2: Ultra Low-Power Wake-up Initialization433.2.3 Pin Descriptions and Diagrams44FIGURE 3-1: Block Diagram of RA044FIGURE 3-2: Block Diagram of RA145FIGURE 3-3: Block Diagram of RA245FIGURE 3-4: Block Diagram of RA346FIGURE 3-5: Block Diagram of RA446FIGURE 3-6: Block Diagram of RA547FIGURE 3-7: Block Diagram of RA647FIGURE 3-8: Block Diagram of RA748TABLE 3-1: Summary of Registers Associated with PORTA483.3 PORTB and TRISB Registers49EXAMPLE 3-3: Initializing PORTB493.4 Additional PORTB Pin Functions493.4.1 ANSELH Register493.4.2 Weak Pull-Ups493.4.3 Interrupt-on-Change49Register 3-4: ANSELH: Analog Select High Register50Register 3-5: PORTB: PORTB Register50Register 3-6: TRISB: PORTB Tri-State Register50Register 3-7: WPUB: Weak Pull-up PORTB Register51Register 3-8: IOCB: Interrupt-on-change PORTB Register513.4.4 Pin Descriptions and Diagrams52FIGURE 3-9: Block Diagram of RB<3:0>52FIGURE 3-10: Block Diagram of RB<7:4>54TABLE 3-2: Summary of Registers Associated with PORTB543.5 PORTC and TRISC Registers55EXAMPLE 3-4: Initializing PORTC55Register 3-9: PORTC: PORTC Register55Register 3-10: TRISC: PORTC Tri-State Register553.5.1 RC0/T1OSO/T1CKI56FIGURE 3-11: Block Diagram of RC0563.5.2 RC1/T1OSI/CCP256FIGURE 3-12: Block Diagram of RC1563.5.3 RC2/P1A/CCP156FIGURE 3-13: Block Diagram of RC2563.5.4 RC3/SCK/SCL57FIGURE 3-14: Block Diagram of RC3573.5.5 RC4/SDI/SDA57FIGURE 3-15: Block Diagram of RC4573.5.6 RC5/SDO57FIGURE 3-16: Block Diagram of RC5573.5.7 RC6/TX/CK58FIGURE 3-17: Block Diagram of RC6583.5.8 RC7/RX/DT58FIGURE 3-18: Block Diagram of RC758TABLE 3-3: Summary of Registers Associated with PORTC583.6 PORTD and TRISD Registers59EXAMPLE 3-5: Initializing PORTD59Register 3-11: PORTD: PORTD Register59Register 3-12: TRISD: PORTD Tri-State Register593.6.1 RD<4:0>60FIGURE 3-19: Block Diagram of RD<4:0>603.6.2 RD5/P1B(1)603.6.3 RD6/P1C(1)603.6.4 RD7/P1D(1)60FIGURE 3-20: Block Diagram of RD<7:5>60TABLE 3-4: Summary of Registers Associated with PORTD603.7 PORTE and TRISE Registers61EXAMPLE 3-6: Initializing PORTE61Register 3-13: PORTE: PORTE Register61Register 3-14: TRISE: PORTE Tri-State Register613.7.1 RE0/AN5(1)623.7.2 RE1/AN6(1)623.7.3 RE2/AN7(1)62FIGURE 3-21: Block Diagram of RE<2:0>623.7.4 RE3/MCLR/Vpp62FIGURE 3-22: Block Diagram of RE362TABLE 3-5: Summary of Registers Associated with PORTE634.0 Oscillator Module (With Fail-Safe Clock Monitor)654.1 Overview65FIGURE 4-1: Simplified PIC® MCU Clock Source Block Diagram654.2 Oscillator Control66Register Definitions: Oscillator Control66Register 4-1: OSCCON: Oscillator Control Register664.3 Clock Source Modes674.4 External Clock Modes674.4.1 Oscillator Start-up Timer (OST)67TABLE 4-1: Oscillator Delay Examples674.4.2 EC Mode67FIGURE 4-2: External Clock (EC) Mode Operation674.4.3 LP, XT, HS Modes68FIGURE 4-3: Quartz Crystal Operation (LP, XT or HS Mode)68FIGURE 4-4: Ceramic Resonator Operation (XT or HS Mode)684.4.4 External RC Modes69FIGURE 4-5: External RC Modes694.5 Internal Clock Modes694.5.1 INTOSC and INTOSCIO Modes694.5.2 HFINTOSC69Register 4-2: OSCTUNE: Oscillator Tuning ReGister704.5.3 LFINTOSC714.5.4 Frequency Select Bits (IRCF)714.5.5 HFINTOSC and LFINTOSC Clock Switch Timing71FIGURE 4-6: Internal Oscillator Switch Timing724.6 Clock Switching734.6.1 System Clock Select (SCS) Bit734.6.2 Oscillator Start-up Time-out Status (OSTS) Bit734.7 Two-Speed Clock Start-up Mode734.7.1 Two-Speed Start-up Mode Configuration734.7.2 Two-Speed Start-up Sequence744.7.3 Checking Two-Speed Clock Status74FIGURE 4-7: Two-Speed Start-up744.8 Fail-Safe Clock Monitor75FIGURE 4-8: FSCM Block Diagram754.8.1 Fail-Safe Detection754.8.2 Fail-Safe Operation754.8.3 Fail-Safe Condition Clearing754.8.4 Reset or Wake-up from Sleep75FIGURE 4-9: FSCM Timing Diagram76TABLE 4-2: Summary of Registers Associated with Clock Sources76TABLE 4-3: Summary of Configuration Word Associated with Clock Sources765.0 Timer0 Module775.1 Timer0 Operation775.1.1 8-Bit Timer Mode775.1.2 8-Bit Counter Mode77FIGURE 5-1: Timer0/WDT Prescaler Block Diagram775.1.3 Software Programmable Prescaler78EXAMPLE 5-1: Changing Prescaler (Timer0 ® WDT)78EXAMPLE 5-2: Changing Prescaler (WDT ® Timer0)785.1.4 Timer0 Interrupt785.1.5 Using Timer0 with an External Clock78Register 5-1: OPTION_REG: OPTION Register79TABLE 5-1: Summary of Registers Associated with Timer0796.0 Timer1 Module with Gate Control816.1 Timer1 Operation816.2 Clock Source Selection81FIGURE 6-1: Timer1 Block Diagram816.2.1 Internal Clock Source826.2.2 External Clock Source826.3 Timer1 Prescaler826.4 Timer1 Oscillator826.5 Timer1 Operation in Asynchronous Counter Mode826.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode826.6 Timer1 Gate826.7 Timer1 Interrupt836.8 Timer1 Operation During Sleep836.9 ECCP Capture/Compare Time Base836.10 ECCP Special Event Trigger836.11 Comparator Synchronization83FIGURE 6-2: Timer1 Incrementing Edge836.12 Timer1 Control Register84Register Definitions: Timer1 Control84Register 6-1: T1CON: Timer1 Control Register84TABLE 6-1: Summary of Registers Associated with Timer1857.0 Timer2 Module877.1 Timer2 Operation87FIGURE 7-1: Timer2 Block Diagram87Register Definitions: Timer2 Control88Register 7-1: T2CON: Timer2 Control Register88TABLE 7-1: Summary of Associated Timer2 Registers888.0 Comparator Module898.1 Comparator Overview89FIGURE 8-1: Single Comparator89FIGURE 8-2: Comparator C1 Simplified Block Diagram90FIGURE 8-3: Comparator C2 Simplified Block Diagram908.2 Comparator Control918.2.1 Comparator Enable918.2.2 Comparator Input Selection918.2.3 Comparator Reference Selection918.2.4 Comparator Output Selection918.2.5 Comparator Output Polarity91TABLE 8-1: Comparator Output State vs. Input Conditions918.3 Comparator Response Time918.4 Comparator Interrupt Operation92FIGURE 8-4: Comparator Interrupt Timing W/O CMxCON0 Read92FIGURE 8-5: Comparator Interrupt Timing With CMxCON0 Read928.5 Operation During Sleep938.6 Effects of a Reset93Register Definitions: Comparator C193Register 8-1: CM1CON0: Comparator C1 Control Register 093Register Definitions: Comparator C294Register 8-2: CM2CON0: Comparator C2 Control Register 0948.7 Analog Input Connection Considerations95FIGURE 8-6: Analog Input Model958.8 Additional Comparator Features968.8.1 Comparator C2 Gating Timer1968.8.2 Synchronizing Comparator C2 Output to Timer1968.8.3 Simultaneous Comparator Output Read96Register 8-3: CM2CON1: Comparator C2 Control Register 1968.9 Comparator SR Latch978.9.1 Latch Operation978.9.2 Latch Output97FIGURE 8-7: SR Latch Simplified Block Diagram97Register Definitions: SR Latch98Register 8-4: SRCON: SR Latch Control Register988.10 Comparator Voltage Reference998.10.1 Independent Operation998.10.2 Output Voltage Selection99EQUATION 8-1: CVref Output Voltage998.10.3 Output Clamped to Vss998.10.4 Output Ratiometric to Vdd998.10.5 Fixed Voltage Reference998.10.6 Fixed Voltage Reference Stabilization Period998.10.7 Voltage Reference Selection99FIGURE 8-8: Comparator Voltage Reference Block Diagram100FIGURE 8-9: Comparator and ADC Voltage Reference Block Diagram100TABLE 8-2: Comparator and ADC Voltage Reference Priority101Register Definitions: Voltage Reference Control102Register 8-5: VRCON: Voltage Reference Control Register102TABLE 8-3: Summary of Registers Associated with the Comparator and Voltage Reference Modules1029.0 Analog-to-Digital Converter (ADC) Module103FIGURE 9-1: ADC Block Diagram1039.1 ADC Configuration1049.1.1 Port Configuration1049.1.2 Channel Selection1049.1.3 ADC Voltage Reference1049.1.4 Conversion Clock104TABLE 9-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies (Vdd > 3.0V)105FIGURE 9-2: Analog-to-Digital Conversion Tad Cycles1059.1.5 Interrupts1059.1.6 Result Formatting106FIGURE 9-3: 10-Bit A/D Conversion Result Format1069.2 ADC Operation1069.2.1 Starting a Conversion1069.2.2 Completion of a Conversion1069.2.3 Terminating a Conversion1069.2.4 ADC Operation During Sleep1069.2.5 Special Event Trigger1069.2.6 A/D Conversion Procedure107EXAMPLE 9-1: A/D Conversion1079.2.7 ADC Register Definitions108Register Definitions: ADC Control108Register 9-1: ADCON0: A/D Control Register 0108Register 9-2: ADCON1: A/D Control Register 1109Register 9-3: ADRESH: ADC Result Register High (ADRESH) ADFM = 0110Register 9-4: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0110Register 9-5: ADRESH: ADC Result Register High (ADRESH) ADFM = 1110Register 9-6: ADRESL: ADC Result Register Low (ADRESL) ADFM = 11109.3 A/D Acquisition Requirements111EQUATION 9-1: Acquisition Time Example111FIGURE 9-4: Analog Input Model112FIGURE 9-5: ADC Transfer Function112TABLE 9-2: Summary of Associated ADC Registers11310.0 Data EEPROM and Flash Program Memory Control11510.1 EEADR and EEADRH Registers11510.1.1 EECON1 and EECON2 Registers115Register Definitions: Data EEPROM Control116Register 10-1: EEDAT: EEPROM Data Register116Register 10-2: EEADR: EEPROM Address Register116Register 10-3: EEDATH: EEPROM Data High Byte Register116Register 10-4: EEADRH: EEPROM Address High Byte Register116Register 10-5: EECON1: EEPROM Control Register11710.1.2 Reading the Data EEPROM Memory118EXAMPLE 10-1: Data EEPROM Read11810.1.3 Writing to the Data EEPROM Memory118EXAMPLE 10-2: Data EEPROM Write11810.1.4 Reading the Flash Program Memory119EXAMPLE 10-3: Flash Program Read119FIGURE 10-1: Flash Program Memory Read Cycle Execution12010.2 Writing to Flash Program Memory121FIGURE 10-2: Block Writes to 2K and 4k Flash Program Memory122FIGURE 10-3: Block Writes to 8k Flash Program Memory122EXAMPLE 10-4: Writing to Flash Program Memory12310.3 Write Verify124EXAMPLE 10-5: Write Verify12410.3.1 Using the Data EEPROM12410.4 Protection Against Spurious Write12410.5 Data EEPROM Operation During Code-Protect124TABLE 10-1: Summary of Registers Associated with Data EEPROM12511.0 Capture/Compare/PWM Modules (CCP1 and CCP2)12711.1 Enhanced Capture/Compare/PWM (CCP1)127TABLE 11-1: ECCP Mode – Timer Resources Required127Register Definitions: CCP Control128Register 11-1: CCP1CON: Enhanced CCP1 Control Register12811.2 Capture/Compare/PWM (CCP2)129TABLE 11-2: CCP Mode – Timer Resources Required129Register 11-2: CCP2CON: CCP2 Control Register12911.3 Capture Mode13011.3.1 CCP pin Configuration130FIGURE 11-1: Capture Mode Operation Block Diagram13011.3.2 Timer1 Mode Selection13011.3.3 Software Interrupt13011.3.4 CCP Prescaler130EXAMPLE 11-1: Changing Between Capture Prescalers13011.4 Compare Mode131FIGURE 11-2: Compare Mode Operation Block Diagram13111.4.1 CCP Pin Configuration13111.4.2 Timer1 Mode Selection13111.4.3 Software Interrupt Mode13111.4.4 Special Event Trigger13111.5 PWM Mode132FIGURE 11-3: Simplified PWM Block Diagram132FIGURE 11-4: CCP PWM Output13211.5.1 PWM Period132EQUATION 11-1: PWM Period13211.5.2 PWM Duty Cycle133EQUATION 11-2: Pulse Width133EQUATION 11-3: Duty Cycle Ratio13311.5.3 PWM Resolution134EQUATION 11-4: PWM Resolution134TABLE 11-3: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)134TABLE 11-4: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)13411.5.4 Operation in Sleep Mode13511.5.5 Changes in System Clock Frequency13511.5.6 Effects of Reset13511.5.7 Setup for PWM Operation13511.6 PWM (Enhanced Mode)136FIGURE 11-5: Example Simplified Block Diagram of the Enhanced PWM Mode136TABLE 11-5: Example Pin Assignments for Various PWM Enhanced Modes136FIGURE 11-6: Example PWM (Enhanced Mode) Output Relationships (Active-High State)137FIGURE 11-7: Example Enhanced PWM Output Relationships (Active-Low State)13811.6.1 Half-Bridge Mode139FIGURE 11-8: Example of Half- Bridge PWM Output139FIGURE 11-9: Example of Half-Bridge Applications13911.6.2 Full-Bridge Mode140FIGURE 11-10: Example of Full-Bridge Application140FIGURE 11-11: Example of Full-Bridge PWM Output141FIGURE 11-12: Example of PWM Direction Change142FIGURE 11-13: Example of PWM Direction Change at Near 100% Duty Cycle14311.6.3 Start-up Considerations14411.6.4 Enhanced PWM Auto- Shutdown Mode145FIGURE 11-14: Auto-Shutdown Block Diagram145Register 11-3: ECCPAS: Enhanced Capture/Compare/PWM Auto-Shutdown Control Register146FIGURE 11-15: PWM Auto-Shutdown With Firmware Restart (PRSEN = 0)14711.6.5 Auto-Restart Mode147FIGURE 11-16: PWM Auto-Shutdown With Auto-Restart Enabled (PRSEN = 1)14711.6.6 Programmable Dead-Band Delay Mode148FIGURE 11-17: Example of Half- Bridge PWM Output148FIGURE 11-18: Example of Half-Bridge Applications148Register Definitions: PWM Control149Register 11-4: PWM1CON: Enhanced PWM Control Register14911.6.7 Pulse Steering Mode150Register Definitions: Pulse Steering Control150Register 11-5: PSTRCON: Pulse Steering Control Register(1)150FIGURE 11-19: Simplified Steering Block Diagram151FIGURE 11-20: Example of Steering Event at End of Instruction (STRSYNC = 0)152FIGURE 11-21: Example of Steering Event at Beginning of Instruction (STRSYNC = 1)152TABLE 11-6: Registers Associated with Capture, Compare and Timer1153TABLE 11-7: Registers Associated with PWM and Timer215312.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)155FIGURE 12-1: EUSART Transmit Block Diagram155FIGURE 12-2: EUSART Receive Block Diagram15612.1 EUSART Asynchronous Mode15712.1.1 EUSART Asynchronous Transmitter157FIGURE 12-3: Asynchronous Transmission158FIGURE 12-4: Asynchronous Transmission (Back-to-Back)159TABLE 12-1: Registers Associated with Asynchronous Transmission15912.1.2 EUSART Asynchronous Receiver160FIGURE 12-5: Asynchronous Reception162TABLE 12-2: Registers Associated with Asynchronous Reception16312.2 Clock Accuracy with Asynchronous Operation164Register Definitions: EUSART Control164Register 12-1: TXSTA: Transmit Status and Control Register164Register 12-2: RCSTA: Receive Status and Control Register(1)165Register 12-3: BAUDCTL: Baud Rate Control Register16612.3 EUSART Baud Rate Generator (BRG)167EXAMPLE 12-1: Calculating Baud Rate Error167TABLE 12-3: Baud Rate Formulas167TABLE 12-4: Registers Associated with the Baud Rate Generator167TABLE 12-5: Baud Rates for Asynchronous Modes16812.3.1 Auto-Baud Detect171TABLE 12-6: BRG Counter Clock Rates171FIGURE 12-6: Automatic Baud Rate Calibration17112.3.2 Auto-Wake-up on Break172FIGURE 12-7: Auto-Wake-up Bit (WUE) Timing during Normal Operation172FIGURE 12-8: Auto-Wake-up Bit (WUE) Timings during Sleep17312.3.3 Break Character Sequence17312.3.4 Receiving a Break Character173FIGURE 12-9: Send Break Character Sequence17412.4 EUSART Synchronous Mode17512.4.1 Synchronous Master Mode175FIGURE 12-10: Synchronous Transmission176FIGURE 12-11: Synchronous Transmission (Through TXEN)176TABLE 12-7: Registers Associated with Synchronous Master Transmission176FIGURE 12-12: Synchronous Reception (Master Mode, SREN)178TABLE 12-8: Registers Associated with Synchronous Master Reception17812.4.2 Synchronous Slave Mode179TABLE 12-9: Registers Associated with Synchronous Slave Transmission179TABLE 12-10: Registers Associated with Synchronous Slave Reception18012.5 EUSART Operation During Sleep18112.5.1 Synchronous Receive During Sleep18112.5.2 Synchronous Transmit During Sleep18113.0 Master Synchronous Serial Port (MSSP) Module18313.1 Master SSP (MSSP) Module Overview18313.2 Control Registers183Register 13-1: SSPSTAT: SSP STATUS Register184Register 13-2: SSPCON: SSP Control Register 1185Register 13-3: SSPCON2: SSP Control Register 218613.3 SPI Mode18713.3.1 Operation187FIGURE 13-1: MSSP Block Diagram (SPI Mode)18713.3.2 Enabling SPI I/O18813.3.3 Master Mode189FIGURE 13-2: SPI Mode Waveform (Master Mode)18913.3.4 Slave Mode19013.3.5 Slave Select Synchronization190FIGURE 13-3: Slave Synchronization Waveform190FIGURE 13-4: SPI Mode Waveform (Slave Mode with CKE = 0)191FIGURE 13-5: SPI Mode Waveform (Slave Mode with CKE = 1)19113.3.6 Sleep Operation19213.3.7 Effects of a Reset19213.3.8 Bus Mode Compatibility192TABLE 13-1: SPI Bus Modes192TABLE 13-2: Registers Associated with SPI Operation19213.4 MSSP I2C Operation193FIGURE 13-6: MSSP Block Diagram (I2C Mode)19313.4.1 Slave Mode193FIGURE 13-7: I2C™ Slave Mode Waveforms for Reception (7-Bit Address)195FIGURE 13-8: I2C™ Slave Mode Waveforms for Transmission (7-Bit Address)19513.4.2 General Call Address Support196FIGURE 13-9: Slave Mode General Call Address Sequence (7 or 10-Bit Address)19613.4.3 Master Mode19713.4.4 I2C™ Master Mode Support197FIGURE 13-10: MSSP Block Diagram (I2C™ Master Mode)19713.4.5 Baud Rate Generator199FIGURE 13-11: Baud Rate Generator Block Diagram199FIGURE 13-12: Baud Rate Generator Timing With Clock Arbitration19913.4.6 I2C™ Master Mode Start Condition Timing200FIGURE 13-13: First Start Bit Timing20013.4.7 I2C™ Master Mode Repeated Start Condition Timing201FIGURE 13-14: Repeat Start Condition Waveform20113.4.8 I2C™ Master Mode Transmission20213.4.9 I2C™ Master Mode Reception202FIGURE 13-15: I2C™ Master Mode Waveform (Transmission, 7 or 10-Bit Address)203FIGURE 13-16: I2C™ Master Mode Waveform (Reception, 7-Bit Address)20413.4.10 Acknowledge Sequence Timing20513.4.11 Stop Condition Timing205FIGURE 13-17: Acknowledge Sequence Waveform205FIGURE 13-18: Stop Condition Receive or Transmit Mode20613.4.12 Clock Arbitration20613.4.13 Sleep Operation20613.4.14 Effect of a Reset206FIGURE 13-19: Clock Arbitration Timing in Master Transmit Mode20613.4.15 Multi-Master Mode20713.4.16 Multi -Master Communication, Bus Collision, and Bus Arbitration207FIGURE 13-20: Bus Collision Timing for Transmit and Acknowledge207FIGURE 13-21: Bus Collision During Start Condition (SDA only)208FIGURE 13-22: Bus Collision During Start Condition (SCL = 0)209FIGURE 13-23: BRG Reset Due to SDA Arbitration During Start Condition209FIGURE 13-24: Bus Collision During a Repeated Start Condition (Case 1)210FIGURE 13-25: Bus Collision During Repeated Start Condition (Case 2)210FIGURE 13-26: Bus Collision During a Stop Condition (Case 1)211FIGURE 13-27: Bus Collision During a Stop Condition (Case 2)21113.4.17 SSP Mask Register212Register 13-4: SSPMSK: SSP Mask Register(1)21214.0 Special Features of the CPU21314.1 Configuration Bits214Register Definitions: Configuration Words214Register 14-1: CONFIG1: Configuration Word Register 1214Register 14-2: CONFIG2: Configuration Word Register 221514.2 Reset216FIGURE 14-1: Simplified Block Diagram of On-chip Reset Circuit21614.2.1 Power-on Reset (POR)21714.2.2 MCLR217FIGURE 14-2: Recommended MCLR Circuit21714.2.3 Power-up Timer (PWRT)21714.2.4 Brown-out Reset (BOR)218FIGURE 14-3: Brown-out Situations21814.2.5 Time-out Sequence21914.2.6 Power Control (PCON) Register219TABLE 14-1: Time-out in Various Situations219TABLE 14-2: Status/PCON Bits and Their Significance219TABLE 14-3: Summary of Registers Associated with Brown-out219FIGURE 14-4: Time-out Sequence On Power-up (Delayed MCLR): Case 1220FIGURE 14-5: Time-out Sequence On Power-up (Delayed MCLR): Case 2220FIGURE 14-6: Time-out Sequence on Power-up (MCLR with Vdd)220TABLE 14-4: Initialization Condition for Register221TABLE 14-5: Initialization Condition for Special Registers22314.3 Interrupts22414.3.1 RB0/INT Interrupt22414.3.2 Timer0 Interrupt22514.3.3 PORTB Interrupt225FIGURE 14-7: Interrupt Logic225FIGURE 14-8: INT Pin Interrupt Timing226TABLE 14-6: Summary of Interrupt Registers22614.4 Context Saving During Interrupts227EXAMPLE 14-1: Saving STATUS and W Registers in RAM22714.5 Watchdog Timer (WDT)22814.5.1 WDT Oscillator22814.5.2 WDT Control228FIGURE 14-9: Watchdog Timer Block Diagram228TABLE 14-7: WDT Status228Register 14-3: WDTCON: Watchdog Timer Control Register229TABLE 14-8: Summary of Registers Associated with Watchdog Timer229TABLE 14-9: Summary of Configuration Word Associated with Watchdog Timer22914.6 Power-Down Mode (Sleep)23014.6.1 Wake-up from Sleep23014.6.2 Wake-up Using Interrupts230FIGURE 14-10: Wake-up from Sleep Through Interrupt23114.7 Code Protection23114.8 ID Locations23114.9 In-Circuit Serial Programming™231FIGURE 14-11: Typical In-Circuit Serial Programming™ Connection23214.10 Low-Voltage (Single-Supply) ICSP Programming23214.11 In-Circuit Debugger23314.11.1 ICD Pinout233TABLE 14-10: PIC16F883/884/886/887-ICD Pin Descriptions23315.0 Instruction Set Summary23515.1 Read-Modify-Write Operations235TABLE 15-1: Opcode Field Descriptions235FIGURE 15-1: General Format for Instructions235TABLE 15-2: PIC16F882/883/884/886/887 Instruction Set23615.2 Instruction Descriptions23716.0 Development Support24516.1 MPLAB Integrated Development Environment Software24516.2 MPLAB C Compilers for Various Device Families24616.3 HI-TECH C for Various Device Families24616.4 MPASM Assembler24616.5 MPLINK Object Linker/ MPLIB Object Librarian24616.6 MPLAB Assembler, Linker and Librarian for Various Device Families24616.7 MPLAB SIM Software Simulator24716.8 MPLAB REAL ICE In-Circuit Emulator System24716.9 MPLAB ICD 3 In-Circuit Debugger System24716.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express24716.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express24816.12 MPLAB PM3 Device Programmer24816.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits24817.0 Electrical Specifications249Absolute Maximum Ratings(†)249FIGURE 17-1: PIC16F882/883/884/886/887 Voltage-Frequency Graph, -40°C £ ta £ +125°C250FIGURE 17-2: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature25017.1 DC Characteristics: PIC16F882/883/884/886/887-I (Industrial) PIC16F882/883/884/886/887-E (Extended)25117.2 DC Characteristics: PIC16F882/883/884/886/887-I (Industrial) PIC16F882/883/884/886/887-E (Extended)25217.3 DC Characteristics: PIC16F882/883/884/886/887-I (Industrial)25317.4 DC Characteristics: PIC16F882/883/884/886/887-E (Extended)25417.5 DC Characteristics: PIC16F882/883/884/886/887-I (Industrial) PIC16F882/883/884/886/887-E (Extended)25517.6 Thermal Considerations25717.7 Timing Parameter Symbology258FIGURE 17-3: Load Conditions25817.8 AC Characteristics: PIC16F882/883/884/886/887 (Industrial, Extended)259FIGURE 17-4: Clock Timing259TABLE 17-1: Clock Oscillator Timing Requirements259TABLE 17-2: Oscillator Parameters260FIGURE 17-5: CLKOUT and I/O Timing261TABLE 17-3: CLKOUT and I/O Timing Parameters261FIGURE 17-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing262FIGURE 17-7: Brown-out Reset Timing and Characteristics262TABLE 17-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Parameters263FIGURE 17-8: Timer0 and Timer1 External Clock Timings264TABLE 17-5: Timer0 and Timer1 External Clock Requirements264FIGURE 17-9: Capture/Compare/PWM Timings (ECCP)265TABLE 17-6: Capture/Compare/PWM Requirements (ECCP)265TABLE 17-7: Comparator Specifications266TABLE 17-8: Comparator Voltage Reference (CVref) Specifications266TABLE 17-9: Voltage (VR) Reference Specifications266TABLE 17-10: PIC16F882/883/884/886/887 A/D Converter (ADC) Characteristics267TABLE 17-11: PIC16F882/883/884/886/887 A/D Conversion Requirements268FIGURE 17-10: PIC16F882/883/884/886/887 A/D Conversion Timing (Normal Mode)269FIGURE 17-11: PIC16F882/883/884/886/887 A/D Conversion Timing (Sleep Mode)269FIGURE 17-12: EUSART Synchronous Transmission (Master/Slave) Timing270TABLE 17-12: EUSART Synchronous Transmission Requirements270FIGURE 17-13: EUSART Synchronous Receive (Master/Slave) Timing270TABLE 17-13: EUSART Synchronous Receive Requirements270FIGURE 17-14: SPI Master Mode Timing (CKE = 0, smp = 0)271FIGURE 17-15: SPI Master Mode Timing (CKE = 1, SMP = 1)271FIGURE 17-16: SPI Slave Mode Timing (CKE = 0)272FIGURE 17-17: SPI Slave Mode Timing (CKE = 1)272TABLE 17-14: SPI Mode requirements273FIGURE 17-18: I2C™ Bus Start/Stop Bits Timing273TABLE 17-15: I2C™ Bus Start/Stop Bits Requirements274FIGURE 17-19: I2C™ Bus Data Timing274TABLE 17-16: I2C™ Bus Data Requirements27518.0 DC and AC Characteristics Graphs and Tables277FIGURE 18-1: Typical Idd vs. Fosc Over Vdd (EC Mode)278FIGURE 18-2: Maximum Idd vs. Fosc Over Vdd (EC Mode)278FIGURE 18-3: Typical Idd vs. Fosc Over Vdd (HS Mode)279FIGURE 18-4: Maximum Idd vs. Fosc Over Vdd (HS Mode)279FIGURE 18-5: Typical Idd vs. Vdd Over Fosc (XT Mode)280FIGURE 18-6: Maximum Idd vs. Vdd Over Fosc (XT Mode)280FIGURE 18-7: Typical Idd vs. Vdd Over Fosc (EXTRC Mode)281FIGURE 18-8: Maximum Idd vs. Vdd (EXTRC Mode)281FIGURE 18-9: Idd vs. Vdd Over Fosc (LFINTOSC Mode, 31 kHz)282FIGURE 18-10: Idd vs. Vdd (LP Mode)282FIGURE 18-11: Typical Idd vs. Fosc Over Vdd (HFINTOSC Mode)283FIGURE 18-12: Maximum Idd vs. Fosc Over Vdd (HFINTOSC Mode)283FIGURE 18-13: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)284FIGURE 18-14: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)284FIGURE 18-15: Comparator Ipd vs. Vdd (Both Comparators Enabled)285FIGURE 18-16: BOR Ipd vs. Vdd Over Temperature285FIGURE 18-17: Typical WDT Ipd vs. Vdd (25°C)286FIGURE 18-18: Maximum WDT Ipd vs. Vdd Over Temperature286FIGURE 18-19: WDT Period vs. Vdd Over Temperature287FIGURE 18-20: WDT Period vs. Temperature (Vdd = 5.0V)287FIGURE 18-21: CVref Ipd vs. Vdd Over Temperature (High Range)288FIGURE 18-22: CVref Ipd vs. Vdd Over Temperature (Low Range)288FIGURE 18-23: Typical VP6 Reference Ipd vs. Vdd (25°C)289FIGURE 18-24: Maximum VP6 Reference Ipd vs. Vdd Over Temperature289FIGURE 18-25: T1OSC Ipd vs. Vdd Over Temperature (32 kHz)290FIGURE 18-26: Vol vs. Iol Over Temperature (Vdd = 3.0V)290FIGURE 18-27: Vol vs. Iol Over Temperature (Vdd = 5.0V)291FIGURE 18-28: Voh vs. Ioh Over Temperature (Vdd = 3.0V)291FIGURE 18-29: Voh vs. Ioh Over Temperature (Vdd = 5.0V)292FIGURE 18-30: TTL Input Threshold Vin vs. Vdd Over Temperature292FIGURE 18-31: Schmitt Trigger Input Threshold Vin vs. Vdd Over Temperature293FIGURE 18-32: Comparator Response Time (Rising Edge)293FIGURE 18-33: Comparator Response Time (Falling Edge)294FIGURE 18-34: LFINTOSC Frequency vs. Vdd Over Temperature (31 kHz)294FIGURE 18-35: ADC Clock Period vs. Vdd Over Temperature295FIGURE 18-36: Typical HFINTOSC Start-Up Times vs. Vdd Over Temperature295FIGURE 18-37: Maximum HFINTOSC Start-Up Times vs. Vdd Over Temperature296FIGURE 18-38: Minimum HFINTOSC Start-Up Times vs. Vdd Over Temperature296FIGURE 18-39: Typical HFINTOSC Frequency Change vs. Vdd (25°C)297FIGURE 18-40: Typical HFINTOSC Frequency Change Over Device Vdd (85°C)297FIGURE 18-41: Typical HFINTOSC Frequency Change vs. Vdd (125°C)298FIGURE 18-42: Typical HFINTOSC Frequency Change vs. Vdd (-40°C)298FIGURE 18-43: Typical VP6 Reference Voltage vs. Vdd (25°C)299FIGURE 18-44: VP6 Drift Over Temperature Normalized at 25°C (Vdd 5V)299FIGURE 18-45: VP6 Drift Over Temperature Normalized at 25°C (Vdd 3V)300FIGURE 18-46: Typical VP6 Reference Voltage Distribution (3V, 25°C)300FIGURE 18-47: Typical VP6 Reference Voltage Distribution (3V, 85°C)301FIGURE 18-48: Typical VP6 Reference Voltage Distribution (3V, 125°C)301FIGURE 18-49: Typical VP6 Reference Voltage Distribution (3V, -40°C)302FIGURE 18-50: Typical VP6 Reference Voltage Distribution (5V, 25°C)302FIGURE 18-51: Typical VP6 Reference Voltage Distribution (5V, 85°C)303FIGURE 18-52: Typical VP6 Reference Voltage Distribution (5V, 125°C)303FIGURE 18-53: Typical VP6 Reference Voltage Distribution (5V, -40°C)30419.0 Packaging Information30519.1 Package Marking Information30519.1 Package Marking Information (Continued)30619.1 Package Marking Information (Continued)30719.2 Package Details308Appendix A: Data Sheet Revision History323Appendix B: Migrating from other PIC® Devices324TABLE B-1: Feature Comparison324INDEX325A325B325C325D326E326F327G327I327L328M328O328P328R329S330T330U331V331W331The Microchip Web Site333Customer Change Notification Service333Customer Support333Reader Response334Product Identification System335Trademarks337Worldwide Sales338Size: 6.27 MBPages: 338Language: EnglishOpen manual
