Data Sheet (PIC18F87K22-I/PTRSL)Table of ContentsLow-Power Features:3Special Microcontroller Features:3Peripheral Highlights:4Pin Diagrams – PIC18F6XK225Pin Diagrams – PIC18F8XK226Table of Contents7Most Current Data Sheet8Errata8Customer Notification System81.0 Device Overview91.1 Core Features91.1.1 nanoWatt Technology91.1.2 Oscillator Options and Features91.1.3 Memory Options91.1.4 External Memory Bus91.1.5 Extended Instruction Set91.1.6 Easy Migration101.2 Other Special Features101.3 Details on Individual Family Members11TABLE 1-1: Device Features for the PIC18F6XK22 (64-pin Devices)12TABLE 1-2: Device Features for the PIC18F8XK22 (80-pin Devices)12FIGURE 1-1: PIC18F6XK22 (64-pin) Block Diagram13FIGURE 1-2: PIC18F8XK22 (80-pin) Block Diagram14TABLE 1-3: PIC18F6XK22 Pinout I/O Descriptions15TABLE 1-4: PIC18F8XK22 Pinout I/O Descriptions242.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers372.1 Basic Connection Requirements37FIGURE 2-1: Recommended Minimum connections372.2 Power Supply Pins382.3 Master Clear (MCLR) Pin38FIGURE 2-2: Example of MCLR Pin Connections382.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)39FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap39TABLE 2-1: Suitable Capacitor Equivalents39FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics402.5 ICSP Pins402.6 External Oscillator Pins412.7 Unused I/Os41FIGURE 2-5: Suggested Placement of the Oscillator Circuit413.0 Oscillator Configurations433.1 Oscillator Types43TABLE 3-1: HS, EC, XT, LP and RC Modes: Ranges and Settings44FIGURE 3-1: PIC18F87K22 Family Clock Diagram443.2 Control Registers45Register 3-1: OSCCON: Oscillator Control Register(1)45Register 3-2: OSCCON2: Oscillator Control Register 246Register 3-3: OSCTUNE: Oscillator Tuning Register473.3 Clock Sources and Oscillator Switching483.3.1 OSC1/OSC2 Oscillator483.3.2 Clock Source Selection483.3.3 Oscillator Transitions493.4 RC Oscillator49FIGURE 3-2: RC Oscillator Mode49FIGURE 3-3: RCIO Oscillator Mode493.5 External Oscillator Modes503.5.1 Crystal Oscillator/Ceramic Resonators (HS Modes)50TABLE 3-2: Capacitor Selection for Ceramic Resonators50TABLE 3-3: Capacitor Selection for Crystal Oscillator50FIGURE 3-4: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)503.5.2 External Clock Input (EC Modes)51FIGURE 3-5: External Clock Input Operation (EC Configuration)51FIGURE 3-6: External Clock Input Operation (HS OSC Configuration)513.5.3 PLL Frequency Multiplier51FIGURE 3-7: PLL Block Diagram513.6 Internal Oscillator Block523.6.1 INTIO Modes52FIGURE 3-8: INTIO1 Oscillator Mode52FIGURE 3-9: INTIO2 Oscillator Mode523.6.2 INTPLL Modes523.6.3 Internal Oscillator Output Frequency and Tuning533.6.4 INTOSC Frequency Drift533.7 Reference Clock Output53Register 3-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER543.8 Effects of Power-Managed Modes on the Various Clock Sources553.9 Power-up Delays55TABLE 3-4: OSC1 and OSC2 Pin States in Sleep Mode554.0 Power-Managed Modes574.1 Selecting Power-Managed Modes574.1.1 Clock Sources574.1.2 Entering Power-Managed Modes57TABLE 4-1: Power-Managed Modes574.1.3 Clock Transitions and Status Indicators58TABLE 4-2: System Clock Indicator584.1.4 Multiple Sleep Commands584.2 Run Modes584.2.1 PRI_RUN Mode584.2.2 SEC_RUN Mode58FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode59FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)594.2.3 RC_RUN Mode60TABLE 4-3: Internal Oscillator Frequency Stability Bits60FIGURE 4-3: Transition Timing to RC_RUN Mode61FIGURE 4-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode614.3 Sleep Mode624.4 Idle Modes62FIGURE 4-5: Transition Timing for Entry to Sleep Mode62FIGURE 4-6: Transition Timing for Wake From Sleep (HSPLL)624.4.1 PRI_IDLE Mode634.4.2 SEC_IDLE Mode63FIGURE 4-7: Transition Timing for Entry to Idle Mode63FIGURE 4-8: Transition Timing for Wake From Idle to Run Mode634.4.3 RC_IDLE Mode644.5 Selective Peripheral Module Control64Register 4-1: PMD3: Peripheral Module Disable Register 365Register 4-2: PMD2: Peripheral Module Disable Register 266Register 4-3: PMD1: Peripheral Module Disable Register 167Register 4-4: PMD0: Peripheral Module Disable Register 0684.6 Exiting Idle and Sleep Modes694.6.1 Exit By Interrupt694.6.2 Exit By WDT Time-out694.6.3 Exit By Reset694.6.4 Exit Without an Oscillator Start-up Delay694.7 Ultra Low-Power Wake-up70EXAMPLE 4-1: Ultra Low-Power Wake-up Initialization70FIGURE 4-9: Ultra Low-Power Wake-up Initialization70TABLE 4-4: Exit Delay on Wake-up By Reset From Sleep Mode or Any Idle Mode (By Clock Sources)715.0 Reset735.1 RCON Register73FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit73Register 5-1: RCON: Reset Control Register745.2 Master Clear (MCLR)755.3 Power-on Reset (POR)755.4 Brown-out Reset (BOR)75FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)755.4.1 Detecting BOR755.5 Configuration Mismatch (CM)765.6 Power-up Timer (PWRT)765.6.1 Time-out Sequence76FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)76FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 177FIGURE 5-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 277FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)775.7 Reset State of Registers78TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register78TABLE 5-2: Initialization Conditions for All Registers796.0 Memory Organization87FIGURE 6-1: Memory Maps for PIC18F87K22 Family Devices876.1 Program Memory Organization886.1.1 Hard Memory Vectors88FIGURE 6-2: Hard Vector for PIC18F87K22 Family Devices886.1.2 Program Counter896.1.3 Return Address Stack89FIGURE 6-3: Return Address Stack and Associated Registers89Register 6-1: STKPTR: Stack Pointer Register906.1.4 Fast Register Stack91EXAMPLE 6-1: Fast Register Stack Code Example916.1.5 Look-up Tables in Program Memory91EXAMPLE 6-2: Computed GOTO Using an Offset Value916.2 PIC18 Instruction Cycle926.2.1 Clocking Scheme926.2.2 Instruction Flow/Pipelining92FIGURE 6-4: Clock/ Instruction Cycle92EXAMPLE 6-3: Instruction Pipeline Flow926.2.3 Instructions in Program Memory93FIGURE 6-5: Instructions in Program Memory936.2.4 Two-Word Instructions93EXAMPLE 6-4: Two-Word Instructions936.3 Data Memory Organization946.3.1 Bank Select Register94FIGURE 6-6: Data Memory Map for PIC18FX5K22 and PIC18FX7K22 Devices95FIGURE 6-7: Use of the Bank Select Register (Direct Addressing)966.3.2 Access Bank966.3.3 General Purpose Register File966.3.4 Special Function Registers97TABLE 6-1: Special Function Register Map for PIC18F87K22 Family97TABLE 6-2: PIC18F87K22 Family Register File Summary986.3.5 STATUS Register104Register 6-2: Status Register1046.4 Data Addressing Modes1056.4.1 Inherent and Literal Addressing1056.4.2 Direct Addressing1056.4.3 Indirect Addressing105EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing105FIGURE 6-8: Indirect Addressing1066.5 Program Memory and the Extended Instruction Set1076.6 Data Memory and the Extended Instruction Set1086.6.1 Indexed Addressing with Literal Offset1086.6.2 Instructions Affected By Indexed Literal Offset Mode108FIGURE 6-9: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)1096.6.3 Mapping the Access Bank in Indexed Literal Offset Mode1106.6.4 BSR in Indexed Literal Offset Mode110FIGURE 6-10: Remapping the Access Bank with Indexed Literal Offset Addressing1107.0 Flash Program Memory1117.1 Table Reads and Table Writes111FIGURE 7-1: Table Read Operation111FIGURE 7-2: Table Write Operation1127.2 Control Registers1127.2.1 EECON1 and EECON2 Registers112Register 7-1: EECON1: EEPROM Control Register 11137.2.2 TABLAT – Table Latch Register1147.2.3 TBLPTR – Table Pointer Register1147.2.4 Table Pointer Boundaries114TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions114FIGURE 7-3: Table Pointer Boundaries Based on Operation1147.3 Reading the Flash Program Memory115FIGURE 7-4: Reads From Flash Program Memory115EXAMPLE 7-1: Reading a Flash Program Memory Word1157.4 Erasing Flash Program Memory1167.4.1 Flash Program Memory Erase Sequence116EXAMPLE 7-2: Erasing a Flash Program Memory Row1167.5 Writing to Flash Program Memory117FIGURE 7-5: Table Writes to Flash Program Memory1177.5.1 Flash Program Memory Write Sequence118EXAMPLE 7-3: Writing to Flash Program Memory119EXAMPLE 7-3: Writing to Flash Program Memory (Continued)1207.5.2 Write Verify1207.5.3 Unexpected Termination of Write Operation1207.5.4 Protection Against Spurious Writes1207.6 Flash Program Operation During Code Protection120TABLE 7-2: Registers Associated with Program Flash Memory1208.0 External Memory Bus121TABLE 8-1: PIC18F87K22 family External Bus – I/O Port Functions1218.1 External Memory Bus Control122Register 8-1: MEMCON: External Memory Bus Control Register(1)1228.2 Address and Data Width1238.2.1 Address Shifting on the External Bus1238.2.2 21-bit Addressing123TABLE 8-2: Address and Data Lines for Different Address and Data Widths1238.3 Wait States1248.4 Port Pin Weak Pull-ups1248.5 Program Memory Modes and the External Memory Bus1248.6 16-Bit Data Width Modes1248.6.1 16-Bit Byte Write Mode125FIGURE 8-1: 16-bit Byte Write Mode Example1258.6.2 16-Bit Word Write Mode126FIGURE 8-2: 16-bit Word Write Mode Example1268.6.3 16-Bit Byte Select Mode127FIGURE 8-3: 16-bit Byte Select Mode Example1278.6.4 16-Bit Mode Timing128FIGURE 8-4: External Memory Bus Timing for TBLRD (Extended Microcontroller Mode)128FIGURE 8-5: External Memory Bus Timing for Sleep (Extended Microcontroller Mode)1288.7 8-Bit Data Width Mode129FIGURE 8-6: 8-bit Multiplexed Mode Example1298.7.1 8-bit Mode Timing130FIGURE 8-7: External Memory Bus Timing For TBLRD (Extended Microcontroller Mode)130FIGURE 8-8: External Memory Bus Timing for SLEEP (Extended Microcontroller Mode)1308.8 Operation in Power-Managed Modes131TABLE 8-3: Registers Associated with the External Memory Bus1319.0 Data EEPROM Memory1339.1 EEADR and EEADRH Registers1339.2 EECON1 and EECON2 Registers133Register 9-1: EECON1: Data EEPROM Control Register 11349.3 Reading the Data EEPROM Memory1359.4 Writing to the Data EEPROM Memory1359.5 Write Verify135EXAMPLE 9-1: Data EEPROM Read136EXAMPLE 9-2: Data EEPROM Write1369.6 Operation During Code-Protect1379.7 Protection Against Spurious Write1379.8 Using the Data EEPROM137EXAMPLE 9-3: Data EEPROM Refresh Routine137TABLE 9-1: Registers Associated with Data EEPROM Memory13810.0 8 X 8 Hardware Multiplier13910.1 Introduction13910.2 Operation139EXAMPLE 10-1: 8 x 8 Unsigned Multiply Routine139EXAMPLE 10-2: 8 x 8 Signed Multiply Routine139TABLE 10-1: Performance Comparison for Various Multiply Operations139EQUATION 10-1: 16 x 16 Unsigned Multiplication Algorithm140EXAMPLE 10-3: 16 x 16 Unsigned Multiply Routine140EQUATION 10-2: 16 x 16 Signed Multiplication Algorithm140EXAMPLE 10-4: 16 x 16 Signed Multiply Routine14011.0 Interrupts141FIGURE 11-1: PIC18F87K22 Family Interrupt Logic14211.1 INTCON Registers143Register 11-1: INTCON: Interrupt Control Register143Register 11-2: INTCON2: Interrupt Control Register 2144Register 11-3: INTCON3: Interrupt Control Register 314511.2 PIR Registers146Register 11-4: PIR1: Peripheral Interrupt Request (Flag) Register 1146Register 11-5: PIR2: Peripheral Interrupt Request (Flag) Register 2147Register 11-6: PIR3: Peripheral Interrupt Request (Flag) Register 3148Register 11-7: PIR4: Peripheral Interrupt Request (Flag) Register 4149Register 11-8: PIR5: Peripheral Interrupt Request (Flag) Register 5150Register 11-9: PIR6: Peripheral Interrupt Request (Flag) Register 615111.3 PIE Registers152Register 11-10: PIE1: Peripheral Interrupt Enable Register 1152Register 11-11: PIE2: Peripheral Interrupt Enable Register 2153Register 11-12: PIE3: Peripheral Interrupt Enable Register 3154Register 11-13: PIE4: Peripheral Interrupt Enable Register 4154Register 11-14: PIE5: Peripheral Interrupt Enable Register 5155Register 11-15: PIE6: Peripheral Interrupt Enable Register 615611.4 IPR Registers157Register 11-16: IPR1: Peripheral Interrupt Priority Register 1157Register 11-17: IPR2: Peripheral Interrupt Priority Register 2158Register 11-18: IPR3: Peripheral Interrupt Priority Register 3159Register 11-19: IPR4: Peripheral Interrupt Priority Register 4159Register 11-20: IPR5: Peripheral Interrupt Priority Register 5160Register 11-21: IPR6: Peripheral Interrupt Priority Register 616111.5 RCON Register162Register 11-22: RCON: Reset Control Register16211.6 INTx Pin Interrupts16311.7 TMR0 Interrupt16311.8 PORTB Interrupt-on-Change16311.9 Context Saving During Interrupts163EXAMPLE 11-1: Saving STATUS, WREG and BSR Registers in RAM163TABLE 11-1: Summary of Registers Associated with Interrupts16412.0 I/O Ports165FIGURE 12-1: Generic I/O Port Operation16512.1 I/O Port Pin Capabilities16512.1.1 Pin Output Drive16512.1.2 Pull-up Configuration165Register 12-1: PADCFG1: Pad Configuration Register16612.1.3 Open-Drain Outputs167FIGURE 12-2: Using the Open-Drain Output (USART Shown as Example)167Register 12-2: ODCON1: Peripheral Open-Drain Control Register 1167Register 12-3: ODCON2: Peripheral Open-Drain Control Register 2168Register 12-4: ODCON3: Peripheral Open-Drain Control Register 316912.1.4 Analog and Digital Ports16912.2 PORTA, TRISA and LATA Registers170EXAMPLE 12-1: Initializing PORTA170TABLE 12-1: PORTA Functions171TABLE 12-2: Summary of Registers Associated with PORTA17112.3 PORTB, TRISB and LATB Registers172EXAMPLE 12-2: Initializing PORTB172TABLE 12-3: PORTB Functions172TABLE 12-4: Summary of Registers Associated with PORTB17312.4 PORTC, TRISC and LATC Registers174EXAMPLE 12-3: Initializing PORTC174TABLE 12-5: PORTC Functions174TABLE 12-6: Summary of Registers Associated with PORTC17512.5 PORTD, TRISD and LATD Registers176EXAMPLE 12-4: Initializing PORTD176TABLE 12-7: PORTD Functions176TABLE 12-8: Summary of Registers Associated with PORTD17712.6 PORTE, TRISE and LATE Registers178EXAMPLE 12-5: Initializing PORTE178TABLE 12-9: PORTE Functions178TABLE 12-10: Summary of Registers Associated with PORTE18012.7 PORTF, LATF and TRISF Registers181EXAMPLE 12-6: Initializing PORTF181TABLE 12-11: PORTF Functions181TABLE 12-12: Summary of Registers Associated with PORTF18212.8 PORTG, TRISG and LATG Registers183EXAMPLE 12-7: Initializing PORTG183TABLE 12-13: PORTG Functions183TABLE 12-14: Summary of Registers Associated with PORTG18412.9 PORTH, LATH and TRISH Registers185EXAMPLE 12-8: Initializing PORTH185TABLE 12-15: PORTH Functions185TABLE 12-16: Summary of Registers Associated with PORTH18712.10 PORTJ, TRISJ and LATJ Registers187EXAMPLE 12-9: Initializing PORTJ187TABLE 12-17: PORTJ Functions188TABLE 12-18: Summary of Registers Associated with PORTJ18812.11 Parallel Slave Port189FIGURE 12-3: PORTD and PORTE Block Diagram (Parallel Slave Port)189Register 12-5: PSPCON: Parallel Slave Port Control Register190FIGURE 12-4: Parallel Slave Port Write Waveforms190FIGURE 12-5: Parallel Slave Port Read Waveforms191TABLE 12-19: Registers Associated with Parallel Slave Port19113.0 Timer0 Module193Register 13-1: T0CON: Timer0 Control Register19313.1 Timer0 Operation19413.2 Timer0 Reads and Writes in 16-Bit Mode194FIGURE 13-1: Timer0 Block Diagram (8-bit Mode)194FIGURE 13-2: Timer0 Block Diagram (16-bit Mode)19413.3 Prescaler19513.3.1 Switching Prescaler Assignment19513.4 Timer0 Interrupt195TABLE 13-1: Registers Associated with Timer019514.0 Timer1 Module197Register 14-1: T1CON: Timer1 Control Register19714.1 Timer1 Gate Control Register198Register 14-2: T1GCON: Timer1 Gate Control Register(1)19814.2 Timer1 Operation19914.3 Clock Source Selection19914.3.1 INTERNAL CLOCK SOURCE19914.3.2 EXTERNAL CLOCK SOURCE199TABLE 14-1: Timer1 Clock Source Selection199Figure 14-1: Timer1 Block Diagram20014.4 Timer1 16-Bit Read/Write Mode20114.5 SOSC Oscillator201FIGURE 14-2: External Components for the SOSC Low-Power Oscillator201TABLE 14-2: Capacitor Selection for the Timer Oscillator(2,3,4,5)20114.5.1 Using SOSC as a Clock Source20214.5.2 SOSC Oscillator Layout Considerations202FIGURE 14-3: Oscillator Circuit with Grounded Guard Ring20214.6 Timer1 Interrupt20214.7 Resetting Timer1 Using the ECCP Special Event Trigger20314.8 Timer1 Gate20314.8.1 TIMER1 GATE COUNT ENABLE203TABLE 14-3: TIMER1 GATE ENABLE SELECTIONS203FIGURE 14-4: Timer1 Gate Count Enable Mode20414.8.2 TIMER1 GATE SOURCE SELECTION204TABLE 14-4: TIMER1 GATE SOURCES20414.8.3 TIMER1 GATE TOGGLE MODE205FIGURE 14-5: Timer1 Gate Toggle Mode20514.8.4 TIMER1 GATE SINGLE PULSE MODE20614.8.5 TIMER1 GATE VALUE STATUS206FIGURE 14-6: Timer1 Gate Single Pulse Mode206FIGURE 14-7: Timer1 Gate Single Pulse and Toggle Combined Mode207TABLE 14-5: Registers Associated with Timer1 as a Timer/Counter20715.0 Timer2 Module20915.1 Timer2 Operation209Register 15-1: T2CON: Timer2 Control Register20915.2 Timer2 Interrupt21015.3 Timer2 Output210FIGURE 15-1: Timer2 Block Diagram210TABLE 15-1: Registers Associated with Timer2 as a Timer/Counter21016.0 Timer3/5/7 Modules211Register 16-1: TxCON: Timerx Control Register21216.1 Timer3/5/7 Gate Control Register213Register 16-2: TxGCON: Timerx Gate Control Register(1)213Register 16-3: OSCCON2: Oscillator Control Register 221416.2 Timer3/5/7 Operation215Figure 16-1: TIMER3/5/7 Block Diagram21516.3 Timer3/5/7 16-Bit Read/Write Mode21616.4 Using the SOSC Oscillator as the Timer3/5/7 Clock Source21616.5 Timer3/5/7 Gates21716.5.1 TIMER3/5/7 GATE COUNT ENABLE217TABLE 16-1: TIMER3/5/7 GATE ENABLE SELECTIONS217FIGURE 16-2: Timer3/5/7 Gate Count Enable Mode21716.5.2 TIMER3/5/7 GATE SOURCE SELECTION218TABLE 16-2: TIMER3/5/7 GATE SOURCES21816.5.3 TIMER3/5/7 GATE TOGGLE MODE218FIGURE 16-3: Timer3/5/7 Gate Toggle Mode21816.5.4 TIMER3/5/7 GATE SINGLE PULSE MODE219FIGURE 16-4: Timer3/5/7 Gate Single Pulse Mode219FIGURE 16-5: Timer3/5/7 Gate Single Pulse and Toggle Combined Mode22016.5.5 TIMER3/5/7 GATE VALUE STATUS22016.5.6 TIMER3/5/7 GATE EVENT INTERRUPT22016.6 Timer3/5/7 Interrupt221TABLE 16-3: Timer3/5/7 Interrupt Flag Bits221TABLE 16-4: Timer3/5/7 Interrupt Enable Bits22116.7 Resetting Timer3/5/7 Using the ECCP Special Event Trigger221TABLE 16-5: Registers Associated with Timer3/5/7 as a Timer/Counter22217.0 Timer4/6/8/10/12 Modules22317.1 Timer4/6/8/10/12 Operation223TABLE 17-1: Timer4/6/8/10/12 Flag Bits223TABLE 17-2: Timer4/6/8/10/12 Interrupt Enable Bits223Register 17-1: TxCON: Timerx Control Register22417.2 Timer4/6/8/10/12 Interrupt22417.3 Output of TMRx224FIGURE 17-1: Timer4 Block Diagram224TABLE 17-3: Registers Associated with Timer4/6/8/10/12 as a Timer/Counter22518.0 Real-Time Clock and Calendar (RTCC)227FIGURE 18-1: RTCC Block Diagram22718.1 RTCC Module Registers228RTCC Control Registers228RTCC Value Registers228Alarm Value Registers22818.1.1 RTCC Control Registers229Register 18-1: RTCCFG: RTCC Configuration Register(1)229Register 18-2: RTCCAL: RTCC Calibration Register230Register 18-3: PADCFG1: Pad Configuration Register230Register 18-4: ALRMCFG: Alarm Configuration Register231Register 18-5: ALRMRPT: Alarm Repeat Register23218.1.2 RTCVALH and RTCVALL Register Mappings232Register 18-6: Reserved Register232Register 18-7: Year: Year Value Register(1)232Register 18-8: MontH: Month Value Register(1)233Register 18-9: Day: Day Value Register(1)233Register 18-10: Weekday: Weekday Value Register(1)233Register 18-11: Hour: Hour Value Register(1)234Register 18-12: MINUTE: Minute Value Register234Register 18-13: SECOND: Second Value Register23418.1.3 ALRMVALH and ALRMVALL Register Mappings235Register 18-14: ALRMMNTH: Alarm Month Value Register(1)235Register 18-15: ALRMDAY: Alarm Day Value Register(1)235Register 18-16: ALRMWd: Alarm Weekday Value Register(1)235Register 18-17: ALRMHr: Alarm Hours Value Register(1)236Register 18-18: ALRMMIN: Alarm Minutes Value Register236Register 18-19: ALRMSEC: Alarm Seconds Value Register23618.1.4 RTCEN Bit Write23718.2 Operation23718.2.1 Register Interface237FIGURE 18-2: Timer Digit Format237FIGURE 18-3: Alarm Digit Format23718.2.2 Clock Source238FIGURE 18-4: Clock Source Multiplexing23818.2.3 Digit Carry Rules238TABLE 18-1: Day of Week Schedule238TABLE 18-2: Day to Month Rollover Schedule23818.2.4 Leap Year23918.2.5 General Functionality23918.2.6 Safety Window for Register Reads and Writes23918.2.7 Write Lock239EXAMPLE 18-1: Setting the RTCWREN Bit23918.2.8 Register Mapping239TABLE 18-3: RTCVALH and RTCVALL Register Mapping239TABLE 18-4: ALRMVAL Register Mapping24018.2.9 Calibration240EQUATION 18-1: Converting Error Clock Pulses24018.3 Alarm24018.3.1 Configuring the Alarm240FIGURE 18-5: Alarm Mask Settings24118.3.2 Alarm Interrupt241FIGURE 18-6: Timer Pulse Generation24218.4 Sleep Mode24218.5 Reset24218.5.1 Device Reset24218.5.2 Power-on Reset (POR)24218.6 Register Maps243TABLE 18-5: RTCC Control Registers243TABLE 18-6: RTCC Value Registers243TABLE 18-7: Alarm Value Registers24319.0 Capture/Compare/PWM (CCP) Modules245Register 19-1: CCPxCON: CCPx Control Register (CCP4-CCP10 Modules)(1)245Register 19-2: CCPTMRS1: CCP Timer Select Register 1246Register 19-3: CCPTMRS2: CCP Timer Select Register 2247Register 19-4: CCPRxL: CCPx Period Low Byte Register248Register 19-5: CCPRxH: CCPx Period High Byte Register24819.1 CCP Module Configuration24919.1.1 CCP Modules and Timer Resources249TABLE 19-1: CCP Mode – Timer Resource249TABLE 19-2: Timer Assignments for CCP Modules 4, 5, 6 and 7249TABLE 19-3: Timer Assignments for CCP Modules 8, 9 and 1024919.1.2 Open-Drain Output Option25019.1.3 Pin Assignment For CCP6, CCP7, CCP8 and CCP9250TABLE 19-4: CCP Pin Assignment25019.2 Capture Mode25019.2.1 CCP Pin Configuration25019.2.2 Timer1/3/5/7 Mode Selection250FIGURE 19-1: Capture Mode Operation Block Diagram25119.2.3 Software Interrupt25119.2.4 CCP Prescaler251EXAMPLE 19-1: Changing Between Capture Prescalers25119.3 Compare Mode25219.3.1 CCP Pin Configuration25219.3.2 Timer1/3/5/7 Mode Selection25219.3.3 Software Interrupt Mode25219.3.4 Special Event Trigger252FIGURE 19-2: Compare Mode Operation Block Diagram253TABLE 19-5: Registers Associated with Capture, Compare, Timer1/3/5/725319.4 PWM Mode255FIGURE 19-3: Simplified PWM Block Diagram255FIGURE 19-4: PWM Output25519.4.1 PWM Period255EQUATION 19-1:25519.4.2 PWM Duty Cycle256EQUATION 19-2:256EQUATION 19-3:256TABLE 19-6: Example PWM Frequencies and Resolutions at 40 MHz25619.4.3 Setup for PWM Operation256TABLE 19-7: Registers Associated with PWM and Timers25620.0 Enhanced Capture/Compare/PWM (ECCP) Module259Register 20-1: CCPxCON: Enhanced Capture/Compare/PWMx Control260Register 20-2: CCPTMRS0: CCP Timer Select 0 Register26120.1 ECCP Outputs and Configuration26220.1.1 ECCP Module and Timer Resources262TABLE 20-1: ECCP Mode – Timer Resource26220.1.2 ECCP Pin Assignment26220.2 Capture Mode263TABLE 20-2: ECCP1/2/3 Interrupt Flag Bits26320.2.1 ECCP Pin Configuration26320.2.2 Timer1/2/3/4/6/8/10/12 Mode Selection26320.2.3 Software Interrupt26320.2.4 ECCP Prescaler263EXAMPLE 20-1: Changing Between Capture Prescalers263FIGURE 20-1: Capture Mode Operation Block Diagram26320.3 Compare Mode26420.3.1 ECCP Pin Configuration26420.3.2 Timer1/2/3/4/6/8/10/12 Mode Selection26420.3.3 Software Interrupt Mode26420.3.4 Special Event Trigger264FIGURE 20-2: Compare Mode Operation Block Diagram26420.4 PWM (Enhanced Mode)265FIGURE 20-3: Example Simplified Block Diagram of the Enhanced PWM Mode265TABLE 20-3: Example Pin Assignments for Various PWM Enhanced Modes266FIGURE 20-4: Example PWM (enhanced Mode) Output Relationships (Active-High State)266FIGURE 20-5: Example Enhanced PWM Output Relationships (Active-Low State)26720.4.1 Half-Bridge Mode268FIGURE 20-6: Example of Half-Bridge PWM Output268FIGURE 20-7: Example of Half-Bridge Applications26820.4.2 Full-Bridge Mode269FIGURE 20-8: Example of Full-Bridge Application269FIGURE 20-9: Example of Full-Bridge PWM Output270FIGURE 20-10: Example of PWM Direction Change271FIGURE 20-11: Example of PWM Direction Change at Near 100% Duty Cycle(1)27220.4.3 Start-up Considerations27220.4.4 Enhanced PWM Auto-shutdown mode272Register 20-3: ECCPxAS: ECCPx Auto-Shutdown Control Register273FIGURE 20-12: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)27420.4.5 Auto-Restart Mode274FIGURE 20-13: PWM Auto-shutdown With Auto-Restart Enabled (PxRSEN = 1)27420.4.6 Programmable Dead-Band Delay Mode275FIGURE 20-14: Example of Half-Bridge PWM Output275FIGURE 20-15: Example of Half-Bridge Applications275Register 20-4: ECCPxDEL: Enhanced PWM Control Register27620.4.7 Pulse Steering Mode276Register 20-5: PSTRxCON: Pulse Steering Control(1)277FIGURE 20-16: Simplified Steering Block Diagram278FIGURE 20-17: Example of Steering Event at End of Instruction (STRSYNC = 0)278FIGURE 20-18: Example of Steering Event at Beginning of Instruction (STRSYNC = 1)27820.4.8 Operation in Power-Managed Modes27920.4.9 Effects of a Reset279TABLE 20-4: Registers Associated with ECCP1/2/3 Module and Timer1/2/3/4/6/8/10/1227921.0 Master Synchronous Serial Port (MSSP) Module28121.1 Master SSP (MSSP) Module Overview28121.2 Control Registers28121.3 SPI Mode281FIGURE 21-1: MSSP Block Diagram (SPI Mode)28121.3.1 Registers282Register 21-1: SSPxSTAT: MSSPx Status Register (SPI Mode)282Register 21-2: SSPxCON1: MSSPx Control Register 1 (SPI Mode)28321.3.2 Operation28421.3.3 OPEN-DRAIN OUTPUT OPTION284EXAMPLE 21-1: Loading the SSP1BUF (SSP1SR) Register28421.3.4 Enabling SPI I/O28521.3.5 Typical Connection285FIGURE 21-2: SPI Master/Slave Connection28521.3.6 Master Mode286FIGURE 21-3: SPI Mode Waveform (Master Mode)28621.3.7 Slave Mode28721.3.8 Slave Select Synchronization287FIGURE 21-4: Slave Synchronization Waveform287FIGURE 21-5: SPI Mode Waveform (Slave Mode with CKE = 0)288FIGURE 21-6: SPI Mode Waveform (Slave Mode with CKE = 1)28821.3.9 Operation in Power-Managed Modes28921.3.10 Effects of a Reset28921.3.11 Bus Mode Compatibility289TABLE 21-1: SPI Bus Modes28921.3.12 SPI Clock Speed and Module Interactions289TABLE 21-2: Registers Associated with SPI Operation29021.4 I2C Mode291FIGURE 21-7: MSSP Block Diagram (I2C™ Mode)29121.4.1 Registers291Register 21-3: SSPxSTAT: MSSPx Status Register (I2C™ Mode)292Register 21-4: SSPxCON1: MSSPx Control Register 1 (I2C™ Mode)293Register 21-5: SSPxCON2: MSSPx Control Register 2 (I2C™ Master Mode)294Register 21-6: SSPxCON2: MSSPx Control Register 2 (I2C™ Slave Mode)295Register 21-7: SSPxMSK: I2C™ Slave Address Mask Register (7-bit Masking Mode)(1)29521.4.2 Operation29621.4.3 Slave Mode296EXAMPLE 21-2: Address Masking Examples in 5-bit Masking Mode297EXAMPLE 21-3: Address Masking Examples in 7-Bit Masking Mode298FIGURE 21-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)300FIGURE 21-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Address)301FIGURE 21-10: I2C™ Slave Mode Timing (Transmission, 7-bit Address)302FIGURE 21-11: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Address)303FIGURE 21-12: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)304FIGURE 21-13: I2C™ Slave Mode Timing (Transmission, 10-bit Address)30521.4.4 Clock Stretching306FIGURE 21-14: Clock Synchronization Timing307FIGURE 21-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)308FIGURE 21-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)30921.4.5 General Call Address Support310FIGURE 21-17: Slave Mode General Call Address Sequence (7 or 10-bit Addressing Mode)31021.4.6 Master Mode311FIGURE 21-18: MSSP Block Diagram (I2C™ Master Mode)31121.4.7 Baud Rate313FIGURE 21-19: Baud Rate Generator Block Diagram313TABLE 21-3: I2C™ Clock Rate w/BRG313FIGURE 21-20: Baud Rate Generator Timing with Clock Arbitration31421.4.8 I2C™ Master Mode Start Condition Timing315FIGURE 21-21: First Start Bit Timing31521.4.9 I2C™ Master Mode Repeated Start Condition Timing316FIGURE 21-22: Repeated Start Condition Waveform31621.4.10 I2C™ Master Mode Transmission31721.4.11 I2C™ Master Mode Reception317FIGURE 21-23: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Address)318FIGURE 21-24: I2C™ Master Mode Waveform (Reception, 7-bit Address)31921.4.12 Acknowledge Sequence Timing32021.4.13 Stop Condition Timing320FIGURE 21-25: Acknowledge Sequence Waveform320FIGURE 21-26: Stop Condition Receive or Transmit Mode32021.4.14 Sleep Operation32121.4.15 Effects of a Reset32121.4.16 Multi-master Mode32121.4.17 Multi -master Communication, Bus Collision and Bus Arbitration321FIGURE 21-27: Bus Collision Timing for Transmit and Acknowledge321FIGURE 21-28: Bus Collision During Start Condition (SDAx Only)322FIGURE 21-29: Bus Collision During Start Condition (SCLx = 0)323FIGURE 21-30: BRG Reset Due to SDAx Arbitration During Start Condition323FIGURE 21-31: Bus Collision During a Repeated Start Condition (Case 1)324FIGURE 21-32: Bus Collision During Repeated Start Condition (Case 2)324FIGURE 21-33: Bus Collision During a Stop Condition (Case 1)325FIGURE 21-34: Bus Collision During a Stop Condition (Case 2)325TABLE 21-4: Registers Associated with I2C™ Operation32622.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)327Register 22-1: TXSTAx: Transmit Status And Control Register328Register 22-2: RCSTAx: Receive Status And Control Register329Register 22-3: BAUDCONx: Baud Rate Control Register33022.1 Baud Rate Generator (BRG)33122.1.1 Operation in Power-Managed Modes33122.1.2 Sampling331TABLE 22-1: Baud Rate Formulas331EXAMPLE 22-1: Calculating Baud Rate Error332TABLE 22-2: Registers Associated with Baud Rate Generator332TABLE 22-3: Baud Rates for Asynchronous Modes33322.1.3 Auto-Baud Rate Detect335TABLE 22-4: BRG Counter Clock Rates335FIGURE 22-1: Automatic Baud Rate Calculation336FIGURE 22-2: BRG Overflow Sequence33622.2 EUSART Asynchronous Mode33722.2.1 EUSART Asynchronous Transmitter337FIGURE 22-3: EUSART Transmit Block Diagram338FIGURE 22-4: Asynchronous Transmission338FIGURE 22-5: Asynchronous Transmission (Back-to-Back)338TABLE 22-5: Registers Associated with Asynchronous Transmission33922.2.2 EUSART Asynchronous Receiver34022.2.3 Setting Up 9-bit Mode with Address Detect340FIGURE 22-6: EUSART Receive Block Diagram340FIGURE 22-7: Asynchronous Reception341TABLE 22-6: Registers Associated with Asynchronous Reception34122.2.4 Auto-Wake-up on Sync Break Character342FIGURE 22-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation343FIGURE 22-9: Auto-Wake-up Bit (WUE) Timings During Sleep34322.2.5 Break Character Sequence34422.2.6 Receiving A Break Character344FIGURE 22-10: Send Break Character Sequence34422.3 EUSART Synchronous Master Mode34522.3.1 EUSART Synchronous Master Transmission345FIGURE 22-11: Synchronous Transmission345FIGURE 22-12: Synchronous Transmission (Through TXEN)346TABLE 22-7: Registers Associated with Synchronous Master Transmission34622.3.2 EUSART Synchronous Master Reception347FIGURE 22-13: Synchronous Reception (Master Mode, SREN)347TABLE 22-8: Registers Associated with Synchronous Master Reception34822.4 EUSART Synchronous Slave Mode34922.4.1 EUSART Synchronous Slave Transmission349TABLE 22-9: Registers Associated with Synchronous Slave Transmission34922.4.2 EUSART Synchronous Slave Reception350TABLE 22-10: Registers Associated with Synchronous Slave Reception35023.0 12-Bit Analog-to-Digital Converter (A/D) Module35123.1 Differential A/D Converter351FIGURE 23-1: Differential Channel Measurement351FIGURE 23-2: Single Channel Measurement35123.2 A/D Registers35223.2.1 A/D Control Registers352Register 23-1: ADCON0: A/D Control Register 0352Register 23-2: ADCON1: A/D Control Register 1353Register 23-3: ADCON2: A/D Control Register 235423.2.2 A/D Result Registers355FIGURE 23-3: A/D Result Justification355Register 23-4: ADRESH: A/D Result High Byte Register, Left Justified (ADFM = 0)356Register 23-5: ADRESL: A/D Result High Byte Register, Left Justified (ADFM = 0)356Register 23-6: ADRESH: A/D Result High Byte Register, Right Justified (ADFM = 1)357Register 23-7: ADRESL: A/D Result Low Byte Register, Right Justified (ADFM = 1)357Register 23-8: ANCON0: A/D Port Configuration Register 0358Register 23-9: ANCON1: A/D Port Configuration Register 1358Register 23-10: ANCON2: A/D Port Configuration Register 2359FIGURE 23-4: A/D Block Diagram360FIGURE 23-5: Analog Input Model36123.3 A/D Acquisition Requirements362EQUATION 23-1: Acquisition Time362EQUATION 23-2: A/D Minimum Charging Time362EQUATION 23-3: Calculating the Minimum Required Acquisition Time36223.4 Selecting and Configuring Automatic Acquisition Time36323.5 Selecting the A/D Conversion Clock363TABLE 23-1: Tad vs. Device Operating Frequencies36323.6 Configuring Analog Port Pins36323.7 A/D Conversions364FIGURE 23-6: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)364FIGURE 23-7: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)36423.8 Use of the Special Event Triggers36523.9 Operation in Power-Managed Modes365TABLE 23-2: Registers Associated with A/D Module36624.0 Comparator Module36724.1 Registers367FIGURE 24-1: Comparator Simplified Block Diagram367Register 24-1: CMxCON: Comparator Control x Register368Register 24-2: CMSTAT: Comparator Status Register36924.2 Comparator Operation370FIGURE 24-2: Single Comparator37024.3 Comparator Response Time37024.4 Analog Input Connection Considerations370FIGURE 24-3: Comparator Analog Input Model37024.5 Comparator Control and Configuration371TABLE 24-1: Comparator Inputs and Outputs37124.5.1 Comparator Enable and Input selection37124.5.2 Comparator Enable and OUtput Selection371FIGURE 24-4: Comparator Configurations37224.6 Comparator Interrupts373TABLE 24-2: Comparator Interrupt Generation37324.7 Comparator Operation During Sleep37424.8 Effects of a Reset374TABLE 24-3: Registers Associated with Comparator Module37425.0 Comparator Voltage Reference Module37525.1 Configuring the Comparator Voltage Reference375EQUATION 25-1:375Register 25-1: CVRCON: Comparator Voltage Reference Control Register375FIGURE 25-1: Comparator Voltage Reference Block Diagram37625.2 Voltage Reference Accuracy/Error37625.3 Operation During Sleep37625.4 Effects of a Reset37625.5 Connection Considerations376FIGURE 25-2: Comparator Voltage Reference Output Buffer Example377TABLE 25-1: Registers Associated with Comparator Voltage Reference37726.0 High/Low-Voltage Detect (HLVD)379Register 26-1: HLVDCON: High/Low-Voltage Detect Control Register37926.1 Operation380FIGURE 26-1: HLVD Module Block Diagram (with External Input)38026.2 HLVD Setup38126.3 Current Consumption38126.4 HLVD Start-up Time381FIGURE 26-2: Low-Voltage Detect Operation (VDIRMAG = 0)382FIGURE 26-3: High-Voltage Detect Operation (VDIRMAG = 1)38326.5 Applications383FIGURE 26-4: Typical Low-Voltage Detect Application38326.6 Operation During Sleep38426.7 Effects of a Reset384TABLE 26-1: Registers Associated with High/Low-Voltage Detect Module38427.0 Charge Time Measurement Unit (CTMU)385FIGURE 27-1: CTMU Block Diagram38527.1 CTMU Registers386Register 27-1: CTMUCONH: CTMU Control High Register386Register 27-2: CTMUCONL: CTMU Control Low Register387Register 27-3: CTMUICON: CTMU current Control Register38827.2 CTMU Operation38927.2.1 Theory of Operation38927.2.2 Current Source38927.2.3 Edge Selection and Control38927.2.4 Edge Status38927.2.5 Interrupts39027.3 CTMU Module Initialization39027.4 Calibrating the CTMU Module39027.4.1 Current Source Calibration390FIGURE 27-2: CTMU Current Source Calibration Circuit391EXAMPLE 27-1: Setup for CTMU Calibration Routines392EXAMPLE 27-2: Current Calibration Routine39327.4.2 Capacitance Calibration394EXAMPLE 27-3: Capacitance Calibration Routine39527.5 Measuring Capacitance with the CTMU39627.5.1 Absolute Capacitance Measurement39627.5.2 Relative Charge Measurement396EXAMPLE 27-4: Routine for Capacitive Touch Switch39727.6 Measuring Time with the CTMU Module398FIGURE 27-3: Typical Connections and Internal Configuration for Time Measurement39827.7 Creating a Delay with the CTMU Module399FIGURE 27-4: Typical Connections and Internal Configuration for Pulse Delay Generation39927.8 Measuring Temperature with the CTMU Module400EXAMPLE 27-5: Routine for Temperature Measurement Using Internal Diode40027.9 Operation During Sleep/Idle Modes40127.9.1 Sleep Mode40127.9.2 Idle Mode40127.10 Effects of a Reset on CTMU401TABLE 27-1: Registers Associated with CTMU Module40128.0 Special Features of the CPU40328.1 Configuration Bits403TABLE 28-1: Configuration Bits and Device IDs404Register 28-1: CONFIG1L: Configuration Register 1 lOW (Byte Address 300000h)405Register 28-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)406Register 28-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)407Register 28-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)408Register 28-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)409Register 28-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)410Register 28-7: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)411Register 28-8: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)412Register 28-9: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)413Register 28-10: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)414Register 28-11: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)415Register 28-12: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)416Register 28-13: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)417Register 28-14: DEVID1: Device ID Register 1 for the PIC18F87K22 Family418Register 28-15: DEVID2: Device ID Register 2 for the PIC18F87K22 Family41828.2 Watchdog Timer (WDT)419FIGURE 28-1: WDT Block Diagram41928.2.1 Control Register420Register 28-16: WDTCON: Watchdog Timer Control Register420TABLE 28-2: Summary of Watchdog Timer Registers42028.3 On-Chip Voltage Regulator42128.3.1 Regulator Enable/Disable By Hardware421FIGURE 28-2: Connections for the On-chip Regulator42128.3.2 Operation of Regulator in Sleep422TABLE 28-3: Sleep Mode Regulator Settings(1)42228.4 Two-Speed Start-up42328.4.1 Special Considerations for Using Two-Speed Start-up423FIGURE 28-3: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)42328.5 Fail-Safe Clock Monitor424FIGURE 28-4: FSCM Block Diagram42428.5.1 FSCM and the Watchdog Timer42428.5.2 Exiting Fail-Safe Operation424FIGURE 28-5: FSCM Timing Diagram42528.5.3 FSCM Interrupts in Power-Managed Modes42528.5.4 POR or Wake From Sleep42528.6 Program Verification and Code Protection426FIGURE 28-6: Code-Protected Program Memory for the PIC18F87K22 Family(1)426TABLE 28-4: Summary of Code Protection Registers42728.6.1 Program Memory Code Protection427FIGURE 28-7: Table Write (WRTx) Disallowed427FIGURE 28-8: External Block Table Read (EBTRx) Disallowed428FIGURE 28-9: External Block Table Read (EBTRx) Allowed42828.6.2 Data EEPROM Code Protection42928.6.3 Configuration Register Protection42928.7 ID Locations42928.8 In-Circuit Serial Programming42928.9 In-Circuit Debugger429TABLE 28-5: Debugger Resources42929.0 Instruction Set Summary43129.1 Standard Instruction Set431TABLE 29-1: Opcode Field Descriptions432FIGURE 29-1: General Format for Instructions433TABLE 29-2: PIC18F87K22 Family Instruction Set43429.1.1 Standard Instruction Set43729.2 Extended Instruction Set47329.2.1 Extended Instruction Syntax473TABLE 29-3: Extensions to the PIC18 Instruction Set47329.2.2 Extended Instruction Set47429.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode47829.2.4 Considerations When Enabling the Extended Instruction Set47829.2.5 Special Considerations with Microchip MPLAB® IDE Tools48030.0 Development Support48131.0 Electrical Characteristics485Absolute Maximum Ratings(†)485FIGURE 31-1: Voltage-frequency Graph, Regulator Enabled (Industrial/Extended)(1)486FIGURE 31-2: Voltage-frequency Graph, Regulator Disabled (Industrial/Extended)(1,2)48631.1 DC Characteristics: Supply Voltage PIC18F87K22 Family (Industrial/Extended)48731.2 DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended)48831.3 DC Characteristics: PIC18F87K22 Family (Industrial/Extended)49731.4 DC Characteristics: CTMU Current Source Specifications498TABLE 31-1: Memory Programming Requirements499TABLE 31-2: Comparator Specifications500TABLE 31-3: Voltage Reference Specifications500TABLE 31-4: Internal Voltage Regulator Specifications50031.5 AC (Timing) Characteristics50131.5.1 Timing Parameter Symbology50131.5.2 Timing Conditions502TABLE 31-5: Temperature and Voltage Specifications – AC502FIGURE 31-3: Load Conditions for Device Timing Specifications50231.5.3 Timing Diagrams and Specifications503FIGURE 31-4: External Clock Timing503TABLE 31-6: External Clock Timing Requirements503TABLE 31-7: PLL Clock Timing Specifications (Vdd = 1.8V to 5.5V)504TABLE 31-8: Internal RC Accuracy (INTOSC)504FIGURE 31-5: CLKO and I/O Timing505TABLE 31-9: CLKO and I/O Timing Requirements505FIGURE 31-6: Program Memory Fetch Timing Diagram (8-Bit)506TABLE 31-10: Program Memory Fetch Timing Requirements (8-Bit)506FIGURE 31-7: Program Memory Read Timing Diagram507TABLE 31-11: CLKO and I/O Timing Requirements507FIGURE 31-8: Program Memory Write Timing Diagram508TABLE 31-12: Program Memory Write Timing Requirements508FIGURE 31-9: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing509FIGURE 31-10: Brown-out Reset Timing509TABLE 31-13: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements510FIGURE 31-11: High/Low-Voltage Detect Characteristics511TABLE 31-14: High/Low-Voltage Detect Characteristics511FIGURE 31-12: Timer0 and Timer1 External Clock Timings512TABLE 31-15: Timer0 and Timer1 External Clock Requirements512FIGURE 31-13: Capture/Compare/PWM Timings (ECCP1, ECCP2 Modules)513TABLE 31-16: Capture/Compare/PWM Requirements (ECCP1, ECCP2 Modules)513FIGURE 31-14: Example SPI Master Mode Timing (CKE = 0)514TABLE 31-17: Example SPI Mode Requirements (Master Mode, Cke = 0)514FIGURE 31-15: Example SPI Master Mode Timing (CKE = 1)515TABLE 31-18: Example SPI Mode Requirements (Master Mode, CKE = 1)515FIGURE 31-16: Example SPI Slave Mode Timing (CKE = 0)516TABLE 31-19: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)516FIGURE 31-17: Example SPI Slave Mode Timing (CKE = 1)517TABLE 31-20: Example SPI Slave Mode Requirements (CKE = 1)517FIGURE 31-18: I2C™ Bus Start/Stop Bits Timing518TABLE 31-21: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)518FIGURE 31-19: I2C™ Bus Data Timing519TABLE 31-22: I2C™ Bus Data Requirements (Slave Mode)519FIGURE 31-20: MSSP I2C™ Bus Start/Stop Bits Timing Waveforms520TABLE 31-23: MSSP I2C™ Bus Start/Stop Bits Requirements520FIGURE 31-21: MSSP I2C™ Bus Data Timing520TABLE 31-24: MSSP I2C™ Bus Data Requirements521FIGURE 31-22: EUSART Synchronous Transmission (Master/Slave) Timing522TABLE 31-25: EUSART/AUSART Synchronous Transmission Requirements522FIGURE 31-23: EUSART/AUSART Synchronous Receive (Master/Slave) Timing522TABLE 31-26: EUSART/AUSART Synchronous Receive Requirements522TABLE 31-27: A/D Converter Characteristics: PIC18F87K22 Family (Industrial)523FIGURE 31-24: A/D Conversion Timing524TABLE 31-28: A/D Conversion Requirements52432.0 Packaging Information52532.1 Package Marking Information52532.2 Package Details526Appendix A: Revision History533Revision A (November 2009)533Revision B (May 2010)533Revision C (March 2011)533Revision D (June 2011)533Appendix B: Migration From PIC18F87J11 and PIC18F8722 to PIC18F87K22534TABLE B-1: Notable Differences Between PIC18F87K22, PIC18F87J11 and PIC18F8722 Families534INDEX535The Microchip Web Site547Customer Change Notification Service547Customer Support547Reader Response548Product Identification System549Worldwide Sales and Service550Size: 4.34 MBPages: 550Language: EnglishOpen manual