Microchip Technology Microstick for the 5V PIC24F K-series DM240013-2 User Manuals

Table of Contents

• Analog Peripheral Features

  1
• High-Performance RISC CPU

  1
• Multiple/Single Capture Compare Peripheral (MCCP/SCCP) Features

  1
• Peripheral Features

  3
• Special Microcontroller Features

  3
• Pin Diagrams

  4
• Pin Diagrams (Continued)

  5
• Pin Diagrams (Continued)

  6
• Pin Diagrams (Continued)

  7
• Pin Diagrams (Continued)

  8
• Pin Diagrams (Continued)

  9
• Table of Contents

  10
• Most Current Data Sheet

  11
• Errata

  11
• Customer Notification System

  11
• 1.0 Device Overview

  13
  • 1.1 Core Features

    13
    • 1.1.1 16-Bit Architecture

      13
    • 1.1.2 Power-saving Technology

      13
    • 1.1.3 OSCILLATOR OPTIONS AND FEATURES

      13
    • 1.1.4 EASY MIGRATION

      14
  • 1.2 Other Special Features

    14
  • 1.3 Details on Individual Family Members

    14
    • TABLE 1-1: Device Features for the PIC24F16KM204 Family

      15
    • TABLE 1-2: Device Features for the PIC24F16KM104 Family

      16
    • TABLE 1-3: Device Features for the PIC24FV16KM204 Family

      17
    • TABLE 1-4: Device Features for the PIC24FV16KM104 Family

      18
    • FIGURE 1-1: PIC24FXXXXX Family General Block Diagrams

      19
    • TABLE 1-5: PIC24FV16KM204 Family Pinout Description

      20
• 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers

  29
  • 2.1 Basic Connection Requirements

    29
    • FIGURE 2-1: Recommended Minimum connections

      29
  • 2.2 Power Supply Pins

    30
    • 2.2.1 Decoupling Capacitors

      30
    • 2.2.2 Tank Capacitors

      30
  • 2.3 Master Clear (MCLR) Pin

    30
    • FIGURE 2-2: Example of MCLR Pin Connections

      30
  • 2.4 Voltage Regulator Pin (Vcap)

    31
    • FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap

      31
    • TABLE 2-1: Suitable Capacitor Equivalents

      31
    • 2.4.1 Considerations for Ceramic Capacitors

      32
      • FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics

        32
  • 2.5 ICSP Pins

    32
  • 2.6 External Oscillator Pins

    33
  • 2.7 Unused I/Os

    33
    • FIGURE 2-5: Suggested Placement of the Oscillator Circuit

      33
• 3.0 CPU

  35
  • 3.1 Programmer’s Model

    35
    • FIGURE 3-1: PIC24F CPU Core Block Diagram

      36
    • TABLE 3-1: CPU Core Registers

      36
    • FIGURE 3-2: Programmer’s Model

      37
  • 3.2 CPU Control Registers

    38
    • Register 3-1: SR: ALU STATUS Register

      38
    • Register 3-2: CORCON: CPU Control Register

      39
  • 3.3 Arithmetic Logic Unit (ALU)

    39
    • 3.3.1 Multiplier

      39
    • 3.3.2 Divider

      40
    • 3.3.3 Multi-Bit Shift Support

      40
      • TABLE 3-2: Instructions that Use the Single and Multi-Bit Shift Operation

        40
• 4.0 Memory Organization

  41
  • 4.1 Program Address Space

    41
    • FIGURE 4-1: Program Space Memory Map for PIC24FXXXXX Family Devices

      41
    • 4.1.1 Program Memory Organization

      42
    • 4.1.2 Hard Memory Vectors

      42
    • 4.1.3 Data EEPROM

      42
    • 4.1.4 Device Configuration Words

      42
      • TABLE 4-1: Device Configuration Words for PIC24FXXXXX Family Devices

        42
      • FIGURE 4-2: Program Memory Organization

        42
  • 4.2 Data Address Space

    43
    • 4.2.1 Data Space Width

      43
      • FIGURE 4-3: Data Space Memory Map for PIC24FXXXXX Family Devices(3)

        43
    • 4.2.2 Data Memory Organization and Alignment

      44
    • 4.2.3 Near Data Space

      44
    • 4.2.4 SFR Space

      44
      • TABLE 4-2: Implemented Regions of SFR Data Space

        44
      • TABLE 4-3: CPU CORE Registers Map

        45
      • TABLE 4-4: ICN Register Map

        46
      • TABLE 4-5: Interrupt Controller Register Map

        47
      • TABLE 4-6: Timer1 Register Map

        48
      • TABLE 4-7: CLC1-2 Register Map

        48
      • TABLE 4-8: MCCP1 Register Map

        49
      • TABLE 4-9: MCCP2 Register Map

        50
      • TABLE 4-10: MCCP3 Register Map

        51
      • TABLE 4-11: SCCP4 Register Map

        52
      • TABLE 4-12: SCCP5 Register Map

        53
      • TABLE 4-13: MSSP1 (I2C™/SPI) Register Map

        54
      • TABLE 4-14: MSSP2 (I2C™/SPI) Register Map

        54
      • TABLE 4-15: UART1 Register Map

        55
      • TABLE 4-16: UART2 Register Map

        55
      • TABLE 4-17: OP AMP 1 Register Map

        56
      • TABLE 4-18: OP AMP 2 Register Map

        56
      • TABLE 4-19: DAC1 Register Map

        56
      • TABLE 4-20: DAC2 Register Map

        56
      • TABLE 4-21: PORTA Register Map

        57
      • TABLE 4-22: PORTb Register Map

        57
      • TABLE 4-23: PORTC Register Map

        57
      • TABLE 4-24: Pad Configuration Register Map

        58
      • TABLE 4-25: A/D Register Map

        59
      • TABLE 4-26: CTMU Register Map

        60
      • TABLE 4-27: ANSEL Register Map

        60
      • TABLE 4-28: Real-Time Clock and Calendar Register Map

        60
      • TABLE 4-29: Comparator Register Map

        61
      • TABLE 4-30: Band gap Buffer Control Register Map

        61
      • TABLE 4-31: Clock Control Register Map

        62
      • TABLE 4-32: NVM Register Map

        62
      • TABLE 4-33: Ultra Low-Power Wake-up Register Map

        62
      • TABLE 4-34: PMD Register Map

        62
    • 4.2.5 Software Stack

      63
      • FIGURE 4-4: CALL Stack Frame

        63
  • 4.3 Interfacing Program and Data Memory Spaces

    63
    • 4.3.1 Addressing Program Space

      63
      • TABLE 4-35: Program Space Address Construction

        64
      • FIGURE 4-5: Data Access From Program Space Address Generation

        64
    • 4.3.2 Data Access From Program Memory and Data EEPROM Memory Using Table Instructions

      65
      • FIGURE 4-6: Accessing Program Memory with Table Instructions

        65
    • 4.3.3 Reading Data From Program Memory Using Program Space Visibility

      66
      • FIGURE 4-7: Program Space Visibility Operation

        66
• 5.0 Flash Program Memory

  67
  • 5.1 Table Instructions and Flash Programming

    67
    • FIGURE 5-1: Addressing for Table Registers

      67
  • 5.2 RTSP Operation

    68
  • 5.3 Enhanced In-Circuit Serial Programming

    68
  • 5.4 Control Registers

    68
  • 5.5 Programming Operations

    68
    • Register 5-1: NVMCON: Flash Memory Control Register

      69
    • 5.5.1 Programming Algorithm for Flash Program Memory

      70
      • EXAMPLE 5-1: Erasing a Program Memory Row – Assembly Language Code

        70
      • EXAMPLE 5-2: Erasing a Program Memory Row – ‘C’ Language Code

        70
      • EXAMPLE 5-3: Loading the Write Buffers – Assembly Language Code

        71
      • EXAMPLE 5-4: Loading the Write Buffers – ‘C’ Language Code

        71
      • EXAMPLE 5-5: Initiating a Programming Sequence – Assembly Language Code

        72
      • EXAMPLE 5-6: Initiating a Programming Sequence – ‘C’ Language Code

        72
• 6.0 Data EEPROM Memory

  73
  • 6.1 NVMCON Register

    73
  • 6.2 NVMKEY Register

    73
    • EXAMPLE 6-1: Data EEPROM Unlock Sequence

      73
    • Register 6-1: NVMCON: Nonvolatile Memory Control Register

      74
  • 6.3 NVM Address Register

    75
    • FIGURE 6-1: Data EEPROM Addressing with TBLPAG and NVM Address Registers

      75
  • 6.4 Data EEPROM Operations

    75
    • 6.4.1 Erase Data EEPROM

      76
      • EXAMPLE 6-2: Single-Word Erase

        76
    • 6.4.2 Single-Word Write

      77
      • EXAMPLE 6-3: Data EEPROM Bulk Erase

        77
      • EXAMPLE 6-4: Single-Word Write to Data EEPROM

        77
    • 6.4.3 Reading the Data EEPROM

      78
      • EXAMPLE 6-5: Reading the Data EEPROM Using the TBLRD Command

        78
• 7.0 Resets

  79
  • FIGURE 7-1: Reset System Block Diagram

    79
  • Register 7-1: RCON: Reset Control Register(1)

    80
  • TABLE 7-1: Reset Flag Bit Operation

    81
  • 7.1 Clock Source Selection at Reset

    82
    • TABLE 7-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)

      82
  • 7.2 Device Reset Times

    82
    • TABLE 7-3: Reset Delay Times for Various Device Resets

      82
    • 7.2.1 POR and Long Oscillator Start-up Times

      83
    • 7.2.2 Fail-Safe Clock Monitor (FSCM) and Device Resets

      83
  • 7.3 Special Function Register Reset States

    83
  • 7.4 Brown-out Reset (BOR)

    83
    • 7.4.1 Low-Power BOR (LPBOR)

      83
    • 7.4.2 Software Enabled BOR

      84
    • 7.4.3 Detecting BOR

      84
    • 7.4.4 Disabling BOR in Sleep Mode

      84
• 8.0 Interrupt Controller

  85
  • 8.1 Interrupt Vector Table (IVT)

    85
    • 8.1.1 Alternate Interrupt Vector Table (AIVT)

      85
  • 8.2 Reset Sequence

    85
    • FIGURE 8-1: PIC24F Interrupt Vector Table

      86
    • TABLE 8-1: Trap Vector Details

      87
    • TABLE 8-2: Implemented Interrupt Vectors

      87
  • 8.3 Interrupt Control and Status Registers

    88
    • Register 8-1: SR: ALU STATUS Register

      89
    • Register 8-2: CORCON: CPU Control Register

      90
    • Register 8-3: INTCON1: Interrupt Control Register 1

      91
    • Register 8-4: INTCON2: Interrupt Control Register 2

      92
    • Register 8-5: IFS0: Interrupt Flag Status Register 0

      93
    • Register 8-6: IFS1: Interrupt Flag Status Register 1

      94
    • Register 8-7: IFS2: Interrupt Flag Status Register 2

      95
    • Register 8-8: IFS3: Interrupt Flag Status Register 3

      95
    • Register 8-9: IFS4: Interrupt Flag Status Register 4

      96
    • Register 8-10: IFS5: Interrupt Flag Status Register 5

      97
    • Register 8-11: IFS6: Interrupt Flag Status Register 6

      97
    • Register 8-12: IEC0: Interrupt Enable Control Register 0

      98
    • Register 8-13: IEC1: Interrupt Enable Control Register 1

      99
    • Register 8-14: IEC2: Interrupt Enable Control Register 2

      100
    • Register 8-15: IEC3: Interrupt Enable Control Register 3

      100
    • Register 8-16: IEC4: Interrupt Enable Control Register 4

      101
    • Register 8-17: Iec5: Interrupt ENABLE CONTROL Register 5

      102
    • Register 8-18: Iec6: Interrupt ENABLE CONTROL Register 5

      102
    • Register 8-19: IPC0: Interrupt Priority Control Register 0

      103
    • Register 8-20: IPC1: Interrupt Priority Control Register 1

      104
    • Register 8-21: IPC2: Interrupt Priority Control Register 2

      105
    • Register 8-22: IPC3: Interrupt Priority Control Register 3

      106
    • Register 8-23: IPC4: Interrupt Priority Control Register 4

      107
    • Register 8-24: IPC5: Interrupt Priority Control Register 5

      108
    • Register 8-25: IPC6: Interrupt Priority Control Register 6

      109
    • Register 8-26: IPC7: Interrupt Priority Control Register 7

      110
    • Register 8-27: IPC10: Interrupt Priority Control Register 10

      111
    • Register 8-28: IPC12: Interrupt Priority Control Register 12

      112
    • Register 8-29: IPC15: Interrupt Priority Control Register 15

      113
    • Register 8-30: IPC16: Interrupt Priority Control Register 16

      114
    • Register 8-31: IPC18: Interrupt Priority Control Register 18

      115
    • Register 8-32: IPC19: Interrupt Priority Control Register 19

      116
    • Register 8-33: IPC20: Interrupt Priority Control Register 20

      117
    • Register 8-34: IPC24: Interrupt Priority Control Register 24

      117
    • Register 8-35: INTTREG: Interrupt Control and Status Register

      118
  • 8.4 Interrupt Setup Procedures

    119
    • 8.4.1 Initialization

      119
    • 8.4.2 Interrupt Service Routine

      119
    • 8.4.3 Trap Service Routine (TSR)

      119
    • 8.4.4 Interrupt Disable

      119
• 9.0 Oscillator Configuration

  121
  • FIGURE 9-1: PIC24FXXXXX Family Clock Diagram

    121
  • 9.1 CPU Clocking Scheme

    122
  • 9.2 Initial Configuration on POR

    122
    • 9.2.1 Clock Switching Mode Configuration Bits

      122
      • TABLE 9-1: Configuration Bit Values for Clock Selection

        122
  • 9.3 Control Registers

    123
    • Register 9-1: OSCCON: Oscillator Control Register

      123
    • Register 9-2: CLKDIV: Clock Divider Register

      125
    • Register 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER

      126
  • 9.4 Clock Switching Operation

    127
    • 9.4.1 Enabling Clock Switching

      127
    • 9.4.2 Oscillator Switching Sequence

      127
      • EXAMPLE 9-1: Assembly Code Sequence For Clock Switching

        128
      • EXAMPLE 9-2: Basic ‘C’ Code Sequence For Clock Switching

        128
  • 9.5 Reference Clock Output

    128
    • Register 9-4: REFOCON: Reference Oscillator Control Register

      129
• 10.0 Power-Saving Features

  131
  • 10.1 Clock Frequency and Clock Switching

    131
  • 10.2 Instruction-Based Power-Saving Modes

    131
    • 10.2.1 Sleep Mode

      131
      • EXAMPLE 10-1: ‘C’ POWER-SAVING ENTRY

        131
    • 10.2.2 Idle Mode

      132
    • 10.2.3 Interrupts Coincident with Power Save Instructions

      132
  • 10.3 Ultra Low-Power Wake-up

    132
    • EXAMPLE 10-2: ULTRA LOW-POWER WAKE-UP INITIALIZATION

      132
    • FIGURE 10-1: Series Resistor

      132
    • Register 10-1: ULPWCON: ULPWU Control Register

      133
  • 10.4 Voltage Regulator-Based Power-Saving Features

    134
    • 10.4.1 Run Mode

      134
    • 10.4.2 Sleep Mode

      134
    • 10.4.3 Retention Regulator

      134
    • 10.4.4 Retention Sleep Mode

      134
      • TABLE 10-1: Voltage Regulation Configuration Settings for PIC24FXXXXX Family Devices

        134
  • 10.5 Doze Mode

    135
  • 10.6 Selective Peripheral Module Control

    135
• 11.0 I/O Ports

  137
  • 11.1 Parallel I/O (PIO) Ports

    137
    • FIGURE 11-1: Block Diagram of a Typical Shared Port Structure

      137
    • 11.1.1 Open-Drain Configuration

      138
  • 11.2 Configuring Analog Port Pins

    138
    • 11.2.1 ANALOG SELECTION REGISTER

      138
      • Register 11-1: ANSA: PORTA Analog Selection Register

        138
      • Register 11-2: ANSB: PORTB Analog Selection Register

        139
      • Register 11-3: ANSC: PORTC Analog Selection Register

        139
    • 11.2.2 I/O Port Write/Read Timing

      140
  • 11.3 Input Change Notification (ICN)

    140
    • EXAMPLE 11-1: Port Write/Read Example

      140
• 12.0 Timer1

  141
  • FIGURE 12-1: 16-Bit Timer1 Module Block Diagram

    141
  • Register 12-1: T1CON: Timer1 Control Register

    142
• 13.0 Capture/Compare/PWM/ Timer Modules (MCCP and SCCP)

  143
  • FIGURE 13-1: MCCPx/SCCPx Conceptual Block Diagram

    143
  • 13.1 Time Base Generator

    144
    • TABLE 13-1: Valid Timer Options for MCCPx/SCCPx Modes

      144
    • FIGURE 13-2: Timer Clock generator

      144
  • 13.2 General Purpose Timer

    145
    • TABLE 13-2: Timer Operation Mode

      145
    • 13.2.1 SYNC and Trigger Operation

      145
      • FIGURE 13-3: Dual 16-Bit Timer Mode

        145
      • FIGURE 13-4: 32-Bit Timer Mode

        146
  • 13.3 Output Compare Mode

    147
    • TABLE 13-3: Output Compare/PWM Modes

      147
    • FIGURE 13-5: Output Compare x Block Diagram

      147
  • 13.4 Input Capture Mode

    148
    • TABLE 13-4: Input Capture Modes

      148
    • FIGURE 13-6: Input Capture x Block Diagram

      148
  • 13.5 Auxiliary Output

    149
    • TABLE 13-5: Auxiliary Output

      149
    • Register 13-1: CCPxCON1L: CCPx Control 1 Low Registers

      150
    • Register 13-2: CCPxCON1H: CCPx Control 1 High Registers

      152
    • TABLE 13-6: Synchronization Sources

      153
    • Register 13-3: CCPxCON2L: CCPx Control 2 Low Registers

      154
    • TABLE 13-7: Auto-Shutdown and Gating Sources

      154
    • Register 13-4: CCPxCON2H: CCPx Control 2 High Registers

      155
    • Register 13-5: CCPxCON3L: CCPx Control 3 Low Registers (1)

      156
    • Register 13-6: CCPxCON3H: CCPx Control 3 High Registers

      157
    • Register 13-7: CCPxSTATL: CCPx STATUS Register

      158
• 14.0 Master Synchronous Serial Port (MSSP)

  159
  • 14.1 I/O Pin Configuration for SPI

    159
    • FIGURE 14-1: MSSPx Block Diagram (SPI Mode)

      160
    • FIGURE 14-2: SPI Master/Slave Connection

      160
    • FIGURE 14-3: MSSPx Block Diagram (I2C™ Mode)

      161
    • FIGURE 14-4: MSSPx Block Diagram (I2C™ Master Mode)

      161
    • Register 14-1: SSPxSTAT: MSSPx Status Register (SPI Mode)

      162
    • Register 14-2: SSPxSTAT: MSSPx Status Register (I2C™ Mode)

      163
    • Register 14-3: SSPxCON1: MSSPx Control Register 1 (SPI Mode)

      165
    • Register 14-4: SSPxCON1: MSSPx Control Register 1 (I2C™ Mode)

      166
    • Register 14-5: SSPxCON2: MSSPx Control Register 2 (I2C™ Mode)

      167
    • Register 14-6: SSPxCON3: MSSPx Control Register 3 (SPI Mode)

      168
    • Register 14-7: SSPxCON3: MSSPx Control Register 3 (I2C™ Mode)

      169
    • Register 14-8: SSPxADD: MSSPx Slave Address/Baud Rate Generator Register

      170
    • Register 14-9: SSPxMSK: I2C™ Slave Address Mask Register

      170
    • Register 14-10: PADCFG1: Pad Configuration Control Register

      171
• 15.0 Universal Asynchronous Receiver Transmitter (UART)

  173
  • FIGURE 15-1: UARTx Module Simplified Block Diagram

    173
  • 15.1 UARTx Baud Rate Generator (BRG)

    174
    • EQUATION 15-1: UARTx Baud Rate with BRGH = 0(1)

      174
    • EQUATION 15-2: UARTx Baud Rate with BRGH = 1(1)

      174
    • EXAMPLE 15-1: Baud Rate Error Calculation (BRGH = 0)(1)

      174
  • 15.2 Transmitting in 8-Bit Data Mode

    175
  • 15.3 Transmitting in 9-Bit Data Mode

    175
  • 15.4 Break and Sync Transmit Sequence

    175
  • 15.5 Receiving in 8-Bit or 9-Bit Data Mode

    175
  • 15.6 Operation of UxCTS and UxRTS Control Pins

    175
  • 15.7 Infrared Support

    175
    • 15.7.1 External IrDA Support – IrDA Clock Output

      175
    • 15.7.2 Built-in IrDA Encoder and Decoder

      175
      • Register 15-1: UxMODE: UARTx Mode Register

        176
      • Register 15-2: UxSTA: UARTx Status and Control Register

        178
      • Register 15-3: UxTXREG: UARTx Transmit Register

        180
      • Register 15-4: UxRXREG: UARTx Receive Register

        180
• 16.0 Real-Time Clock and Calendar (RTCC)

  181
  • 16.1 RTCC Source Clock

    181
    • FIGURE 16-1: RTCC Block Diagram

      181
  • 16.2 RTCC Module Registers

    182
    • 16.2.1 Register Mapping

      182
      • TABLE 16-1: RTCVAL Register Mapping

        182
      • TABLE 16-2: ALRMVAL Register Mapping

        182
    • 16.2.2 Write Lock

      182
    • 16.2.3 Selecting RTCC Clock Source

      182
      • EXAMPLE 16-1: Setting the RTCWREN Bit in Assembly

        182
      • EXAMPLE 16-2: Setting the RTCWREN Bit in ‘C’

        182
    • 16.2.4 RTCC Control Registers

      183
      • Register 16-1: RCFGCAL: RTCC Calibration and Configuration Register(1)

        183
      • Register 16-2: RTCPWC: RTCC Configuration Register 2(1)

        185
      • Register 16-3: ALCFGRPT: Alarm Configuration Register

        186
    • 16.2.5 RTCVAL Register Mappings

      187
      • Register 16-4: YEAR: Year Value Register(1)

        187
      • Register 16-5: MTHDY: Month and Day Value Register(1)

        187
      • Register 16-6: WKDYHR: Weekday and Hours Value Register(1)

        188
      • Register 16-7: MINSEC: Minutes and Seconds Value Register

        188
    • 16.2.6 ALRMVAL Register Mappings

      189
      • Register 16-8: ALMTHDY: Alarm Month and Day Value Register(1)

        189
      • Register 16-9: ALWDHR: Alarm Weekday and Hours Value Register(1)

        189
      • Register 16-10: ALMINSEC: Alarm Minutes and Seconds Value Register

        190
      • Register 16-11: RTCCSWT: rtcc Control/Sample Window Timer Register(1)

        191
  • 16.3 Calibration

    192
    • EQUATION 16-1:

      192
  • 16.4 Alarm

    192
    • 16.4.1 Configuring The Alarm

      192
    • 16.4.2 Alarm Interrupt

      192
      • FIGURE 16-2: Alarm Mask Settings

        193
  • 16.5 Power Control

    193
• 17.0 Configurable Logic Cell (CLC)

  195
  • FIGURE 17-1: CLCx Module

    195
  • FIGURE 17-2: CLCx Logic Function Combinatorial Options

    196
  • FIGURE 17-3: CLCx Input Source Selection Diagram

    197
  • 17.1 Control Registers

    198
    • Register 17-1: CLCxCONL: CLCx CONTROL REGISTER (LOW)

      198
    • Register 17-2: CLCxCONH: CLCx Control REGISTER (HIGH)

      199
    • Register 17-3: CLCxSEL: CLCx INPUT MUX SELECT REGISTER

      200
    • Register 17-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER

      202
    • Register 17-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER

      204
• 18.0 High/Low-Voltage Detect (HLVD)

  207
  • FIGURE 18-1: High/Low-Voltage Detect (HLVD) Module Block Diagram

    207
  • Register 18-1: HLVDCON: High/Low-Voltage Detect Control Register

    208
• 19.0 12-Bit A/D Converter with Threshold Detect

  209
  • FIGURE 19-1: 12-Bit A/D Converter Block Diagram

    210
  • 19.1 A/D Control Registers

    212
    • 19.1.1 Control Registers

      212
    • 19.1.2 A/D Result Buffers

      212
      • Register 19-1: AD1CON1: A/DA/D Control Register 1

        213
      • Register 19-2: AD1CON2: A/D Control Register 2

        215
      • Register 19-3: AD1CON3: A/D Control Register 3

        216
      • Register 19-4: AD1CON5: A/D Control Register 5

        217
      • Register 19-5: AD1CHS: A/D Sample Select Register

        218
      • Register 19-6: AD1CHITH: A/D Scan Compare Hit Register (High Word)(1)

        219
      • Register 19-7: AD1CHITL: A/D Scan Compare Hit Register (Low Word)(1)

        220
      • Register 19-8: AD1CSSH: A/D Input Scan Select Register (High Word)(1)

        221
      • Register 19-9: AD1CSSL: A/D Input Scan Select Register (Low word)(1)

        221
      • Register 19-10: AD1CTMENH: CTMU Enable Register (High Word)(1)

        222
      • Register 19-11: AD1CTMENL: CTMU Enable Register (Low Word)(1)

        222
  • 19.2 A/D Sampling Requirements

    223
    • EQUATION 19-1: A/D Conversion Clock Period

      223
    • FIGURE 19-2: 12-Bit A/D Converter Analog Input Model

      223
  • 19.3 Transfer Function

    224
    • FIGURE 19-3: 12-bit A/D Transfer Function

      224
  • 19.4 Buffer Data Formats

    225
    • FIGURE 19-4: A/D Output Data Formats (12-Bit)

      225
    • TABLE 19-1: Numerical Equivalents of Various Result Codes: 12-Bit Integer Formats

      225
    • TABLE 19-2: Numerical Equivalents of Various Result Codes: 12-Bit Fractional Formats

      226
    • FIGURE 19-5: A/D Output Data Formats (10-Bit)

      226
    • TABLE 19-3: Numerical Equivalents of Various Result Codes: 10-Bit Integer Formats

      226
    • TABLE 19-4: Numerical Equivalents of Various Result Codes: 10-Bit Fractional Formats

      227
• 20.0 8-Bit Digital-to-Analog Converter (DAC)

  229
  • FIGURE 20-1: Single DACx Simplified Block Diagram

    229
  • Register 20-1: DACxCON: DACx Control Register

    230
  • Register 20-2: BUFCON0: Internal Voltage reference Control Register 0

    232
• 21.0 Dual Operational Amplifier Module

  233
  • FIGURE 21-1: Single operational Amplifier Block Diagram

    233
  • Register 21-1: AMPxCON: OP AMP x Control Register(1)

    234
• 22.0 Comparator Module

  235
  • FIGURE 22-1: Comparator x Module Block Diagram

    235
  • FIGURE 22-2: Individual Comparator Configurations

    236
  • Register 22-1: CMxCON: Comparator x Control Registers

    237
  • Register 22-2: CMSTAT: Comparator Module Status Register

    238
• 23.0 Comparator Voltage Reference

  239
  • 23.1 Configuring the Comparator Voltage Reference

    239
    • FIGURE 23-1: Comparator Voltage Reference Block Diagram

      239
    • Register 23-1: CVRCON: Comparator Voltage Reference Control Register

      240
• 24.0 Charge Time Measurement Unit (CTMU)

  241
  • 24.1 Measuring Capacitance

    241
    • EQUATION 24-1:

      241
    • FIGURE 24-1: Typical Connections and Internal Configuration for Capacitance Measurement

      242
  • 24.2 Measuring Time

    242
    • FIGURE 24-2: Typical Connections and Internal Configuration for Time Measurement

      242
  • 24.3 Pulse Generation and Delay

    243
    • FIGURE 24-3: Typical Connections and Internal Configuration for Pulse Delay Generation

      243
    • Register 24-1: CTMUCON1L: CTMU Control 1 Low Register

      244
    • Register 24-2: CTMUCON1H: CTMU Control 1 High Register

      246
    • Register 24-3: CTMUCON2L: CTMU Control 2 Low Register

      248
• 25.0 Special Features

  249
  • 25.1 Configuration Bits

    249
    • TABLE 25-1: Configuration Registers Locations

      249
    • Register 25-1: FBS: Boot Segment Configuration Register

      249
    • Register 25-2: FGS: General Segment Configuration Register

      250
    • Register 25-3: FoscSEL: Oscillator Selection Configuration Register

      250
    • Register 25-4: Fosc: Oscillator Configuration Register

      251
    • Register 25-5: FWDT: Watchdog Timer Configuration Register

      252
    • Register 25-6: FPOR: Reset Configuration Register

      253
    • Register 25-7: FICD: In-Circuit Debugger Configuration Register

      254
    • Register 25-8: DEVID: Device ID Register

      255
    • Register 25-9: DEVREV: Device Revision Register

      256
  • 25.2 On-Chip Voltage Regulator

    257
    • 25.2.1 Voltage Regulator Tracking Mode and Low-Voltage Detection

      257
      • FIGURE 25-1: Connections for the On-Chip Voltage Regulator

        257
    • 25.2.2 Voltage Regulator Start-Up Time

      257
  • 25.3 Watchdog Timer (WDT)

    257
    • 25.3.1 Windowed Operation

      258
    • 25.3.2 Control Register

      258
      • FIGURE 25-2: WDT Block Diagram

        258
  • 25.4 Program Verification and Code Protection

    259
  • 25.5 In-Circuit Serial Programming

    259
  • 25.6 In-Circuit Debugger

    259
• 26.0 Development Support

  261
  • 26.1 MPLAB X Integrated Development Environment Software

    261
  • 26.2 MPLAB XC Compilers

    262
  • 26.3 MPASM Assembler

    262
  • 26.4 MPLINK Object Linker/ MPLIB Object Librarian

    262
  • 26.5 MPLAB Assembler, Linker and Librarian for Various Device Families

    262
  • 26.6 MPLAB X SIM Software Simulator

    263
  • 26.7 MPLAB REAL ICE In-Circuit Emulator System

    263
  • 26.8 MPLAB ICD 3 In-Circuit Debugger System

    263
  • 26.9 PICkit 3 In-Circuit Debugger/ Programmer

    263
  • 26.10 MPLAB PM3 Device Programmer

    263
  • 26.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits

    264
  • 26.12 Third-Party Development Tools

    264
• 27.0 Electrical Characteristics

  265
  • Absolute Maximum Ratings(†)

    265
  • 27.1 DC Characteristics

    266
    • FIGURE 27-1: PIC24FV16KM204 Family voltage-frequency graph (industrial)

      266
    • FIGURE 27-2: PIC24F16KM204 Family voltage-frequency graph (industrial)

      266
    • FIGURE 27-3: PIC24FV16KM204 Family voltage-frequency graph (Extended)

      267
    • FIGURE 27-4: PIC24F16KM204 Family voltage-frequency graph (Extended)

      267
    • TABLE 27-1: Thermal Operating Conditions

      268
    • TABLE 27-2: Thermal Packaging Characteristics

      268
    • TABLE 27-3: DC Characteristics: Temperature and Voltage Specifications

      268
    • TABLE 27-4: High/Low-Voltage Detect Characteristics

      269
    • TABLE 27-5: BOR Trip Points

      269
    • TABLE 27-6: DC Characteristics: Operating Current (Idd)

      270
    • TABLE 27-7: DC Characteristics: Idle Current (Iidle)

      271
    • TABLE 27-8: DC Characteristics: Power-Down Current (Ipd)

      272
    • TABLE 27-9: DC Characteristics: I/O Pin Input Specifications

      274
    • TABLE 27-10: DC Characteristics: I/O Pin Output Specifications

      275
    • TABLE 27-11: DC Characteristics: Program Memory

      275
    • TABLE 27-12: DC Characteristics: Data EEPROM Memory

      276
    • TABLE 27-13: DC Characteristics: Comparator

      276
    • TABLE 27-14: DC Characteristics: Comparator Voltage Reference

      276
    • TABLE 27-15: Internal Voltage Regulator Specifications

      277
    • TABLE 27-16: CTMU Current Source Specifications

      277
    • TABLE 27-17: Operational Amplifier Specifications

      278
  • 27.2 AC Characteristics and Timing Parameters

    279
    • TABLE 27-18: Temperature and Voltage Specifications – AC

      279
    • FIGURE 27-5: Load Conditions for Device Timing Specifications

      279
    • TABLE 27-19: Capacitive Loading Requirements on Output Pins

      279
    • FIGURE 27-6: External Clock Timing

      280
    • TABLE 27-20: External Clock Timing Requirements

      280
    • TABLE 27-21: PLL Clock Timing Specifications

      281
    • TABLE 27-22: Internal RC Oscillator Accuracy

      281
    • TABLE 27-23: Internal RC Oscillator Specifications

      281
    • FIGURE 27-7: CLKO and I/O Timing Characteristics

      282
    • TABLE 27-24: CLKO and I/O Timing Requirements

      282
    • FIGURE 27-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics

      283
    • FIGURE 27-9: Brown-out Reset Characteristics

      284
    • TABLE 27-25: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-Up Timer and Brown-Out Reset Timing Requirements

      284
    • TABLE 27-26: Comparator Timing Requirements

      285
    • TABLE 27-27: Comparator Voltage Reference Settling Time Specifications

      285
    • FIGURE 27-10: Capture/Compare/PWM Timings (MCCPx, SCCPx Modules)

      285
    • TABLE 27-28: Capture/Compare/PWM Requirements (MCCPx, SCCPx Modules)

      285
    • FIGURE 27-11: Example SPI Master Mode Timing (CKE = 0)

      286
    • TABLE 27-29: Example SPI Mode Requirements (Master Mode, Cke = 0)

      286
    • FIGURE 27-12: Example SPI Master Mode Timing (CKE = 1)

      287
    • TABLE 27-30: Example SPI Mode Requirements (Master Mode, CKE = 1)

      287
    • FIGURE 27-13: Example SPI Slave Mode Timing (CKE = 0)

      288
    • TABLE 27-31: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)

      288
    • FIGURE 27-14: Example SPI Slave Mode Timing (CKE = 1)

      289
    • TABLE 27-32: Example SPI Slave Mode Requirements (CKE = 1)

      289
    • FIGURE 27-15: I2C™ Bus Start/Stop Bits Timing

      290
    • TABLE 27-33: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)

      290
    • FIGURE 27-16: I2C™ Bus Data Timing

      290
    • TABLE 27-34: I2C™ Bus Data Requirements (Slave Mode)

      291
    • FIGURE 27-17: MSSPx I2C™ Bus Start/Stop Bits Timing Waveforms

      292
    • TABLE 27-35: I2C™ Bus Start/Stop Bits Requirements (Master Mode)

      292
    • FIGURE 27-18: MSSPx I2C™ Bus Data Timing

      293
    • TABLE 27-36: I2C™ Bus Data Requirements (Master Mode)

      293
    • TABLE 27-37: A/D Module Specifications

      294
    • FIGURE 27-19: A/D Conversion Timing

      295
    • TABLE 27-38: A/D Conversion Timing Requirements(1)

      295
    • TABLE 27-39: 8-Bit Digital-to-Analog Converter Specifications

      296
• 28.0 Packaging Information

  297
  • 28.1 Package Marking Information

    297
  • 28.2 Package Details

    300
• Appendix A: Revision History

  325
  • Revision A (February 2013)

    325
  • Revision B (July 2013)

    325
• INDEX

  327
• The Microchip Web Site

  333
• Customer Change Notification Service

  333
• Customer Support

  333
• Product Identification System

  335
• Worldwide Sales and Service

  338