Microchip Technology TDGL003 - chipKIT Max32 Development Board TDGL003 User Manuals

Table of Contents

• High-Performance 32-bit RISC CPU:

  3
• Microcontroller Features:

  3
• Peripheral Features:

  3
• Debug Features:

  3
• Analog Features:

  3
• Pin Diagrams

  6
• Pin Diagrams (Continued)

  7
• Pin Diagrams (Continued)

  8
• Pin Diagrams (Continued)

  9
• Pin Diagrams (Continued)

  12
• Pin Diagrams (Continued)

  13
• Pin Diagrams (Continued)

  14
• Pin Diagrams (Continued)

  15
• Table of Contents

  18
• Most Current Data Sheet

  19
• Errata

  19
• Customer Notification System

  19
• 1.0 Device Overview

  21
  • FIGURE 1-1: Block Diagram(1,2)

    21
  • Table 1-1: Pinout I/O Descriptions (Continued)

    22
• 2.0 Guidelines for Getting Started with 32-bit Microcontrollers

  31
  • 2.1 Basic Connection Requirements

    31
  • 2.2 Decoupling Capacitors

    31
    • FIGURE 2-1: Recommended Minimum Connection

      32
    • 2.2.1 Bulk Capacitors

      32
  • 2.3 Capacitor on Internal Voltage Regulator (Vcap/Vcore)

    32
    • 2.3.1 Internal Regulator Mode

      32
    • 2.3.2 External Regulator Mode

      32
  • 2.4 Master Clear (MCLR) Pin

    32
    • FIGURE 2-2: Example of MCLR Pin Connections

      32
  • 2.5 ICSP Pins

    33
  • 2.6 JTAG

    33
  • 2.7 Trace

    33
  • 2.8 External Oscillator Pins

    33
    • FIGURE 2-3: Suggested Placement of the Oscillator Circuit

      33
  • 2.9 Configuration of Analog and Digital Pins During ICSP Operations

    34
  • 2.10 Unused I/Os

    34
  • 2.11 Referenced Sources

    35
• 3.0 CPU

  37
  • 3.1 Features

    37
    • FIGURE 3-1: MIPS® M4K® Block Diagram

      37
  • 3.2 Architecture Overview

    38
    • 3.2.1 Execution Unit

      38
    • 3.2.2 Multiply/Divide Unit (MDU)

      38
      • Table 3-1: MIPS® M4K® Processor Core High-Performance Integer Multiply/Divide Unit Latencies and Repeat Rates

        39
    • 3.2.3 System Control Coprocessor (CP0)

      39
      • Table 3-2: Coprocessor 0 Registers (Continued)

        39
      • Table 3-3: PIC32MX3XX/4XX family Core Exception Types

        40
  • 3.3 Power Management

    41
    • 3.3.1 Instruction-Controlled Power Management

      41
    • 3.3.2 Local Clock Gating

      41
  • 3.4 EJTAG Debug Support

    41
• 4.0 Memory Organization

  43
  • 4.1 Key Features

    43
  • 4.2 PIC32MX3XX/4XX Memory Layout

    43
    • Figure 4-1: Memory Map on Reset for PIC32MX320F032H and PIC32MX420F032H Devices(1)

      44
    • Figure 4-2: Memory Map on Reset for PIC32MX320F064H Device(1)

      45
    • Figure 4-3: Memory Map on Reset for PIC32MX320F128H and PIC32MX320F128L Devices(1)

      46
    • Figure 4-4: Memory Map on Reset for PIC32MX340F128H, PIC32MX340F128L, PIC32MX440F128H and PIC32MX440F128L Devices(1)

      47
    • Figure 4-5: Memory Map on Reset for PIC32MX340F256H, PIC32MX360F256L, PIC32MX440F256H and PIC32MX460F256L Devices(1)

      48
    • Figure 4-6: Memory Map on Reset for PIC32MX340F512H, PIC32MX360F512L, PIC32MX440F512H and PIC32MX460F512L Devices(1)

      49
    • TABLE 4-1: Bus Matrix Registers Map

      50
    • TABLE 4-2: Interrupt Registers Map for PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)

      51
    • Table 4-3: Interrupt Registers Map for PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX340F128L, PIC32MX360F256L and PIC32MX360F512L Devices Only(1)

      52
    • Table 4-4: Interrupt Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H and PIC32MX320F128L Devices Only(1)

      53
    • Table 4-5: Interrupt Registers Map for PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)

      54
    • Table 4-6: Interrupt Registers Map for the PIC32MX420F032H Device Only(1)

      55
    • TABLE 4-7: Timer1-5 Registers Map(1)

      56
    • TABLE 4-8: Input Capture1-5 Registers Map

      57
    • TABLE 4-9: Output Compare1-5 Registers Map(1)

      58
    • TABLE 4-10: I2C1-2 Registers Map(1)

      59
    • TABLE 4-11: UART1-2 Registers Map

      60
    • TABLE 4-12: SPI1-2 Registers Map(1,2)

      61
    • TABLE 4-13: ADC Registers Map (Continued)

      62
    • TABLE 4-14: DMA Global Registers Map for PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX Devices Only

      64
    • TABLE 4-15: DMA CRC Registers Map for PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX Devices Only(1)

      64
    • TABLE 4-16: DMA Channels 0-3 Registers Map for PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX Devices Only(1) (Continued)

      65
    • TABLE 4-17: Comparator Registers Map(1)

      68
    • TABLE 4-18: Comparator Voltage Reference Registers Map(1)

      68
    • TABLE 4-19: Flash Controller Registers Map

      69
    • TABLE 4-20: System Control Registers Map(1,2)

      69
    • TABLE 4-21: PortA Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)

      70
    • TABLE 4-22: PortB Registers Map(1)

      70
    • TABLE 4-23: PortC Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)

      71
    • TABLE 4-24: PortC Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)

      71
    • TABLE 4-25: PortD Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)

      72
    • TABLE 4-26: PortD Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)

      72
    • TABLE 4-27: PortE Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)

      73
    • TABLE 4-28: PortE Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)

      73
    • TABLE 4-29: PortF Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L and PIC32MX360F512L Devices Only(1)

      74
    • TABLE 4-30: PortF Registers Map for PIC32MX440f128l, pic32mx460f256l AND pic32mx460f512l Devices Only(1)

      74
    • TABLE 4-31: PortF Registers Map for PIC32MX320f032h, pic32mx320f064h, pic32mx320f128h, pic32mx340f128h, pic32mx340f256h AND pic32mx340f512h Devices Only(1)

      75
    • TABLE 4-32: PortF Registers Map for PIC32MX420f032h, pic32mx440f128h and pic2mx440f256h Devices Only(1)

      75
    • TABLE 4-33: PortG Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)

      76
    • TABLE 4-34: PortG Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)

      76
    • TABLE 4-35: Change Notice and Pull-Up Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)

      77
    • TABLE 4-36: Change Notice and Pull-Up Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)

      77
    • TABLE 4-37: Parallel Master Port Registers Map(1)

      78
    • TABLE 4-38: Programming and Diagnostics Registers Map

      78
    • TABLE 4-39: Prefetch Registers Map

      79
    • TABLE 4-40: RTCC Registers Map(1)

      80
    • TABLE 4-41: DEVCFG: Device Configuration Word Summary

      80
    • TABLE 4-42: Device and Revision ID Summary

      81
    • TABLE 4-43: USB Registers Map(1) (Continued)

      82
• 5.0 Flash Program Memory

  85
  • EXAMPLE 5-1:

    85
• 6.0 Resets

  87
  • FIGURE 6-1: System Reset Block Diagram

    87
• 7.0 Interrupt Controller

  89
  • FIGURE 7-1: Interrupt Controller Module

    89
  • Table 7-1: Interrupt IRQ and Vector Location (Continued)

    90
• 8.0 Oscillator Configuration

  93
  • FIGURE 8-1: PIC32MX3XX/4XX Family Clock Diagram

    93
• 9.0 Prefetch Cache

  95
  • 9.1 Features

    95
    • FIGURE 9-1: Prefetch Module Block Diagram

      95
• 10.0 Direct Memory Access (DMA) Controller

  97
  • FIGURE 10-1: DMA Block Diagram

    97
• 11.0 USB On-The-Go (OTG)

  99
  • FIGURE 11-1: PIC32MX3XX/4XX Family USB Interface Diagram

    100
• 12.0 I/O Ports

  101
  • FIGURE 12-1: Block Diagram of a Typical Multiplexed Port Structure

    101
  • 12.1 Parallel I/O (PIO) Ports

    102
    • 12.1.1 CLR, SET and INV Registers

      102
    • 12.1.2 Digital Inputs

      102
    • 12.1.3 Analog Inputs

      102
    • 12.1.4 Digital Outputs

      102
    • 12.1.5 Analog Outputs

      102
    • 12.1.6 Input Change Notification

      102
• 13.0 Timer1

  103
  • 13.1 Additional Supported Features

    103
    • FIGURE 13-1: Timer1 Block Diagram(1)

      103
• 14.0 Timer2/3 and Timer4/5

  105
  • 14.1 Additional Supported Features

    105
    • FIGURE 14-1: Timer2, 3, 4, 5 Block Diagram (16-bit)

      105
    • FIGURE 14-2: Timer2/3, 4/5 Block Diagram (32-bit)

      106
• 15.0 Input Capture

  107
  • FIGURE 15-1: Input Capture Block Diagram

    107
• 16.0 Output Compare

  109
  • FIGURE 16-1: Output Compare Module Block Diagram

    109
• 17.0 Serial Peripheral Interface (SPI)

  111
  • FIGURE 17-1: SPI Module Block Diagram

    111
• 18.0 Inter-Integrated Circuit™ (I2C™)

  113
  • FIGURE 18-1: I2C™ Block Diagram (x = 1 or 2)

    114
• 19.0 Universal Asynchronous Receiver Transmitter (UART)

  115
  • FIGURE 19-1: UART Simplified Block Diagram

    115
  • FIGURE 19-2: Transmission (8-Bit or 9-Bit Data)

    116
  • FIGURE 19-3: Two Consecutive Transmissions

    116
  • FIGURE 19-4: UART Reception

    117
  • FIGURE 19-5: UART Reception with Receive Overrun

    117
• 20.0 Parallel Master Port (PMP)

  119
  • FIGURE 20-1: PMP Module Pinout and Connections to External Devices

    119
• 21.0 Real-Time Clock and Calendar (RTCC)

  121
  • FIGURE 21-1: RTCC Block Diagram

    121
• 22.0 10-bit Analog-to-Digital Converter (ADC)

  123
  • FIGURE 22-1: ADC1 Module Block Diagram

    123
  • FIGURE 22-2: ADC Conversion Clock Period Block Diagram

    124
• 23.0 Comparator

  125
  • FIGURE 23-1: Comparator Block Diagram

    125
• 24.0 Comparator Voltage Reference (CVref)

  127
  • FIGURE 24-1: Comparator Voltage Reference Block Diagram

    127
• 25.0 Power-Saving Features

  129
  • 25.1 Power-Saving with CPU Running

    129
  • 25.2 CPU Halted Methods

    129
  • 25.3 Power-Saving Operation

    129
    • 25.3.1 Sleep Mode

      129
    • 25.3.2 Idle Mode

      130
    • 25.3.3 Peripheral Bus Scaling Method

      130
• 26.0 Special Features

  131
  • 26.1 Configuration Bits

    131
    • Register 26-1: DEVCFG0: Device Configuration Word 0 (Continued)

      131
    • Register 26-2: DEVCFG1: Device Configuration Word 1 (Continued)

      133
    • Register 26-3: DEVCFG2: Device Configuration Word 2

      135
    • Register 26-4: DEVCFG3: Device Configuration Word 3

      136
    • Register 26-5: DEVID: Device and Revision ID Register

      136
  • 26.2 Watchdog Timer (WDT)

    137
    • Figure 26-1: Watchdog and Power-Up Timer Block Diagram

      137
  • 26.3 On-Chip Voltage Regulator

    138
    • 26.3.1 On-Chip Regulator and POR

      138
    • 26.3.2 On-Chip Regulator and BOR

      138
    • 26.3.3 Power-up Requirements

      138
      • Figure 26-2: Connections for the On-Chip Regulator

        138
  • 26.4 Programming and Diagnostics

    139
    • FIGURE 26-3: Block Diagram of Programming, Debugging and Trace Ports

      139
    • Register 26-6: DDPCON: Debug Data Port Control Register

      140
• 27.0 Instruction Set

  141
  • Table 27-1: MIPS32® Instruction Set

    141
• 28.0 Development Support

  147
  • 28.1 MPLAB Integrated Development Environment Software

    147
  • 28.2 MPLAB C Compilers for Various Device Families

    148
  • 28.3 HI-TECH C for Various Device Families

    148
  • 28.4 MPASM Assembler

    148
  • 28.5 MPLINK Object Linker/ MPLIB Object Librarian

    148
  • 28.6 MPLAB Assembler, Linker and Librarian for Various Device Families

    148
  • 28.7 MPLAB SIM Software Simulator

    149
  • 28.8 MPLAB REAL ICE In-Circuit Emulator System

    149
  • 28.9 MPLAB ICD 3 In-Circuit Debugger System

    149
  • 28.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express

    149
  • 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

    150
  • 28.12 MPLAB PM3 Device Programmer

    150
  • 28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    150
• 29.0 Electrical Characteristics

  151
  • Absolute Maximum Ratings

    151
  • (Note 1)

    151
  • 29.1 DC Characteristics

    152
    • Table 29-1: Operating MIPS vs. Voltage

      152
    • Table 29-2: Thermal Operating Conditions

      152
    • Table 29-3: Thermal Packaging Characteristics

      152
    • Table 29-4: DC Temperature and Voltage Specifications

      152
    • Table 29-5: DC Characteristics: Operating Current (Idd)

      153
    • Table 29-6: DC Characteristics: Idle Current (Iidle)

      154
    • Table 29-7: DC Characteristics: Power-Down Current (Ipd) (Continued)

      155
    • Table 29-8: DC Characteristics: I/O Pin Input Specifications

      157
    • Table 29-9: DC Characteristics: I/O Pin Output Specifications

      158
    • Table 29-10: Electrical Characteristics: Brown-Out Reset (BOR)

      158
    • Table 29-11: DC Characteristics: Program Memory(3)

      159
    • Table 29-12: Program Flash Memory Wait State Characteristics

      159
    • Table 29-13: Comparator Specifications

      160
    • Table 29-14: Voltage Reference Specifications

      160
    • Table 29-15: Internal Voltage Regulator Specifications

      160
  • 29.2 AC Characteristics and Timing Parameters

    161
    • Figure 29-1: Load Conditions for Device Timing Specifications

      161
    • Table 29-16: Capacitive Loading Requirements on Output Pins

      161
    • Figure 29-2: External Clock Timing

      161
    • Table 29-17: External Clock Timing Requirements

      162
    • Table 29-18: PLL Clock Timing Specifications (Vdd = 2.3V to 3.6V)

      163
    • Table 29-19: Internal FRC Accuracy

      163
    • Table 29-20: Internal RC Accuracy

      163
    • Figure 29-3: I/O Timing Characteristics

      164
    • Table 29-21: I/O Timing Requirements

      164
    • Figure 29-4: Power-On Reset Timing Characteristics

      165
    • Figure 29-5: External Reset Timing Characteristics

      166
    • Table 29-22: Resets Timing

      166
    • Figure 29-6: Timer1, 2, 3, 4, 5 External Clock Timing Characteristics

      167
    • Table 29-23: Timer1 External Clock Timing Requirements(1)

      167
    • Table 29-24: Timer2, 3, 4, 5 External Clock Timing Requirements

      168
    • Figure 29-7: Input Capture (CAPx) Timing Characteristics

      169
    • Table 29-25: Input Capture Module Timing Requirements

      169
    • Figure 29-8: Output Compare Module (OCx) Timing Characteristics

      169
    • Table 29-26: Output Compare Module Timing Requirements

      169
    • Figure 29-9: OC/PWM Module Timing Characteristics

      170
    • Table 29-27: Simple OC/PWM MODE Timing Requirements

      170
    • Figure 29-10: SPIx Module Master Mode (CKE = 0) Timing Characteristics

      171
    • Table 29-28: SPIx Master Mode (CKE = 0) Timing Requirements

      171
    • Figure 29-11: SPIx Module Master Mode (CKE = 1) Timing Characteristics

      172
    • Table 29-29: SPIx Module Master Mode (CKE = 1) Timing Requirements

      172
    • Figure 29-12: SPIx Module Slave Mode (CKE = 0) Timing Characteristics

      173
    • Table 29-30: SPIx Module Slave Mode (CKE = 0) Timing Requirements

      173
    • Figure 29-13: SPIx Module Slave Mode (CKE = 1) Timing Characteristics

      174
    • Table 29-31: SPIx Module Slave Mode (CKE = 1) Timing Requirements

      174
    • Figure 29-14: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)

      175
    • Figure 29-15: I2Cx Bus Data Timing Characteristics (Master Mode)

      175
    • Table 29-32: I2Cx Bus Data Timing Requirements (Master Mode)

      176
    • Figure 29-16: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)

      177
    • Figure 29-17: I2Cx Bus Data Timing Characteristics (Slave Mode)

      177
    • Table 29-33: I2Cx Bus Data Timing Requirements (Slave Mode)

      178
    • Table 29-34: ADC Module Specifications (Continued)

      179
    • Table 29-35: 10-bit ADC Conversion Rate Parameters(2)

      181
    • Table 29-36: Analog-to-Digital Conversion Timing Requirements

      182
    • Figure 29-18: Analog-to-Digital Conversion (10-bit Mode) Timing Characteristics (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)

      183
    • Figure 29-19: Analog-to-Digital Conversion (10-bit mode) Timing Characteristics (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)

      184
    • Figure 29-20: Parallel Slave Port Timing

      185
    • Table 29-37: Parallel Slave Port Requirements

      185
    • Figure 29-21: Parallel Master Port Read Timing Diagram

      186
    • Table 29-38: Parallel Master Port Read Timing Requirements

      186
    • Figure 29-22: Parallel Master Port Write Timing Diagram

      187
    • Table 29-39: Parallel Master Port Write Timing Requirements

      187
    • Table 29-40: OTG Electrical Specifications

      188
    • Figure 29-23: EJTAG Timing Characteristics

      189
    • Table 29-41: EJTAG Timing Requirements

      189
• 30.0 Packaging Information

  191
  • 30.1 Package Marking Information

    191
  • 30.2 Package Details

    192
• Appendix A: Revision History

  203
  • Revision E (July 2008)

    203
  • Revision F (June 2009)

    203
    • TABLE A-1: Major Section Updates (Continued)

      203
  • Revision G (April 2010)

    205
    • TABLE A-2: Major Section Updates (Continued)

      205
  • Revision H (May 2011)

    207
    • TABLE A-3: Major Section Updates (Continued)

      207
• Index

  209
• The Microchip Web Site

  211
• Customer Change Notification Service

  211
• Customer Support

  211
• Reader Response

  212
  • Product Identification System

    213
    • Worldwide Sales and Service

      214