User ManualTable of ContentsOverview211.1 Introduction231.1.1 Manual Organization241.1.2 Manual Conventions25Example11 Sample Code Listing25Table11 High True / Low True Signal Conventions261.2 DSP56012 Features26Table12 DSP56012 Internal Memory Configurations271.3 DSP56012 Architectural Overview28Figure11 DSP56012 Block Diagram291.3.1 Peripheral Modules301.3.2 DSP Core Processor301.3.2.1 Data Arithmetic and Logic Unit (Data ALU)311.3.2.2 Address Generation Unit (AGU)311.3.2.3 Program Control Unit321.3.2.4 Data Buses321.3.2.5 Address Buses321.3.2.6 Phase Lock Loop (PLL)321.3.2.7 On-Chip Emulation (OnCE) Port331.3.3 Memories331.3.3.1 Program Memory33Table13 Interrupt Starting Addresses and Sources (Continued)331.3.3.2 X Data Memory351.3.3.3 Y Data Memory351.3.3.4 On-Chip Memory Configuration Bits35Table14 Internal Memory Configurations 351.3.3.5 Memory Configuration Bits361.3.3.6 External Memory361.3.3.7 Bootstrap ROM361.3.3.8 Reserved Memory Spaces361.3.4 Input/Output36Table15 On-chip Peripheral Memory Map (Continued)371.3.4.1 Parallel Host Interface (HI)381.3.4.2 Serial Host Interface (SHI)381.3.4.3 Serial Audio Interface (SAI)391.3.4.4 General Purpose I/O391.3.4.5 Digital Audio Transmitter (DAX)39Signal Descriptions412.1 Signal Groupings43Table21 DSP56012 Functional Signal Groupings43Figure21 DSP56012 Signals442.2 Power45Table22 Power Inputs452.3 Ground46Table23 Grounds462.4 Phase Lock Loop (PLL)47Table24 Phase Lock Loop Signals472.5 Interrupt and Mode Control48Table25 Interrupt and Mode Control (Continued)482.6 Host Interface (HI)50Table26 Host Interface (Continued)502.7 Serial Host Interface (SHI)53Table27 Serial Host Interface (SHI) Signals (Continued)532.8 Serial Audio Interface (SAI)562.8.1 SAI Receive Section56Table28 Serial Audio Interface (SAI) Receive Signals562.8.2 SAI Transmit Section57Table29 Serial Audio Interface (SAI) Transmit Signals572.9 General Purpose Input/Output (GPIO)58Table210 General Purpose I/O (GPIO) Signals582.10 Digital Audio Interface (DAX)58Table211 Digital Audio Interface (DAX) Signals582.11 OnCE Port59Table212 On-Chip Emulation Port (OnCE) Signals (Continued)59Memory, Operating Modes, and Interrupts613.1 Introduction63Table31 Internal Memory Configurations633.2 DSP56012 Data and Program Memory633.2.1 X and Y Data ROM643.2.2 Bootstrap ROM643.3 DSP56012 Data and Program Memory Maps643.3.1 Reserved Memory Spaces65Figure31 Memory Maps for PEA = 0, PEB = 065Figure32 Memory Maps for PEA = 1, PEB = 066Figure33 Memory Maps for PEA = 0, PEB = 167Figure34 Memory Maps for PEA = 1, PEB = 1683.3.2 Dynamic Switch of Memory Configurations683.3.3 Internal I/O Memory Map70Table32 Internal I/O Memory Map (Continued)703.4 Operating Mode Register (OMR)72Figure35 Operating Mode Register (OMR)723.4.1 DSP Operating Mode (MC, MB, MA)—Bits 4, 1, and 0723.4.2 Program RAM Enable A and Program RAM Enable B (PEA and PEB)—Bits 2 and 3723.4.3 Stop Delay (SD)—Bit 6723.5 Operating Modes73Table33 Operating Modes 733.6 Interrupt Priority Register75Figure36 Interrupt Priority Register (Addr X:$FFFF)76Table34 Interrupt Priorities (Continued)76Table35 Interrupt Vectors (Continued)773.7 Phase Lock Loop (PLL) Configuration79Figure37 PLL Configuration803.8 Operation on Hardware Reset80Parallel Host Interface814.1 Introduction83Figure41 Port B Interface834.2 Port B Configuration83Figure42 Parallel Port B Registers84Figure43 Port B GPIO Signals and Registers85Figure44 Port B I/O Pin Control Logic864.2.1 Port B Control (PBC) Register864.2.2 Port B Data Direction Register (PBDDR)874.2.3 Port B Data (PBD) Register874.3 Programming the GPIO88Figure45 Instructions to Write/Read Parallel Data with Port B88Figure46 I/O Port B Configuration894.4 Host Interface (HI)894.4.1 HI Features904.4.2 HI Block Diagram91Figure47 HI Block Diagram924.4.3 HI—DSP Viewpoint924.4.4 Programming Model—DSP Viewpoint93Figure48 HI Programming Model–DSP Viewpoint944.4.4.1 HI Control Register (HCR)944.4.4.1.1 HCR HI Receive Interrupt Enable (HRIE)—Bit 0954.4.4.1.2 HCR HI Transmit Interrupt Enable (HTIE)—Bit 1954.4.4.1.3 HCR HI Command Interrupt Enable (HCIE)—Bit 2954.4.4.1.4 HCR HI Flag 2 (HF2)—Bit 3954.4.4.1.5 HCR HI Flag 3 (HF3)—Bit 4954.4.4.1.6 HCR Reserved—Bits 5, 6, and 7964.4.4.2 HI Status Register (HSR)964.4.4.2.1 HSR HI Receive Data Full (HRDF)—Bit 0964.4.4.2.2 HSR HI Transmit Data Empty (HTDE)—Bit 1964.4.4.2.3 HSR HI Command Pending (HCP)—Bit 2974.4.4.2.4 HSR HI Flag 0 (HF0)—Bit 3974.4.4.2.5 HSR HI Flag 1 (HF1)—Bit 497Figure49 HI Flag Operation984.4.4.2.6 HSR Reserved—Bits 5 and 6984.4.4.2.7 HSR DMA Status (DMA)—Bit 7984.4.4.3 HI Receive Data Register (HORX)984.4.4.4 HI Transmit Data Register (HOTX)994.4.4.5 Register Contents After Reset99Table41 HI Registers after Reset—DSP CPU Side (Continued)994.4.4.6 DSP Interrupts1004.4.4.7 HI Usage Considerations—DSP Side1014.4.5 HI—Host Processor Viewpoint1014.4.5.1 Programming Model—Host Processor Viewpoint1014.4.5.2 Host Command102Figure410 Host Processor Programming Model–Host Side103Figure411 HI Register Map1044.4.5.3 Interrupt Control Register (ICR)1044.4.5.3.1 ICR Receive Request Enable (RREQ)—Bit 01044.4.5.3.2 ICR Transmit Request Enable (TREQ)—Bit 1104Table42 HOREQ Pin Definition1054.4.5.3.3 ICR Reserved—Bit 21054.4.5.3.4 ICR HI Flag 0 (HF0)—Bit 3105Figure412 HSR and HCR Operation1064.4.5.3.5 ICR HI Flag 1 (HF1)—Bit 41064.4.5.3.6 ICR HI Mode Control (HM1 and HM0)—Bits 5 and 6106Table43 HI Mode Bit Definition 1064.4.5.3.7 ICR Initialize Bit (INIT)—Bit 71074.4.5.4 HI Initialization107Table44 HOREQ Pin Definition 1084.4.5.5 Command Vector Register (CVR)1094.4.5.5.1 CVR HI Vector (HV)—Bits 0–5109Figure413 Command Vector Register1094.4.5.5.2 CVR Reserved—Bit 61104.4.5.5.3 CVR Host Command (HC)—Bit 71104.4.5.6 Interrupt Status Register (ISR)1104.4.5.6.1 ISR Receive Data Register Full (RXDF)—Bit 01104.4.5.6.2 ISR Transmit Data Register Empty (TXDE)—Bit 11114.4.5.6.3 ISR Transmitter Ready (TRDY)—Bit 21114.4.5.6.4 ISR HI Flag 2 (HF2)—Bit 3 (read only)1114.4.5.6.5 ISR HI Flag 3 (HF3)—Bit 4 (read only)1114.4.5.6.6 ISR Reserved—Bit 51114.4.5.6.7 ISR DMA Status (DMA)—Bit 61124.4.5.6.8 ISR Host Request (HOREQ)—Bit 71124.4.5.7 Interrupt Vector Register (IVR)1124.4.5.8 Receive Byte Registers (RXH, RXM, RXL)1124.4.5.9 Transmit Byte Registers (TXH, TXM, TXL)1134.4.5.10 Registers After Reset113Table45 HI Registers after Reset (Host Side) 1144.4.6 HI Signals1154.4.6.1 HI Data Bus (H0–H7)1154.4.6.2 HI Address (HOA2–HOA0)1154.4.6.3 HI Read/Write (HR/W)1154.4.6.4 HI Enable (HEN)1154.4.6.5 Host Request (HOREQ)1154.4.6.6 Host Acknowledge (HACK)116Table46 Port B Pin Definitions116Figure414 Host Processor Transfer Timing1174.4.7 Servicing the HI1174.4.7.1 HI—Host Processor Data Transfer1174.4.7.2 Host Interrupts using Host Request (HOREQ)1184.4.7.3 Polling1184.4.7.4 Servicing Non-DMA Interrupts119Figure415 Interrupt Vector Register Read Timing120Figure416 HI Interrupt Structure120Figure417 DMA Transfer Logic and Timing1214.4.7.5 Servicing DMA Interrupts1214.4.8 Host Interface Application Examples1224.4.8.1 HI Initialization122Figure418 HI Initialization Flowchart122Figure419 HI Initialization—DSP Side123Figure420 HI Initialization—Host Side, Interrupt Mode124Figure421 HI Mode and INIT Bits1254.4.8.2 Polling/Interrupt Controlled Data Transfer125Figure422 HI Initialization—Host Side, Polling Mode126Figure423 HI Configuration—Host Side126Figure424 HI Initialization–Host Side, DMA Mode127Figure425 Bits Used for Host-to-DSP Transfer1284.4.8.2.1 Host to DSP—Data Transfer129Figure426 Data Transfer from Host to DSP1304.4.8.2.2 Host to DSP–Command Vector131Figure427 Host Command132Figure428 Receive Data from Host—Main Program133Figure429 Receive Data from Host Interrupt Routine1334.4.8.2.3 Host to DSP—Bootstrap Loading Using the HI134Figure430 Transmit/Receive Byte Registers134Figure431 Bootstrap Using the Host Interface1354.4.8.2.4 DSP to Host—Data Transfer136Figure432 Bits Used for DSP to Host Transfer137Figure433 Data Transfer from DSP to Host1384.4.8.3 DMA Data Transfer139Figure434 Main Program: Transmit 24-bit Data to Host139Figure435 HI Hardware–DMA Mode140Figure436 DMA Transfer and HI Interrupts1414.4.8.3.1 Host to DSP—Internal Processing1414.4.8.3.2 Host to DSP—DMA Procedure142Figure437 Host to DSP DMA Procedure1434.4.8.3.3 DSP to HI —Internal Processing1444.4.8.3.4 DSP to Host—DMA Procedure1454.4.8.4 HI Port Usage Considerations—Host Side1454.4.8.4.1 Unsynchronized Reading of Receive Byte Registers1454.4.8.4.2 Overwriting Transmit Byte Registers1464.4.8.4.3 Synchronization of Status Bits from DSP to Host1464.4.8.4.4 Overwriting the Host Vector1464.4.8.4.5 Cancelling a Pending Host Command interrupt1464.4.8.4.6 Coordinating Data Transfers1474.4.8.4.7 Unused Pins147Serial Host Interface1495.1 Introduction1515.2 Serial Host Interface Internal Architecture152Figure51 Serial Host Interface Block Diagram1525.3 SHI Clock Generator153Figure52 SHI Clock Generator1535.4 Serial Host Interface Programming Model153Figure53 SHI Programming Model—Host Side153Figure54 SHI Programming Model—DSP Side154Table51 SHI Interrupt Vectors155Table52 SHI Internal Interrupt Priorities1555.4.1 SHI Input/Output Shift Register (IOSR)—Host Side156Figure55 SHI I/O Shift Register (IOSR)1565.4.2 SHI Host Transmit Data Register (HTX)—DSP Side1565.4.3 SHI Host Receive Data FIFO (HRX)—DSP Side1575.4.4 SHI Slave Address Register (HSAR)—DSP Side1575.4.4.1 HSAR Reserved Bits—Bits 17–0,191575.4.4.2 HSAR I2C Slave Address (HA[6:3], HA1)—Bits 23–20,181575.4.5 SHI Clock Control Register (HCKR)—DSP Side1575.4.5.1 Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0158Figure56 SPI Data-To-Clock Timing Diagram1585.4.5.2 HCKR Prescaler Rate Select (HRS)—Bit 21595.4.5.3 HCKR Divider Modulus Select (HDM[5:0])—Bits 8–31605.4.5.4 HCKR Reserved Bits—Bits 23–14, 11–91605.4.5.5 HCKR Filter Mode (HFM[1:0]) — Bits 13–12160Table53 SHI Noise Reduction Filter Mode1605.4.6 SHI Control/Status Register (HCSR)—DSP Side1615.4.6.1 HCSR Host Enable (HEN)—Bit 01615.4.6.1.1 SHI Individual Reset1615.4.6.2 HCSR I2C/SPI Selection (HI2C)—Bit 11615.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2162Table54 SHI Data Size 1625.4.6.4 HCSR Reserved Bits—Bits 23, 18, 16, and 41625.4.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 51625.4.6.6 HCSR Master Mode (HMST)—Bit 61625.4.6.7 HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7163Table55 HREQ Function In SHI Slave Modes1635.4.6.8 HCSR Idle (HIDLE)—Bit 91635.4.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 101645.4.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 111645.4.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12164Table56 HCSR Receive Interrupt Enable Bits 1655.4.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 141655.4.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 151655.4.6.14 Host Receive FIFO Not Empty (HRNE)—Bit 171665.4.6.15 Host Receive FIFO Full (HRFF)—Bit 191665.4.6.16 Host Receive Overrun Error (HROE)—Bit 201665.4.6.17 Host Bus Error (HBER)—Bit 211665.4.6.18 HCSR Host Busy (HBUSY)—Bit 221675.5 Characteristics Of The SPI Bus1675.6 Characteristics Of The I2C Bus1685.6.1 Overview168Figure57 I2C Bit Transfer168Figure58 I2C Start and Stop Events169Figure59 Acknowledgment on the I2C Bus1695.6.2 I2C Data Transfer Formats170Figure510 I2C Bus Protocol For Host Write Cycle170Figure511 I2C Bus Protocol For Host Read Cycle1705.7 SHI Programming Considerations1715.7.1 SPI Slave Mode1715.7.2 SPI Master Mode1725.7.3 I2C Slave Mode1735.7.3.1 Receive Data in I2C Slave Mode1745.7.3.2 Transmit Data In I2C Slave Mode1755.7.4 I2C Master Mode1755.7.4.1 Receive Data in I2C Master Mode1775.7.4.2 Transmit Data In I2C Master Mode1775.7.5 SHI Operation During Stop178Serial Audio Interface1796.1 Introduction1816.2 Serial Audio Interface Internal Architecture1826.2.1 Baud-Rate Generator182Figure61 SAI Baud-Rate Generator Block Diagram1826.2.2 Receive Section Overview183Figure62 SAI Receive Section Block Diagram1836.2.3 SAI Transmit Section Overview184Figure63 SAI Transmit Section Block Diagram1856.3 Serial Audio Interface Programming Model186Figure64 SAI Registers186Table61 SAI Interrupt Vector Locations187Table62 SAI Internal Interrupt Priorities1876.3.1 Baud Rate Control Register (BRC)1876.3.1.1 Prescale Modulus select (PM[7:0])—Bits 7–01886.3.1.2 Prescaler Range (PSR)—Bit 81886.3.1.3 BRC Reserved Bits—Bits 15–91886.3.2 Receiver Control/Status Register (RCS)1886.3.2.1 RCS Receiver 0 Enable (R0EN)—Bit 01886.3.2.2 RCS Receiver 1 Enable (R1EN)—Bit 11896.3.2.3 RCS Reserved Bit—Bits 13 and 21896.3.2.4 RCS Receiver Master (RMST)—Bit 31896.3.2.5 RCS Receiver Word Length Control (RWL[1:0])—Bits 4 and 5189Table63 Receiver Word Length Control1896.3.2.6 RCS Receiver Data Shift Direction (RDIR)—Bit 6190Figure65 Receiver Data Shift Direction (RDIR) Programming1906.3.2.7 RCS Receiver Left Right Selection (RLRS)—Bit 7190Figure66 Receiver Left/Right Selection (RLRS) Programming1906.3.2.8 RCS Receiver Clock Polarity (RCKP)—Bit 8191Figure67 Receiver Clock Polarity (RCKP) Programming1916.3.2.9 RCS Receiver Relative Timing (RREL)—Bit 9191Figure68 Receiver Relative Timing (RREL) Programming1926.3.2.10 RCS Receiver Data Word Truncation (RDWT)—Bit 10192Figure69 Receiver Data Word Truncation (RDWT) Programming1926.3.2.11 RCS Receiver Interrupt Enable (RXIE)—Bit 111936.3.2.12 RCS Receiver Interrupt Location (RXIL)—Bit 121936.3.2.13 RCS Receiver Left Data Full (RLDF)—Bit 141946.3.2.14 RCS Receiver Right Data Full (RRDF)—Bit 151946.3.3 SAI Receive Data Registers (RX0 and RX1)1956.3.4 Transmitter Control/Status Register (TCS)1956.3.4.1 TCS Transmitter 0 Enable (T0EN)—Bit 01956.3.4.2 TCS Transmitter 1 Enable (T1EN)—Bit 11956.3.4.3 TCS Transmitter 2 Enable (T2EN)—Bit 21966.3.4.4 TCS Transmitter Master (TMST)—Bit 31966.3.4.5 TCS Transmitter Word Length Control (TWL[1:0])—Bits 4 & 5196Table64 Transmitter Word Length 1966.3.4.6 TCS Transmitter Data Shift Direction (TDIR)—Bit 6196Figure610 Transmitter Data Shift Direction (TDIR) Programming1976.3.4.7 TCS Transmitter Left Right Selection (TLRS)—Bit 7197Figure611 Transmitter Left/Right Selection (TLRS) Programming1976.3.4.8 TCS Transmitter Clock Polarity (TCKP)—Bit 8197Figure612 Transmitter Clock Polarity (TCKP) Programming1986.3.4.9 TCS Transmitter Relative Timing (TREL)—Bit 9198Figure613 Transmitter Relative Timing (TREL) Programming1986.3.4.10 TCS Transmitter Data Word Expansion (TDWE)—Bit 10198Figure614 Transmitter Data Word Expansion (TDWE) Programming1996.3.4.11 TCS Transmitter Interrupt Enable (TXIE)—Bit 111996.3.4.12 TCS Transmitter Interrupt Location (TXIL)—Bit 122006.3.4.13 TCS Reserved Bit—Bit 132006.3.4.14 TCS Transmitter Left Data Empty (TLDE)—Bit 142006.3.4.15 TCS Transmitter Right Data Empty (TRDE)—Bit 152016.3.5 SAI Transmit Data Registers (TX2, TX1 and TX0)2016.4 Programming Considerations2026.4.1 SAI Operation During Stop2026.4.2 Initiating a Transmit Session2026.4.3 Using a Single Interrupt to Service Both Receiver and Transmitter Sections2026.4.4 SAI State Machine203GPIO2057.1 Introduction2077.2 GPIO Programming Model207Figure71 GPIO Control/Data Register2077.3 GPIO Register (GPIOR)2077.3.1 GPIOR Data Bits (GD[7:0])—Bits 7–02087.3.2 GPIOR Data Direction Bits (GDD[7:0])—Bits 15–8208Table71 GPIO Pin Configuration2087.3.3 GPIOR Control Bits (GC[7:0])—Bits 23–16208Figure72 GPIO Circuit Diagram209Digital Audio Transmitter2118.1 Overview213Figure81 Digital Audio Transmitter (DAX) Block Diagram2148.2 DAX Signals2148.3 DAX Functional Overview2158.4 DAX Programming Model216Table81 DAX Interrupt Vectors216Table82 DAX Interrupt Priority2168.5 DAX Internal Architecture216Figure82 DAX Programming Mode2178.5.1 DAX Audio Data Registers A and B (XADRA/XADRB)2178.5.2 DAX Audio Data Buffer (XADBUF)2178.5.3 DAX Audio Data Shift Register (XADSR)2188.5.4 DAX Control Register (XCTR)2188.5.4.1 DAX Enable (XEN)—Bit 02188.5.4.2 DAX Interrupt Enable (XIEN)—Bit 12188.5.4.3 DAX Stop Control (XSTP)—Bit 22188.5.4.4 DAX Clock Input Select (XCS[1:0])—Bits 3–4219Table83 Clock Source Selection2198.5.4.5 XCTR Reserved Bits—Bits 5-9, 16-232198.5.4.6 DAX Channel A Validity (XVA)—Bit 102198.5.4.7 DAX Channel A User Data (XUA)—Bit 112198.5.4.8 DAX Channel A Channel Status (XCA)—Bit 122198.5.4.9 DAX Channel B Validity (XVB)—Bit 132198.5.4.10 DAX Channel B User Data (XUB)—Bit 142208.5.4.11 DAX Channel B Channel Status (XCB)—Bit 152208.5.5 DAX Status Register (XSTR)2208.5.5.1 DAX Audio Data Register Empty (XADE)—Bit 02208.5.5.2 XSTR Reserved Bits—Bits 1, 5–232208.5.5.3 DAX Transmit Underrun Error Flag (XAUR)—Bit 22208.5.5.4 DAX Block Transfer Flag (XBLK)—Bit 3221Figure83 DAX Relative Timing2218.5.5.5 DAX Transmit In Progress (XTIP)—Bit 42218.5.6 DAX Non-Audio Data Buffer (XNADBUF)2228.5.7 DAX Parity Generator (PRTYG)2228.5.8 DAX Biphase Encoder2228.5.9 DAX Preamble Generator222Table84 Preamble Bit Patterns 222Figure84 Preamble sequence2238.5.10 DAX Clock Multiplexer223Figure85 Clock Multiplexer Diagram2238.5.11 DAX State Machine2248.6 DAX Programming Considerations2248.6.1 Initiating A Transmit Session2248.6.2 Transmit Register Empty Interrupt Handling2248.6.3 Block Transferred Interrupt Handling2248.6.4 DAX Operation During Stop225Bootstrap ROM Contents227A.1 INTRODUCTION229A.2 BOOTSTRAPPING THE DSP229A.3 Bootstrap Program Listing230Programming Reference233B.1 Introduction235B.2 Peripheral Addresses235B.3 Interrupt Addresses235B.4 Interrupt Priorities235B.5 Instruction Set Summary235B.6 Programming Sheets235FigureB1 On-chip Peripheral Memory Map236TableB1 Interrupt Starting Addresses and Sources (Continued)237TableB2 Interrupt Priorities Within an IPL (Continued)238TableB3 Instruction Set Summary (Sheet 7 of 7)240Size: 2.2 MBPages: 270Language: EnglishOpen manual