NEC 78k-0 series User Manuals

Table of Contents

• COVER

  1
• Major Revisions in This Edition

  6
• INTRODUCTION

  7
• CHAPTER 1 MEMORY SPACE

  12
  • 1.1 Memory Spaces

    12
  • 1.2 Internal Program Memory (Internal ROM) Space

    12
  • 1.3 Vector Table Area

    12
  • 1.4 CALLT Instruction Table Area

    12
  • 1.5 CALLF Instruction Entry Area

    12
  • 1.6 Internal Data Memory (Internal RAM) Space

    12
  • 1.7 Special Function Register (SFR) Area

    13
  • 1.8 External Memory Space

    13
  • 1.9 IEBus Register Area

    13
• CHAPTER 2 REGISTERS

  14
  • 2.1 Control Registers

    14
    • 2.1.1 Program counter (PC)

      14
    • 2.1.2 Program status word (PSW)

      14
    • 2.1.3 Stack pointer (SP)

      16
  • 2.2 General-Purpose Registers

    17
  • 2.3 Special Function Registers (SFRs)

    19
• CHAPTER 3 ADDRESSING

  20
  • 3.1 Instruction Address Addressing

    20
    • 3.1.1 Relative addressing

      20
    • 3.1.2 Immediate addressing

      21
    • 3.1.3 Table indirect addressing

      22
    • 3.1.4 Register addressing

      23
  • 3.2 Operand Address Addressing

    24
    • 3.2.1 Implied addressing

      24
    • 3.2.2 Register addressing

      25
    • 3.2.3 Direct addressing

      26
    • 3.2.4 Short direct addressing

      27
    • 3.2.5 Special-function register (SFR) addressing

      28
    • 3.2.6 Register indirect addressing

      29
    • 3.2.7 Based addressing

      30
    • 3.2.8 Based indexed addressing

      30
    • 3.2.9 Stack addressing

      31
• CHAPTER 4 INSTRUCTION SET

  32
  • 4.1 Operation

    32
    • 4.1.1 Operand identifiers and description methods

      32
    • 4.1.2 Description of “operation” column

      33
    • 4.1.3 Description of “flag operation” column

      33
    • 4.1.4 Description of number of clocks

      34
    • 4.1.5 Instructions listed by addressing type

      34
  • 4.2 Instruction Codes

    38
    • 4.2.1 Description of instruction code table

      38
    • 4.2.2 Instruction code list

      39
• CHAPTER 5 EXPLANATION OF INSTRUCTIONS

  46
  • 5.1 8-Bit Data Transfer Instructions

    48
  • 5.2 16-Bit Data Transfer Instructions

    51
  • 5.3 8-Bit Operation Instructions

    54
  • 5.4 16-Bit Operation Instructions

    63
  • 5.5 Multiply/Divide Instructions

    67
  • 5.6 Increment/Decrement Instructions

    70
  • 5.7 Rotate Instructions

    75
  • 5.8 BCD Adjust Instructions

    82
  • 5.9 Bit Manipulation Instructions

    85
  • 5.10 Call Return Instructions

    93
  • 5.11 Stack Manipulation Instructions

    101
  • 5.12 Unconditional Branch Instruction

    105
  • 5.13 Conditional Branch Instructions

    107
  • 5.14 CPU Control Instructions

    116
• APPENDIX A REVISION HISTORY

  123
• APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION)

  124
• APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)

  126