User ManualTable of ContentsCOVER1PREFACE6CHAPTER 1 INTRODUCTION231.1 Features231.2 Ordering Information231.3 System Configuration241.4 Block Diagram (Summary)251.5 Block Diagram (Detail)261.5.1 VR4120A RISC processor core261.5.2 IBUS271.5.3 System controller281.5.4 ATM cell processor291.5.5 Ethernet controller301.5.6 USB controller311.5.7 PCI controller321.6 Pin Configuration (Bottom View)331.7 Pin Function371.7.1 Power supply371.7.2 System PLL power supply371.7.3 USB PLL power supply371.7.4 System control interface381.7.5 Memory interface391.7.6 PCI interface411.7.7 ATM interface431.7.8 Ethernet interface451.7.9 USB interface461.7.10 UART interface471.7.11 Micro Wire interface471.7.12 Parallel port interface471.7.13 Boundary scan interface471.7.14 I.C. – open481.7.15 I.C.– pull down481.7.16 I.C. – pull down with resistor481.7.17 I.C. – pull up481.8 I/O Register Map491.9 Memory Map531.10 Reset Configuration541.11 Interrupts551.12 Clock Control Unit56CHAPTER 2 VR4120A572.1 Overview for VR4120A572.1.1 Internal block configuration582.1.2 VR4120A registers592.1.3 VR4120A instruction set overview602.1.4 Data formats and addressing612.1.5 Coprocessors (CP0)632.1.6 Floating-point unit (FPU)642.1.7 CPU core memory management system (MMU)652.1.8 Translation lookaside buffer (TLB)652.1.9 Operating modes652.1.10 Cache652.1.11 Instruction Pipeline662.2 MIPS III Instruction Set Summary662.2.1 MIPS III ISA instruction formats662.2.2 Instruction classes672.3 Pipeline842.3.1 Pipeline stages842.3.2 Branch delay872.3.3 Load delay872.3.4 Pipeline operation882.3.5 Interlock and exception handling942.3.6 Program compatibility1002.4 Memory Management System1012.4.1 Translation lookaside buffer (TLB)1012.4.2 Virtual address space1022.4.3 Physical address space1162.4.4 System control coprocessor1172.4.5 CP0 registers1192.5 Exception Processing1292.5.1 Exception processing operation1292.5.2 Precision of exceptions1302.5.3 Exception processing registers1302.5.4 Details of exceptions1422.5.5 Exception processing and servicing flowcharts1582.6 Initialization Interface1652.6.1 Cold reset1652.6.2 Soft reset1652.6.3 VR4120A processor modes1652.7 Cache Memory1682.7.1 Memory organization1682.7.2 Cache organization1692.7.3 Cache operations1712.7.4 Cache states1722.7.5 Cache state transition diagrams1732.7.6 Cache data integrity1742.7.7 Manipulation of the caches by an external agent1812.8 CPU Core Interrupts1822.8.1 Non-maskable interrupt (NMI)1822.8.2 Ordinary interrupts1822.8.3 Software interrupts generated in CPU core1822.8.4 Timer interrupt1822.8.5 Asserting interrupts183CHAPTER 3 SYSTEM CONTROLLER1853.1 Overview1853.1.1 CPU interface1853.1.2 Memory interface1853.1.3 IBUS Interface1853.1.4 UART1863.1.5 EEPROM1863.1.6 Timer1863.1.7 Interrupt controller1863.1.8 DSU (Deadman’s SW Unit)1863.1.9 System block diagram1873.1.10 Data flow diagram1883.2 Registers1893.2.1 Register map1893.2.2 S_GMR (General Mode Register)1913.2.3 S_GSR (General Status Register)1913.2.4 S_ISR (Interrupt Status Register)1923.2.5 S_IMR (Interrupt Mask Register)1933.2.6 S_NSR (NMI Status Register)1943.2.7 S_NER (NMI Enable Register)1953.2.8 S_VER (Version Register)1953.2.9 S_IOR (IO Port Register)1963.2.10 S_WRCR (Warm Reset Control Register)1973.2.11 S_WRSR (Warm Reset Status Register)1983.2.12 S_PWCR (Power Control Register)1993.2.13 S_PWSR (Power Status Register)2003.3 CPU Interface2013.3.1 Overview2013.3.2 Data rate control2013.3.3 Burst size control2013.3.4 Address decoding2013.3.5 Endian conversion2013.3.6 I/O performance2033.4 Memory Interface2043.4.1 Overview2043.4.2 Memory regions2043.4.3 Memory signal connections2053.4.4 Memory performance2063.4.5 RMMDR (ROM Mode Register)2073.4.6 RMATR (ROM Access Timing Register)2073.4.7 SDMDR (SDRAM Mode Register)2093.4.8 SDTSR (SDRAM Type Selection Register)2103.4.9 SDPTR (SDRAM Precharge Timing Register)2113.4.10 SDRMR (SDRAM Refresh Mode Register)2113.4.11 SDRCR (SDRAM Refresh Timer Count Register)2123.4.12 MBCR (Memory Bus Control Register)2123.4.13 Boot ROM2133.4.14 SDRAM2163.4.15 SDRAM refresh2193.4.16 Memory-to-CPU prefetch FIFO2193.4.17 CPU-to-memory write FIFO2193.4.18 SDRAM memory initialization2203.5 IBUS Interface2213.5.1 Overview2213.5.2 Endian Conversion on IBUS master2213.5.3 Endian Conversion on IBUS slave2223.5.4 ITCNTR (IBUS Timeout Timer Control Register)2233.5.5 ITSETR (IBUS Timeout Timer Set Register)2233.6 DSU (Deadman’s SW Unit)2243.6.1 Overview2243.6.2 DSUCNTR (DSU Control Register)2243.6.3 DSUSETR (DSU Time Set Register)2243.6.4 DSUCLRR (DSU Clear Register)2243.6.5 DSUTIMR (DSU Elapsed Time Register)2253.6.6 DSU register setting flow2253.7 Endian Mode Software Issues2263.7.1 Overview2263.7.2 Endian modes226CHAPTER 4 ATM CELL PROCESSOR2294.1 Overview2294.1.1 Function features2294.1.2 Block diagram of ATM cell processor2304.1.3 ATM cell processing operation overview2324.2 Memory Space2364.2.1 Work RAM and register space2374.2.2 Shared memory2374.3 Interruption2374.4 Registers for ATM Cell Processing2384.4.1 Register map2384.4.2 A_GMR (General Mode Register)2404.4.3 A_GSR (General Status Register)2404.4.4 A_IMR (Interrupt Mask Register)2414.4.5 A_RQU (Receiving Queue Underrun Register)2424.4.6 A_RQA (Receiving Queue Alert Register)2424.4.7 A_VER (Version Register)2424.4.8 A_CMR (Command Register)2424.4.9 A_CER (Command Extension Register)2424.4.10 A_MSA0 to A_MSA3 (Mailbox Start Address Register)2434.4.11 A_MBA0 to A_MBA3 (Mailbox Bottom Address Register)2434.4.12 A_MTA0 to A_MTA3 (Mailbox Tail Address Register)2434.4.13 A_MWA0 to A_MWA3 (Mailbox Write Address Register)2444.4.14 A_RCC (Valid Received Cell Counter)2444.4.15 A_TCC (Valid Transmitted Cell Counter)2444.4.16 A_RUEC (Receive Unprovisioned VPI/VCI Error Cell Counter)2444.4.17 A_RIDC (Receive Internal Dropped Cell Counter)2444.4.18 A_T1R (T1 Time Register)2454.4.19 A_TSR (Time Stamp Register)2454.4.20 A_IBBAR (IBUS Base Address Register)2454.4.21 A_INBAR (Instruction Base Address Register)2454.4.22 A_UMCMD (UTOPIA Management Interface Command Register)2464.5 Data Structure2474.5.1 Tx buffer structure2474.5.2 Rx pool structure2504.6 Initialization2554.6.1 Before starting RISC core2554.6.2 After RISC core’s F/W is starting2564.7 Commands2574.7.1 Set_Link_Rate command2584.7.2 Open_Channel command2584.7.3 Close_Channel command2594.7.4 Tx_Ready command2604.7.5 Add_Buffers command2614.7.6 Indirect_Access command2624.8 Operations2624.8.1 Work RAM usage2624.8.2 Transmission function2634.8.3 Receiving function2704.8.4 Mailbox276CHAPTER 5 ETHERNET CONTROLLER2775.1 Overview2775.1.1 Features2775.1.2 Block diagram of Ethernet controller block2775.2 Registers2795.2.1 Register map2795.2.2 En_MACC1 (MAC Configuration Register 1)2855.2.3 En_MACC2 (MAC Configuration Register 2)2865.2.4 En_IPGT (Back-to-Back IPG Register)2865.2.5 En_IPGR (Non Back-to-Back IPG Register)2865.2.6 En_CLRT (Collision Register)2875.2.7 En_LMAX (Maximum Packet Length Register)2875.2.8 En_RETX (Retry Count Register)2875.2.9 En_LSA2 (Station Address Register 2)2875.2.10 En_LSA1 (Station Address Register 1)2875.2.11 En_PTVR (Pause Timer Value Read Register)2885.2.12 En_VLTP (VLAN Type Register)2885.2.13 En_MIIC (MII Configuration Register)2885.2.14 En_MCMD (MII Command Register)2885.2.15 En_MADR (MII Address Register)2895.2.16 En_MWTD (MII Write Data Register)2895.2.17 En_MRDD (MII Read Data Register)2895.2.18 En_MIND (MII Indicate Register)2895.2.19 En_AFR (Address Filtering Register)2905.2.20 En_HT1 (Hash Table Register 1)2905.2.21 En_HT2 (Hash Table Register 2)2905.2.22 En_CAR1 (Carry Register 1)2915.2.23 En_CAR2 (Carry Register 2)2925.2.24 En_CAM1 (Carry Register 1 Mask Register)2935.2.25 En_CAM2 (Carry Register 2 Mask Register)2945.2.26 En_TXCR (Transmit Configuration Register)2945.2.27 En_TXFCR (Transmit FIFO Control Register)2955.2.28 En_TXDPR (Transmit Descriptor Pointer)2965.2.29 En_RXCR (Receive Configuration Register)2965.2.30 En_RXFCR (Receive FIFO Control Register)2975.2.31 En_RXDPR (Receive Descriptor Pointer)2975.2.32 En_RXPDR (Receive Pool Descriptor Pointer)2985.2.33 En_CCR (Configuration Register)2985.2.34 En_ISR (Interrupt Serves Register)2985.2.35 En_MSR (Mask Serves Register)2995.3 Operation3005.3.1 Initialization3005.3.2 Buffer structure for Ethernet Controller block3005.3.3 Buffer descriptor format3015.3.4 Frame transmission3025.3.5 Frame reception3055.3.6 Address Filtering307CHAPTER 6 USB CONTROLLER3096.1 Overview3096.1.1 Features3096.1.2 Internal block diagram3106.2 Registers3116.2.1 Register map3116.2.2 U_GMR (USB General Mode Register)3136.2.3 U_VER (USB Frame Number/Version Register)3136.2.4 U_GSR1 (USB General Status Register 1)3146.2.5 U_IMR1 (USB Interrupt Mask Register 1)3166.2.6 U_GSR2 (USB General Status Register 2)3186.2.7 U_IMR2 (USB Interrupt Mask Register 2)3196.2.8 U_EP0CR (USB EP0 Control Register)3206.2.9 U_EP1CR (USB EP1 Control Register)3216.2.10 U_EP2CR (USB EP2 Control Register)3216.2.11 U_EP3CR (USB EP3 Control Register)3226.2.12 U_EP4CR (USB EP4 Control Register)3236.2.13 U_EP5CR (USB EP5 Control Register)3246.2.14 U_EP6CR (USB EP6 Control Register)3246.2.15 U_CMR (USB Command Register)3256.2.16 U_CA (USB Command Extension Register)3256.2.17 U_TEPSR (USB Tx EndPoint Status Register)3266.2.18 U_RP0IR (USB Rx Pool0 Information Register)3266.2.19 U_RP0AR (USB Rx Pool0 Address Register)3276.2.20 U_RP1IR (USB Rx Pool1 Information Register)3276.2.21 U_RP1AR (USB Rx Pool1 Address Register)3276.2.22 U_RP2IR (USB Rx Pool2 Information Register)3286.2.23 U_RP2AR (USB Rx Pool2 Address Register)3286.2.24 U_TMSA (USB Tx MailBox Start Address Register)3286.2.25 U_TMBA (USB Tx MailBox Bottom Address Register)3286.2.26 U_TMRA (USB Tx MailBox Read Address Register)3286.2.27 U_TMWA (USB Tx MailBox Write Address Register)3296.2.28 U_RMSA (USB Rx MailBox Start Address Register)3296.2.29 U_RMBA (USB Rx MailBox Bottom Address Register)3296.2.30 U_RMRA (USB Rx MailBox Read Address Register)3296.2.31 U_RMWA (USB Rx MailBox Write Address Register)3296.3 USB Attachment Sequence3306.4 Initialization3316.4.1 Receive pool settings3326.4.2 Transmit/receive MailBox settings3326.5 Data Transmit Function3346.5.1 Overview of transmit processing3346.5.2 Tx buffer configuration3346.5.3 Data transmit modes3376.5.4 VR4120A processing at data transmitting3386.5.5 USB controller processing at data transmitting3416.5.6 Tx indication3436.6 Data Receive Function3446.6.1 Overview of receive processing3446.6.2 Rx Buffer configuration3456.6.3 Receive pool settings3476.6.4 Data receive mode3486.6.5 VR4120A receive processing3516.6.6 USB controller receive processing3526.6.7 Detection of errors on USB3586.6.8 Rx data corruption on Isochronous EndPoint3606.6.9 Rx FIFO overrun3616.6.10 Rx indication3626.7 Power Management3646.7.1 Suspend3646.7.2 Resume3656.7.3 Remote wake up3666.8 Receiving SOF Packet3676.8.1 Receiving SOF Packet and updating the Frame Number3676.8.2 Updating Frame Number automatically3676.8.3 Checking if the skew of SOF arrival time is allowable of not3676.9 Loopback Mode3686.10 Example of Connection369CHAPTER 7 PCI CONTROLLER3707.1 Overview3707.2 Bus Bridge Functions3717.2.1 Internal bus to PCI transaction3717.2.2 PCI to internal bus transaction3767.2.3 Abnormal Termination3817.2.4 Warning for Deadlocks3827.3 PCI Power Management Interface3837.3.1 Power state3837.3.2 Power management event3837.3.3 Power supply3837.3.4 Power state transition3847.4 Functions in Host-mode3867.4.1 Generating configuration cycle3867.4.2 PCI bus arbiter3887.4.3 Reset output3897.4.4 Interrupt input3897.5 Registers3907.5.1 Register map3907.5.2 P_PLBA (PCI lower base address register)3917.5.3 P_IBBA (Internal bus base address register)3917.5.4 P_VERR (Version register)3917.5.5 P_PCAR (PCI Configuration Address Register)3927.5.6 P_PCDR (PCI Configuration Data Register)3927.5.7 P_IGSR (Internal bus-side General Status Register)3937.5.8 P_IIMR (Internal bus Interrupt Mask Register)3947.5.9 P_PGSR (PCI-side General Status Register)3957.5.10 P_IIMR (Internal bus Interrupt Mask Register)3967.5.11 P_PIMR (PCI Interrupt Mask Register)3977.5.12 P_HMCR (Host Mode Control Register)3987.5.13 P_PCDR (Power Consumption Data Register)3987.5.14 P_PDDR (Power Dissipation Data Register)3987.5.15 P_BCNT (Bridge Control Register)3997.5.16 P_PPCR (PCI Power Control Register)4007.5.17 P_SWRR (Software Reset Register)4007.5.18 P_RTMR (Retry Timer Register)4017.5.19 P_CONFIG (PCI configuration registers)4017.6 Information for Software4117.6.1 NIC mode4117.6.2 Host mode412CHAPTER 8 UART4148.1 Overview4148.2 UART Block Diagram4148.3 Registers4158.3.1 Register map4158.3.2 UARTRBR (UART Receiver data Buffer Register)4168.3.3 UARTTHR (UART Transmitter data Holding Register)4168.3.4 UARTIER (UART Interrupt Enable Register)4168.3.5 UARTDLL (UART Divisor Latch LSB Register)4168.3.6 UARTDLM (UART Divisor Latch MSB Register)4178.3.7 UARTIIR (UART Interrupt ID Register)4188.3.8 UARTFCR (UART FIFO Control Register)4198.3.9 UARTLCR (UART Line Control Register)4208.3.10 UARTMCR (UART Modem Control Register)4218.3.11 UARTLSR (UART Line Status Register)4228.3.12 UARTMSR (UART Modem Status Register)4238.3.13 UARTSCR (UART Scratch Register)423CHAPTER 9 TIMER4249.1 Overview4249.2 Block Diagram4249.3 Registers4259.3.1 Register map4259.3.2 TMMR (Timer Mode Register)4259.3.3 TM0CSR (Timer CH0 Count Set Register)4269.3.4 TM1CSR (Timer CH1 Count Set Register)4269.3.5 TM0CCR (Timer CH0 Current Count Register)4269.3.6 TM1CCR (Timer CH1 Current Count Register)426CHAPTER 10 MICRO WIRE42710.1 Overview42710.2 Operations42810.2.1 Data read at the power up load42810.2.2 Accessing to EEPROM42810.3 Registers42910.3.1 Register map42910.3.2 ECCR (EEPROM Command Control Register)42910.3.3 ERDR (EEPROM Read Data Register)42910.3.4 MACAR1 (MAC Address Register 1)42910.3.5 MACAR2 (MAC Address Register 2)42910.3.6 MACAR3 (MAC Address Register 3)430APPENDIX A MIPS III INSTRUCTION SET DETAILS431A.1 Instruction Notation Conventions431A.2 Load and Store Instructions433A.3 Jump and Branch Instructions434A.4 System Control Coprocessor (CP0) Instructions435A.5 CPU Instruction435A.6 CPU Instruction Opcode Bit Encoding588APPENDIX B VR4120A COPROCESSOR 0 HAZARDS590Size: 2.96 MBPages: 595Language: EnglishOpen manual