User ManualTable of ContentsCOVER1GENERAL21FUNCTION OVERVIEW22ORDERING INFORMATION23DIFFERENCES AMONG SUBSERIES PRODUCTS24BLOCK DIAGRAM25PIN CONFIGURATION [TOP VIEW]26PIN FUNCTIONS29PIN FUNCTIONS OF THE µPD75000829PIN FUNCTIONS32P00-P03 [PORT0]32P10-P13 [PORT1]32P20-P23 [PORT2]33P30-P33 [PORT3]33P40-P43 [PORT4], P50-P53 [PORT5]33P60-P63 [PORT6], P70-P73 [PORT7]33P80, P81 [PORT8]33TI033PTO0, PTO133PCL34BUZ34SCK, SO/SB0, SI/SB134INT434INT0, INT134INT235KR0-KR335KR4-KR735X1, X235XT1, XT236RESET36V DD36V SS36IC [for the µPD750004, µPD750006, and µPD750008 only]37V PP [for the µPD75P0016 only]37MD0-MD3 [for the µPD75P0016 only]37PIN INPUT/OUTPUT CIRCUITS38CONNECTION OF UNUSED PINS40FEATURES OF THE ARCHITECTURE AND MEMORY MAP41DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES41Data Memory Bank Structure41Data Memory Addressing Modes43GENERAL REGISTER BANK CONFIGURATION54MEMORY-MAPPED I/O59NTERNAL CPU FUNCTIONS65Mk I MODE/Mk II MODE SWITCH FUNCTIONS65Differences between Mk I Mode and Mk II Mode65Setting of the Stack Bank Selection Register [SBS]66PROGRAM COUNTER [PC]67PROGRAM MEMORY [ROM]68DATA MEMORY [RAM]73Data Memory Configuration73Specification of a Data Memory Bank74GENERAL REGISTER76ACCUMULATOR77STACK POINTER [SP] AND STACK BANK SELECT REGISTER [SBS]78PROGRAM STATUS WORD [PSW]82BANK SELECT REGISTER [BS]85PERIPHERAL HARDWARE FUNCTIONS87DIGITAL I/O PORTS87Types, Features, and Configurations of Digital I/O Ports88I/O Mode Setting94Digital I/O Port Manipulation Instructions96Digital I/O Port Operation99Specification of Bilt-in Pull-Up Resistors101I/O Timing of Digital I/O Ports102CLOCK GENERATOR104Clock Generator Configuration104Functions and Operations of the Clock Generator105System Clock and CPU Clock Setting114Clock Output Circuit116BASIC INTERVAL TIMER/WATCHDOG TIMER119Configuration of the Basic Interval Timer/Watchdog Timer119Basic Interval Timer Mode Register [BTM]119Watchdog Timer Enable Flag [WDTM]121Operation of the Basic Interval Timer121Operation of the Watchdog Timer122Other Functions123CLOCK TIMER125Configuration of the Clock Timer126Clock Mode Register126TIMER/EVENT COUNTER128Configuration of Timer/Event Counter1288-Bit Timer/Event Counter Mode Operation134Notes on Timer/Event Counter Applications140SERIAL INTERFACE143Serial Interface Functions143Configuration of Serial Interface144Register Functions147Operation Halt Mode155Three-Wire Serial I/O Mode Operations157Two-Wire Serial I/O Mode164SBI Mode Operation170Manipulation of SCK Pin Output199BIT SEQUENTIAL BUFFER201INTERRUPT AND TEST FUNCTIONS203CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT203TYPES OF INTERRUPT SOURCES AND VECTOR TABLES205VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS207INTERRUPT SEQUENCE215MULTIPLE INTERRUPT PROCESSING CONTROL216PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS218MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING220EFFECTIVE USE OF INTERRUPTS222INTERRUPT APPLICATIONS222TEST FUNCTION230Test Sources230Hardware to Control Test Functions230STANDBY FUNCTION235SETTING OF STANDBY MODES AND OPERATION STATUS236RELEASE OF THE STANDBY MODES237OPERATION AFTER A STANDBY MODE IS RELEASED239SELECTION OF A MASK OPTION240APPLICATIONS OF THE STANDBY MODES240RESET FUNCTION245WRITING TO AND VERIFYING PROGRAM MEMORY [PROM]249OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY250WRITING TO THE PROGRAM MEMORY250READING THE PROGRAM MEMORY252SCREENING OF ONE-TIME PROM253MASK OPTION255PIN255MASK OPTION OF STANDBY FUNCTION255MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK256INSTRUCTION SET257UNIQUE INSTRUCTIONS257GETI Instruction257Bit Manipulation Instructions258String-Effect Instructions258Number System Conversion Instructions259Skip Instructions and the Number of Machine Cycles Required for a Skip260INSTRUCTION SET AND OPERATION261INSTRUCTION CODES OF EACH INSTRUCTION278FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS284Transfer Instructions284Table Reference Instructions290Bit Transfer Instructions293Arithmetic/Logical Instructions293Accumulator Manipulation Instructions299Increment/Decrement Instructions299Compare Instructions300Carry Flag Manipulation Instructions301Memory Bit Manipulation Instructions302Branch Instructions304Subroutine Stack Control Instructions309Interrupt Control Instructions313I/O Instructions314CPU Control Instructions315Special Instructions315APPENDIX319FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016319DEVELOPMENT TOOLS321MASKED ROM ORDERING PROCEDURE329INSTRUCTION INDEX331D1 INSTRUCTION INDEX [BY FUNCTION]331D2 INSTRUCTION INDEX [ALPHABETICAL ORDER]334HARDWARE INDEX337E1 HARDWARE INDEX [ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME]337E2 HARDWARE INDEX [ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL]339REVISION HISTORY341Size: 1.02 MBPages: 342Language: EnglishOpen manual
User ManualTable of ContentsCOVER1GENERAL21FUNCTION OVERVIEW22ORDERING INFORMATION23DIFFERENCES AMONG SUBSERIES PRODUCTS24BLOCK DIAGRAM25PIN CONFIGURATION [TOP VIEW]26PIN FUNCTIONS29PIN FUNCTIONS OF THE µPD75000829PIN FUNCTIONS32P00-P03 [PORT0]32P10-P13 [PORT1]32P20-P23 [PORT2]33P30-P33 [PORT3]33P40-P43 [PORT4], P50-P53 [PORT5]33P60-P63 [PORT6], P70-P73 [PORT7]33P80, P81 [PORT8]33TI033PTO0, PTO133PCL34BUZ34SCK, SO/SB0, SI/SB134INT434INT0, INT134INT235KR0-KR335KR4-KR735X1, X235XT1, XT236RESET36V DD36V SS36IC [for the µPD750004, µPD750006, and µPD750008 only]37V PP [for the µPD75P0016 only]37MD0-MD3 [for the µPD75P0016 only]37PIN INPUT/OUTPUT CIRCUITS38CONNECTION OF UNUSED PINS40FEATURES OF THE ARCHITECTURE AND MEMORY MAP41DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES41Data Memory Bank Structure41Data Memory Addressing Modes43GENERAL REGISTER BANK CONFIGURATION54MEMORY-MAPPED I/O59NTERNAL CPU FUNCTIONS65Mk I MODE/Mk II MODE SWITCH FUNCTIONS65Differences between Mk I Mode and Mk II Mode65Setting of the Stack Bank Selection Register [SBS]66PROGRAM COUNTER [PC]67PROGRAM MEMORY [ROM]68DATA MEMORY [RAM]73Data Memory Configuration73Specification of a Data Memory Bank74GENERAL REGISTER76ACCUMULATOR77STACK POINTER [SP] AND STACK BANK SELECT REGISTER [SBS]78PROGRAM STATUS WORD [PSW]82BANK SELECT REGISTER [BS]85PERIPHERAL HARDWARE FUNCTIONS87DIGITAL I/O PORTS87Types, Features, and Configurations of Digital I/O Ports88I/O Mode Setting94Digital I/O Port Manipulation Instructions96Digital I/O Port Operation99Specification of Bilt-in Pull-Up Resistors101I/O Timing of Digital I/O Ports102CLOCK GENERATOR104Clock Generator Configuration104Functions and Operations of the Clock Generator105System Clock and CPU Clock Setting114Clock Output Circuit116BASIC INTERVAL TIMER/WATCHDOG TIMER119Configuration of the Basic Interval Timer/Watchdog Timer119Basic Interval Timer Mode Register [BTM]119Watchdog Timer Enable Flag [WDTM]121Operation of the Basic Interval Timer121Operation of the Watchdog Timer122Other Functions123CLOCK TIMER125Configuration of the Clock Timer126Clock Mode Register126TIMER/EVENT COUNTER128Configuration of Timer/Event Counter1288-Bit Timer/Event Counter Mode Operation134Notes on Timer/Event Counter Applications140SERIAL INTERFACE143Serial Interface Functions143Configuration of Serial Interface144Register Functions147Operation Halt Mode155Three-Wire Serial I/O Mode Operations157Two-Wire Serial I/O Mode164SBI Mode Operation170Manipulation of SCK Pin Output199BIT SEQUENTIAL BUFFER201INTERRUPT AND TEST FUNCTIONS203CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT203TYPES OF INTERRUPT SOURCES AND VECTOR TABLES205VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS207INTERRUPT SEQUENCE215MULTIPLE INTERRUPT PROCESSING CONTROL216PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS218MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING220EFFECTIVE USE OF INTERRUPTS222INTERRUPT APPLICATIONS222TEST FUNCTION230Test Sources230Hardware to Control Test Functions230STANDBY FUNCTION235SETTING OF STANDBY MODES AND OPERATION STATUS236RELEASE OF THE STANDBY MODES237OPERATION AFTER A STANDBY MODE IS RELEASED239SELECTION OF A MASK OPTION240APPLICATIONS OF THE STANDBY MODES240RESET FUNCTION245WRITING TO AND VERIFYING PROGRAM MEMORY [PROM]249OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY250WRITING TO THE PROGRAM MEMORY250READING THE PROGRAM MEMORY252SCREENING OF ONE-TIME PROM253MASK OPTION255PIN255MASK OPTION OF STANDBY FUNCTION255MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK256INSTRUCTION SET257UNIQUE INSTRUCTIONS257GETI Instruction257Bit Manipulation Instructions258String-Effect Instructions258Number System Conversion Instructions259Skip Instructions and the Number of Machine Cycles Required for a Skip260INSTRUCTION SET AND OPERATION261INSTRUCTION CODES OF EACH INSTRUCTION278FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS284Transfer Instructions284Table Reference Instructions290Bit Transfer Instructions293Arithmetic/Logical Instructions293Accumulator Manipulation Instructions299Increment/Decrement Instructions299Compare Instructions300Carry Flag Manipulation Instructions301Memory Bit Manipulation Instructions302Branch Instructions304Subroutine Stack Control Instructions309Interrupt Control Instructions313I/O Instructions314CPU Control Instructions315Special Instructions315APPENDIX319FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016319DEVELOPMENT TOOLS321MASKED ROM ORDERING PROCEDURE329INSTRUCTION INDEX331D1 INSTRUCTION INDEX [BY FUNCTION]331D2 INSTRUCTION INDEX [ALPHABETICAL ORDER]334HARDWARE INDEX337E1 HARDWARE INDEX [ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME]337E2 HARDWARE INDEX [ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL]339REVISION HISTORY341Size: 1.02 MBPages: 342Language: EnglishOpen manual