NEC uPD78052(A) User Manuals

NEC

User Manual (English)User Manual (English)

User Manual

Table of Contents

COVER
1
Major Revisions in This Edition
7
PREFACE
9
CHAPTER 1 GENERAL (uPD78054 Subseries)
37
- 1.1 Features
  37
- 1.2 Applications
  38
- 1.3 Ordering Information
  38
- 1.4 Quality Grade
  39
- 1.5 Pin Configuration (Top View)
  40
- 1.6 78K/0 Series Expansion
  43
- 1.7 Block Diagram
  45
- 1.8 Outline of Function
  46
- 1.9 Differences between Standard Quality Grade Products and (A) Products
  48
- 1.10 Mask Options
  48
CHAPTER 2 GENERAL (uPD78054Y Subseries)
49
- 2.1 Features
  49
- 2.2 Applications
  50
- 2.3 Ordering Information
  50
- 2.4 Quality Grade
  50
- 2.5 Pin Configuration (Top View)
  51
- 2.6 78K/0 Series Expansion
  54
- 2.7 Block Diagram
  56
- 2.8 Outline of Function
  57
- 2.9 Mask Options
  58
CHAPTER 3 PIN FUNCTION (uPD78054 Subseries)
59
- 3.1 Pin Function List
  59
  - 3.1.1 Normal operating mode pins
    59
  - 3.1.2 PROM programming mode pins (PROM versions only)
    63
- 3.2 Description of Pin Functions
  64
  - 3.2.1 P00 to P07 (Port 0)
    64
  - 3.2.2 P10 to P17 (Port 1)
    65
  - 3.2.3 P20 to P27 (Port 2)
    65
  - 3.2.4 P30 to P37 (Port 3)
    66
  - 3.2.5 P40 to P47 (Port 4)
    67
  - 3.2.6 P50 to P57 (Port 5)
    67
  - 3.2.7 P60 to P67 (Port 6)
    67
  - 3.2.8 P70 to P72 (Port 7)
    68
  - 3.2.9 P120 to P127 (Port 12)
    69
  - 3.2.10 P130 and P131 (Port 13)
    69
  - 3.2.11 AVREF0
    69
  - 3.2.12 AVREF1
    69
  - 3.2.13 AVDD
    70
  - 3.2.14 AVSS
    70
  - 3.2.15 RESET#
    70
  - 3.2.16 X1 and X2
    70
  - 3.2.17 XT1 and XT2
    70
  - 3.2.18 VDD
    70
  - 3.2.19 VSS
    70
  - 3.2.20 VPP (PROM versions only)
    70
  - 3.2.21 IC (Mask ROM version only)
    70
- 3.3 Input/output Circuits and Recommended Connection of Unused Pins
  71
CHAPTER 4 PIN FUNCTION (uPD78054Y Subseries)
75
- 4.1 Pin Function List
  75
  - 4.1.1 Normal operating mode pins
    75
  - 4.1.2 PROM programming mode pins (PROM versions only)
    79
- 4.2 Description of Pin Functions
  80
  - 4.2.1 P00 to P07 (Port 0)
    80
  - 4.2.2 P10 to P17 (Port 1)
    81
  - 4.2.3 P20 to P27 (Port 2)
    81
  - 4.2.4 P30 to P37 (Port 3)
    82
  - 4.2.5 P40 to P47 (Port 4)
    82
  - 4.2.6 P50 to P57 (Port 5)
    83
  - 4.2.7 P60 to P67 (Port 6)
    83
  - 4.2.8 P70 to P72 (Port 7)
    84
  - 4.2.9 P120 to P127 (Port 12)
    84
  - 4.2.10 P130 and P131 (Port 13)
    85
  - 4.2.11 AVREF0
    85
  - 4.2.12 AVREF1
    85
  - 4.2.13 AVDD
    85
  - 4.2.14 AVSS
    85
  - 4.2.15 RESET#
    85
  - 4.2.16 X1 and X2
    86
  - 4.2.17 XT1 and XT2
    86
  - 4.2.18 VDD
    86
  - 4.2.19 VSS
    86
  - 4.2.20 VPP (PROM versions only)
    86
  - 4.2.21 IC (Mask ROM version only)
    86
- 4.3 Input/output Circuits and Recommended Connection of Unused Pins
  87
CHAPTER 5 CPU ARCHITECTURE
91
- 5.1 Memory Spaces
  91
- 5.2 Processor Registers
  109
- 5.3 Instruction Address Addressing
  118
  - 5.3.1 Relative addressing
    118
  - 5.3.2 Immediate addressing
    119
  - 5.3.3 Table indirect addressing
    120
  - 5.3.4 Register addressing
    120
- 5.4 Operand Address Addressing
  121
CHAPTER 6 PORT FUNCTIONS
129
- 6.1 Port Functions
  129
- 6.2 Port Configuration
  134
  - 6.2.1 Port 0
    134
  - 6.2.2 Port 1
    136
  - 6.2.3 Port 2 (uPD78054 Subseries)
    137
  - 6.2.4 Port 2 (uPD78054Y Subseries)
    139
  - 6.2.5 Port 3
    141
  - 6.2.6 Port 4
    142
  - 6.2.7 Port 5
    143
  - 6.2.8 Port 6
    144
  - 6.2.9 Port 7
    146
  - 6.2.10 Port 12
    148
  - 6.2.11 Port 13
    149
- 6.3 Port Function Control Registers
  150
- 6.4 Port Function Operations
  156
- 6.5 Selection of Mask Option
  157
CHAPTER 7 CLOCK GENERATOR
159
- 7.1 Clock Generator Functions
  159
- 7.2 Clock Generator Configuration
  159
- 7.3 Clock Generator Control Register
  161
- 7.4 System Clock Oscillator
  165
- 7.5 Clock Generator Operations
  169
  - 7.5.1 Main system clock operations
    170
  - 7.5.2 Subsystem clock operations
    171
- 7.6 Changing System Clock and CPU Clock Settings
  171
  - 7.6.1 Time required for switchover between system clock and CPU clock
    171
  - 7.6.2 System clock and CPU clock switching procedure
    173
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
175
- 8.1 Outline of Timers Incorporated in the uPD78054, 78054Y Subseries
  175
- 8.2 16-Bit Timer/Event Counter Functions
  177
- 8.3 16-Bit Timer/Event Counter Configuration
  179
- 8.4 16-Bit Timer/Event Counter Control Registers
  182
- 8.5 16-Bit Timer/Event Counter Operations
  191
- 8.6 16-Bit Timer/Event Counter Operating Precautions
  212
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
215
- 9.1 8-Bit Timer/Event Counters 1 and 2 Functions
  215
  - 9.1.1 8-bit timer/event counter mode
    215
  - 9.1.2 16-bit timer/event counter mode
    218
- 9.2 8-Bit Timer/Event Counters 1 and 2 Configurations
  220
- 9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers
  223
- 9.4 8-Bit Timer/Event Counters 1 and 2 Operations
  228
  - 9.4.1 8-bit timer/event counter mode
    228
  - 9.4.2 16-bit timer/event counter mode
    234
- 9.5 Cautions on 8-Bit Timer/Event Counters 1 and 2
  238
CHAPTER 10 WATCH TIMER
241
- 10.1 Watch Timer Functions
  241
- 10.2 Watch Timer Configuration
  242
- 10.3 Watch Timer Control Registers
  242
- 10.4 Watch Timer Operations
  246
  - 10.4.1 Watch timer operation
    246
  - 10.4.2 Interval timer operation
    246
CHAPTER 11 WATCHDOG TIMER
247
- 11.1 Watchdog Timer Functions
  247
- 11.2 Watchdog Timer Configuration
  249
- 11.3 Watchdog Timer Control Registers
  250
- 11.4 Watchdog Timer Operations
  253
  - 11.4.1 Watchdog timer operation
    253
  - 11.4.2 Interval timer operation
    254
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
255
- 12.1 Clock Output Control Circuit Functions
  255
- 12.2 Clock Output Control Circuit Configuration
  256
- 12.3 Clock Output Function Control Registers
  257
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT
261
- 13.1 Buzzer Output Control Circuit Functions
  261
- 13.2 Buzzer Output Control Circuit Configuration
  261
- 13.3 Buzzer Output Function Control Registers
  262
CHAPTER 14 A/D CONVERTER
265
- 14.1 A/D Converter Functions
  265
- 14.2 A/D Converter Configuration
  265
- 14.3 A/D Converter Control Registers
  269
- 14.4 A/D Converter Operations
  273
- 14.5 A/D Converter Cautions
  278
CHAPTER 15 D/A CONVERTER
281
- 15.1 D/A Converter Functions
  281
- 15.2 D/A Converter Configuration
  282
- 15.3 D/A Converter Control Registers
  284
- 15.4 Operations of D/A Converter
  285
- 15.5 Cautions Related to D/A Converter
  286
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (uPD78054 Subseries)
287
- 16.1 Serial Interface Channel 0 Functions
  288
- 16.2 Serial Interface Channel 0 Configuration
  290
- 16.3 Serial Interface Channel 0 Control Registers
  294
- 16.4 Serial Interface Channel 0 Operations
  301
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (uPD78054Y Subseries)
341
- 17.1 Serial Interface Channel 0 Functions
  342
- 17.2 Serial Interface Channel 0 Configuration
  344
- 17.3 Serial Interface Channel 0 Control Registers
  348
- 17.4 Serial Interface Channel 0 Operations
  356
CHAPTER 18 SERIAL INTERFACE CHANNEL 1
393
- 18.1 Serial Interface Channel 1 Functions
  393
- 18.2 Serial Interface Channel 1 Configuration
  394
- 18.3 Serial Interface Channel 1 Control Registers
  397
- 18.4 Serial Interface Channel 1 Operations
  405
CHAPTER 19 SERIAL INTERFACE CHANNEL 2
439
- 19.1 Serial Interface Channel 2 Functions
  439
- 19.2 Serial Interface Channel 2 Configuration
  440
- 19.3 Serial Interface Channel 2 Control Registers
  444
- 19.4 Serial Interface Channel 2 Operation
  452
CHAPTER 20 REAL-TIME OUTPUT PORT
477
- 20.1 Real-Time Output Port Functions
  477
- 20.2 Real-Time Output Port Configuration
  478
- 20.3 Real-Time Output Port Control Registers
  480
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
483
- 21.1 Interrupt Function Types
  483
- 21.2 Interrupt Sources and Configuration
  484
- 21.3 Interrupt Function Control Registers
  488
- 21.4 Interrupt Servicing Operations
  497
- 21.5 Test Functions
  507
  - 21.5.1 Registers controlling the test function
    507
  - 21.5.2 Test input signal acknowledge operation
    509
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION
511
- 22.1 External Device Expansion Functions
  511
- 22.2 External Device Expansion Function Control Register
  516
- 22.3 External Device Expansion Function Timing
  518
- 22.4 Example of Connection with Memory
  523
CHAPTER 23 STANDBY FUNCTION
525
- 23.1 Standby Function and Configuration
  525
  - 23.1.1 Standby function
    525
  - 23.1.2 Standby function control register
    526
- 23.2 Standby Function Operations
  527
  - 23.2.1 HALT mode
    527
  - 23.2.2 STOP mode
    530
CHAPTER 24 RESET FUNCTION
533
- 24.1 Reset Function
  533
CHAPTER 25 ROM CORRECTION
537
- 25.1 ROM Correction Functions
  537
- 25.2 ROM Correction Configuration
  537
- 25.3 ROM Correction Control Registers
  539
- 25.4 ROM Correction Application
  540
- 25.5 ROM Correction Example
  543
- 25.6 Program Execution Flow
  544
- 25.7 Cautions on ROM Correction
  546
CHAPTER 26 uPD78P054, 78P058
547
- 26.1 Memory Size Switching Register (uPD78P054)
  549
- 26.2 Memory Size Switching Register (uPD78P058)
  550
- 26.3 Internal Expansion RAM Size Switching Register
  551
- 26.4 PROM Programming
  552
  - 26.4.1 Operating modes
    552
  - 26.4.2 PROM write procedure
    554
  - 26.4.3 PROM reading procedure
    558
- 26.5 Erasure Procedure (uPD78P054KK-T and 78P058KK-T Only)
  559
- 26.6 Opaque Film Masking the Window (uPD78P054KK-T and 78P058KK-T Only)
  559
- 26.7 Screening of One-Time PROM Versions
  559
CHAPTER 27 INSTRUCTION SET
561
- 27.1 Legends Used in Operation List
  562
- 27.2 Operation List
  564
- 27.3 Instructions Listed by Addressing Type
  572
APPENDIX A DIFFERENCES BETWEEN uPD78054, 78054Y SUBSERIES AND uPD78058F, 78058FY SUBSERIES
577
APPENDIX B DEVELOPMENT TOOLS
579
- B.1 Language Processing Software
  582
- B.2 PROM Writing Tools
  584
  - B.2.1 Hardware
    584
  - B.2.2 Software
    584
- B.3 Debugging Tools
  585
  - B.3.1 Hardware
    585
  - B.3.2 Software
    587
- B.4 OS for IBM PC
  589
- B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A
  589
APPENDIX C EMBEDDED SOFTWARE
593
APPENDIX D REGISTER INDEX
595
- D.1 Register Index
  595
APPENDIX E REVISION HISTORY
599

Size:

3.21 MB
Pages:

603
Language:

English

User Manual

Table of Contents

Size:

3.21 MB
Pages:

603
Language:

English