PMC-Sierra PM5349 User Manuals

Table of Contents

• FEATURES

  1
• GENERAL

  1
• THE SONET RECEIVER

  1
• THE RECEIVE ATM PROCESSOR

  2
• THE SONET TRANSMITTER

  2
• THE TRANSMIT ATM PROCESSOR

  3
• APPLICATIONS

  4
• REFERENCES

  5
• DEFINITIONS

  6
• APPLICATION EXAMPLES

  7
• BLOCK DIAGRAM

  8
• DESCRIPTION

  9
• PIN DIAGRAM

  11
• PIN DESCRIPTION

  12
• LINE SIDE INTERFACE SIGNALS

  12
• UTOPIA LEVEL 2 SYSTEM INTERFACE

  15
• MICROPROCESSOR INTERFACE SIGNALS

  23
• JTAG TEST ACCESS PORT (TAP) SIGNALS

  25
• ANALOG SIGNALS

  26
• POWER AND GROUND

  26
• FUNCTIONAL DESCRIPTION

  32
• RECEIVE LINE INTERFACE (CRSI)

  32
• CLOCK RECOVERY

  32
• SERIAL TO PARALLEL CONVERTER

  33
• RECEIVE SECTION OVERHEAD PROCESSOR (RSOP)

  33
• FRAMER

  33
• DESCRAMBLE

  34
• ERROR MONITOR

  34
• LOSS OF SIGNAL

  34
• LOSS OF FRAME

  35
• RECEIVE LINE OVERHEAD PROCESSOR (RLOP)

  35
• LINE RDI DETECT

  35
• LINE AIS DETECT

  35
• ERROR MONITOR BLOCK

  35
• MONITOR (RASE)

  36
• AUTOMATIC PROTECTION SWITCH CONTROL

  36
• BIT ERROR RATE MONITOR

  37
• SYNCHRONIZATION STATUS EXTRACTION

  37
• RECEIVE PATH OVERHEAD PROCESSOR (RPOP)

  38
• POINTER INTERPRETER

  38
• SPE TIMING

  42
• ERROR MONITOR

  42
• RECEIVE ATM CELL PROCESSOR (RXCP)

  43
• CELL DELINEATION

  43
• DESCRAMBLER

  44
• CELL FILTER AND HCS VERIFICATION

  44
• PERFORMANCE MONITOR

  46
• TRANSMIT LINE INTERFACE (CSPI)

  46
• CLOCK SYNTHESIS

  46
• PARALLEL TO SERIAL CONVERTER

  47
• TRANSMIT SECTION OVERHEAD PROCESSOR (TSOP)

  47
• LINE AIS INSERT

  47
• BIP-8 INSERT

  47
• FRAMING AND IDENTITY INSERT

  48
• SCRAMBLER

  48
• TRANSMIT LINE OVERHEAD PROCESSOR (TLOP)

  48
• APS INSERT

  48
• LINE BIP CALCULATE

  48
• LINE RDI INSERT

  48
• LINE FEBE INSERT

  49
• TRANSMIT PATH OVERHEAD PROCESSOR (TPOP)

  49
• POINTER GENERATOR

  49
• BIP-8 CALCULATE

  50
• FEBE CALCULATE

  50
• TRANSMIT ATM CELL PROCESSOR (TXCP)

  50
• IDLE/UNASSIGNED CELL GENERATOR

  50
• SCRAMBLER

  50
• HCS GENERATOR

  51
• UTOPIA LEVEL 2 SYSTEM INTERFACE

  51
• RECEIVE ATM INTERFACE

  51
• TRANSMIT ATM INTERFACE

  51
• JTAG TEST ACCESS PORT

  52
• MICROPROCESSOR INTERFACE

  52
• NORMAL MODE REGISTER DESCRIPTION

  59
• TEST FEATURES DESCRIPTION

  193
• MASTER TEST REGISTER

  193
• TEST MODE 0 DETAILS

  195
• JTAG TEST PORT

  196
• BOUNDARY SCAN CELLS

  198
• OPERATION

  201
• SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE

  201
• ATM MAPPING

  201
• TRANSPORT AND PATH OVERHEAD BYTES

  202
• ATM CELL DATA STRUCTURE

  204
• BIT ERROR RATE MONITOR

  205
• CLOCKING OPTIONS

  206
• LOOPBACK OPERATION

  208
• JTAG SUPPORT

  212
• TAP CONTROLLER

  213
• STATES

  215
• INSTRUCTIONS

  216
• BOARD DESIGN RECOMMENDATIONS

  217
• POWER SUPPLY SEQUENCING

  218
• ANALOG POWER SUPPLY FILTERING

  219
• INTERFACING TO ECL OR PECL DEVICES

  220
• INITIALIZING THE S/UNI-QUAD

  222
• USING THE S/UNI-QUAD WITH A 5 VOLT ODL

  222
• FUNCTIONAL TIMING

  223
• ATM UTOPIA LEVEL 2 SYSTEM INTERFACE

  223
• ABSOLUTE MAXIMUM RATINGS

  226
• D.C. CHARACTERISTICS

  227
• MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS

  229
• A.C. TIMING CHARACTERISTICS

  233
• SYSTEM RESET TIMING

  233
• REFERENCE TIMING

  233
• ATM SYSTEM INTERFACE TIMING

  234
• TRANSMIT AND RECEIVE FRAME PULSES

  238
• JTAG TEST PORT TIMING

  239
• ORDERING AND THERMAL INFORMATION

  242
• MECHANICAL INFORMATION

  244