User ManualTable of ContentsCOVER1Notice2NOTES FOR CMOS DEVICES3How to Use This Manual4CONTENTS7CHAPTER 1 OUTLINE211.1 Features211.2 List of Part Numbers241.3 Pin Configuration (Top View)261.3.1 25-pin products261.3.2 32-pin products271.3.3 48-pin products281.3.4 64-pin products301.4 Pin Identification321.5 Block Diagram331.5.1 25-pin products331.5.2 32-pin products341.5.3 48-pin products351.5.4 64-pin products361.6 Outline of Functions37CHAPTER 2 PIN FUNCTIONS392.1 Port Function392.1.1 25-pin products402.1.2 32-pin products422.1.3 48-pin products442.1.4 64-pin products462.2 Functions Other than Port Pins492.2.1 With functions for each product492.2.2 Explanation of function532.3 Pin I/O Circuits and Recommended Connection of Unused Pins552.4 Block Diagrams of Pins56CHAPTER 3 CPU ARCHITECTURE673.1 Memory Space673.1.1 Internal program memory space743.1.2 Mirror area773.1.3 Internal data memory space793.1.4 Special function register (SFR) area803.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area803.1.6 Data memory addressing813.2 Processor Registers823.2.1 Control registers823.2.2 General-purpose registers843.2.3 ES and CS registers853.2.4 Special function registers (SFRs)863.2.5 Extended special function registers (2nd SFRs)923.3 Instruction Address Addressing993.3.1 Relative addressing993.3.2 Immediate addressing993.3.3 Table indirect addressing1003.3.4 Register direct addressing1013.4 Addressing for Processing Data Addresses1023.4.1 Implied addressing1023.4.2 Register addressing1023.4.3 Direct addressing1033.4.4 Short direct addressing1043.4.5 SFR addressing1053.4.6 Register indirect addressing1063.4.7 Based addressing1073.4.8 Based indexed addressing1113.4.9 Stack addressing112CHAPTER 4 PORT FUNCTIONS1164.1 Port Functions1164.2 Port Configuration1174.2.1 Port 01184.2.2 Port 11184.2.3 Port 21194.2.4 Port 31194.2.5 Port 41204.2.6 Port 51204.2.7 Port 61204.2.8 Port 71214.2.9 Port 121214.2.10 Port 131214.2.11 Port 141224.2.12 Port 151224.3 Registers Controlling Port Function1234.3.1 Port mode registers (PMxx)1254.3.2 Port registers (Pxx)1264.3.3 Pull-up resistor option registers (PUxx)1274.3.4 Port input mode registers (PIMxx)1284.3.5 Port output mode registers (POMxx)1294.3.6 Port mode control registers (PMCxx)1304.3.7 A/D port configuration register (ADPC)1314.3.8 Peripheral I/O redirection register (PIOR)1324.3.9 Global digital input disable register (GDIDIS)1334.3.10 Global analog input disable register (GAIDIS)1344.4 Port Function Operations1354.4.1 Writing to I/O port1354.4.2 Reading from I/O port1354.4.3 Operations on I/O port1354.4.4 Handling different potential (1.8 V or 2.5 V) by using EVDD ≤ VDD1364.4.5 Handling different potential (1.8 V or 2.5 V) by using I/O buffers1364.5 Register Settings When Using Alternate Function1384.5.1 Basic concept when using alternate function1384.5.2 Register settings for alternate function whose output function is not used1394.5.3 Register setting examples for used port and alternate functions1404.6 Cautions When Using Port Function1574.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn)1574.6.2 Notes on specifying the pin settings158CHAPTER 5 CLOCK GENERATOR1595.1 Functions of Clock Generator1595.2 Configuration of Clock Generator1615.3 Registers Controlling Clock Generator1635.3.1 Clock operation mode control register (CMC)1635.3.2 System clock control register (CKC)1665.3.3 Clock operation status control register (CSC)1675.3.4 Oscillation stabilization time counter status register (OSTC)1685.3.5 Oscillation stabilization time select register (OSTS)1705.3.6 Peripheral enable register 0 (PER0)1725.3.7 Subsystem clock supply mode control register (OSMC)1755.3.8 High-speed on-chip oscillator frequency select register (HOCODIV)1765.3.9 High-speed on-chip oscillator trimming register (HIOTRM)1775.4 System Clock Oscillator1785.4.1 X1 oscillator1785.4.2 XT1 oscillator1785.4.3 High-speed on-chip oscillator1825.4.4 Low-speed on-chip oscillator1825.5 Clock Generator Operation1835.6 Controlling Clock1855.6.1 Example of setting high-speed on-chip oscillator1855.6.2 Example of setting X1 oscillation clock1865.6.3 Example of setting XT1 oscillation clock1875.6.4 CPU clock status transition diagram1885.6.5 Condition before changing CPU clock and processing after changing CPU clock1945.6.6 Time required for switchover of CPU clock and system clock1965.6.7 Conditions before clock oscillation is stopped1975.7 Resonator and Oscillator Constants198CHAPTER 6 TIMER ARRAY UNIT2026.1 Functions of Timer Array Unit2046.1.1 Independent channel operation function2046.1.2 Simultaneous channel operation function2056.1.3 8-bit timer operation function (channels 1 and 3 only)2066.1.4 LIN-bus supporting function (channel 7 of unit 0 only)2076.2 Configuration of Timer Array Unit2086.2.1 Timer count register mn (TCRmn)2136.2.2 Timer data register mn (TDRmn)2156.3 Registers Controlling Timer Array Unit2166.3.1 Peripheral enable register 0 (PER0)2176.3.2 Timer clock select register m (TPSm)2186.3.3 Timer mode register mn (TMRmn)2216.3.4 Timer status register mn (TSRmn)2266.3.5 Timer channel enable status register m (TEm)2276.3.6 Timer channel start register m (TSm)2286.3.7 Timer channel stop register m (TTm)2296.3.8 Timer input select register 0 (TIS0)2306.3.9 Timer output enable register m (TOEm)2316.3.10 Timer output register m (TOm)2326.3.11 Timer output level register m (TOLm)2336.3.12 Timer output mode register m (TOMm)2346.3.13 Input switch control register (ISC)2356.3.14 Noise filter enable register 1 (NFEN1)2366.3.15 Registers controlling port functions of pins to be used for timer I/O2386.4 Basic Rules of Timer Array Unit2396.4.1 Basic rules of simultaneous channel operation function2396.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only)2416.5 Operation of Counter2426.5.1 Count clock (fTCLK)2426.5.2 Start timing of counter2446.5.3 Operation of counter2456.6 Channel Output (TOmn Pin) Control2506.6.1 TOmn pin output circuit configuration2506.6.2 TOmn pin output setting2516.6.3 Cautions on channel output operation2526.6.4 Collective manipulation of TOmn bit2576.6.5 Timer interrupt and TOmn pin output at operation start2586.7 Timer Input (TImn) Control2596.7.1 TImn pin input circuit configuration2596.7.2 Noise filter2596.7.3 Cautions on channel input2606.8 Independent Channel Operation Function of Timer Array Unit2616.8.1 Operation as interval timer/square wave output2616.8.2 Operation as external event counter2676.8.3 Operation as frequency divider (channel 0 of unit 0 only)2726.8.4 Operation as input pulse interval measurement2766.8.5 Operation as input signal high-/low-level width measurement2806.8.6 Operation as delay counter2846.9 Simultaneous Channel Operation Function of Timer Array Unit2896.9.1 Operation as one-shot pulse output function2896.9.2 Operation as PWM function2966.9.3 Operation as multiple PWM output function3036.10 Cautions When Using Timer Array Unit3116.10.1 Cautions when using timer output311CHAPTER 7 REAL-TIME CLOCK3127.1 Functions of Real-time Clock3127.2 Configuration of Real-time Clock3137.3 Registers Controlling Real-time Clock3157.3.1 Peripheral enable register 0 (PER0)3167.3.2 Subsystem clock supply mode control register (OSMC)3177.3.3 Real-time clock control register 0 (RTCC0)3187.3.4 Real-time clock control register 1 (RTCC1)3197.3.5 Second count register (SEC)3217.3.6 Minute count register (MIN)3217.3.7 Hour count register (HOUR)3227.3.8 Day count register (DAY)3247.3.9 Week count register (WEEK)3257.3.10 Month count register (MONTH)3267.3.11 Year count register (YEAR)3267.3.12 Watch error correction register (SUBCUD)3277.3.13 Alarm minute register (ALARMWM)3287.3.14 Alarm hour register (ALARMWH)3287.3.15 Alarm week register (ALARMWW)3287.3.16 Port mode register 3 (PM3)3297.3.17 Port register 3 (P3)3297.4 Real-time Clock Operation3307.4.1 Starting operation of real-time clock3307.4.2 Shifting to HALT/STOP mode after starting operation3317.4.3 Reading/writing real-time clock3327.4.4 Setting alarm of real-time clock3347.4.5 1 Hz output of real-time clock3357.4.6 Example of watch error correction of real-time clock336CHAPTER 8 12-BIT INTERVAL TIMER3418.1 Functions of 12-bit Interval Timer3418.2 Configuration of 12-bit Interval Timer3418.3 Registers Controlling 12-bit Interval Timer3428.3.1 Peripheral enable register 0 (PER0)3428.3.2 Subsystem clock supply mode control register (OSMC)3438.3.3 Interval timer control register (ITMC)3448.4 12-bit Interval Timer Operation3458.4.1 12-bit interval timer operation timing3458.4.2 Starting counter operation after returning from HALT or STOP mode and then shifting to HALT or STOP mode again346CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER3479.1 Functions of Clock Output/Buzzer Output Controller3479.2 Configuration of Clock Output/Buzzer Output Controller3499.3 Registers Controlling Clock Output/Buzzer Output Controller3499.3.1 Clock output select registers n (CKSn)3499.3.2 Registers controlling port functions of pins to be used for clock or buzzer output3519.4 Operations of Clock Output/Buzzer Output Controller3529.4.1 Operation as output pin3529.5 Cautions of Clock Output/Buzzer Output Controller352CHAPTER 10 WATCHDOG TIMER35310.1 Functions of Watchdog Timer35310.2 Configuration of Watchdog Timer35410.3 Register Controlling Watchdog Timer35510.3.1 Watchdog timer enable register (WDTE)35510.4 Operation of Watchdog Timer35610.4.1 Controlling operation of watchdog timer35610.4.2 Setting overflow time of watchdog timer35710.4.3 Setting window open period of watchdog timer35810.4.4 Setting watchdog timer interval interrupt359CHAPTER 11 A/D CONVERTER36011.1 Function of A/D Converter36011.2 Configuration of A/D Converter36311.3 Registers Used in A/D Converter36511.3.1 Peripheral enable register 0 (PER0)36611.3.2 A/D converter mode register 0 (ADM0)36711.3.3 A/D converter mode register 1 (ADM1)37911.3.4 A/D converter mode register 2 (ADM2)38011.3.5 12-bit A/D conversion result register (ADCR)38211.3.6 8-bit A/D conversion result register (ADCRH)38311.3.7 Analog input channel specification register (ADS)38411.3.8 Conversion result comparison upper limit setting register (ADUL)38611.3.9 Conversion result comparison lower limit setting register (ADLL)38611.3.10 A/D test register (ADTES)38711.3.11 Registers controlling port function of analog input pins38811.4 A/D Converter Conversion Operations38911.5 Input Voltage and Conversion Results39111.6 A/D Converter Operation Modes39211.6.1 Software trigger mode (select mode, sequential conversion mode)39211.6.2 Software trigger mode (select mode, one-shot conversion mode)39311.6.3 Software trigger mode (scan mode, sequential conversion mode)39411.6.4 Software trigger mode (scan mode, one-shot conversion mode)39511.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode)39611.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode)39711.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode)39811.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode)39911.6.9 Hardware trigger wait mode (select mode, sequential conversion mode)40011.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)40111.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode)40211.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode)40311.7 A/D Converter Setup Flowchart40411.7.1 Setting up software trigger mode40511.7.2 Setting up hardware trigger no-wait mode40611.7.3 Setting up hardware trigger wait mode40711.7.4 Setup when temperature sensor output voltage/internal reference voltage is selected (example for software trigger mode and one-shot conversion mode)40811.7.5 Setting up test mode40911.8 SNOOZE Mode Function41011.9 How to Read A/D Converter Characteristics Table41411.10 Cautions for A/D Converter416CHAPTER 12 SERIAL ARRAY UNIT42012.1 Functions of Serial Array Unit42112.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21)42112.1.2 UART (UART0 to UART2)42212.1.3 Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)42312.2 Configuration of Serial Array Unit42412.2.1 Shift register42712.2.2 Lower 8/9 bits of the serial data register mn (SDRmn)42712.3 Registers Controlling Serial Array Unit42912.3.1 Peripheral enable register 0 (PER0)43012.3.2 Serial clock select register m (SPSm)43112.3.3 Serial mode register mn (SMRmn)43212.3.4 Serial communication operation setting register mn (SCRmn)43312.3.5 Higher 7 bits of the serial data register mn (SDRmn)43612.3.6 Serial flag clear trigger register mn (SIRmn)43812.3.7 Serial status register mn (SSRmn)43912.3.8 Serial channel start register m (SSm)44112.3.9 Serial channel stop register m (STm)44212.3.10 Serial channel enable status register m (SEm)44312.3.11 Serial output enable register m (SOEm)44412.3.12 Serial output register m (SOm)44512.3.13 Serial output level register m (SOLm)44612.3.14 Serial standby control register 0 (SSC0)44812.3.15 Input switch control register (ISC)44912.3.16 Noise filter enable register 0 (NFEN0)45012.3.17 Registers controlling port functions of serial input/output pins45112.4 Operation Stop Mode45212.4.1 Stopping the operation by units45212.4.2 Stopping the operation by channels45312.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) Communication45412.5.1 Master transmission45712.5.2 Master reception46712.5.3 Master transmission/reception47712.5.4 Slave transmission48712.5.5 Slave reception49712.5.6 Slave transmission/reception50512.5.7 SNOOZE mode function51512.5.8 Calculating transfer clock frequency51912.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) communication52112.6 Operation of UART (UART0 to UART2) Communication52212.6.1 UART transmission52512.6.2 UART reception53512.6.3 SNOOZE mode function54212.6.4 Calculating baud rate55012.6.5 Procedure for processing errors that occurred during UART (UART0 to UART2) communication55412.7 LIN Communication Operation55512.7.1 LIN transmission55512.7.2 LIN reception55812.8 Operation of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) Communication56412.8.1 Address field transmission56712.8.2 Data transmission57312.8.3 Data reception57712.8.4 Stop condition generation58212.8.5 Calculating transfer rate58312.8.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication585CHAPTER 13 SERIAL INTERFACE IICA58613.1 Functions of Serial Interface IICA58613.2 Configuration of Serial Interface IICA58913.3 Registers Controlling Serial Interface IICA59213.3.1 Peripheral enable register 0 (PER0)59213.3.2 IICA control register 00 (IICCTL00)59313.3.3 IICA status register 0 (IICS0)59813.3.4 IICA flag register 0 (IICF0)60113.3.5 IICA control register 01 (IICCTL01)60313.3.6 IICA low-level width setting register 0 (IICWL0)60513.3.7 IICA high-level width setting register 0 (IICWH0)60513.3.8 Port mode register 6 (PM6)60613.4 I2C Bus Mode Functions60713.4.1 Pin configuration60713.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers60813.5 I2C Bus Definitions and Control Methods61013.5.1 Start conditions61013.5.2 Addresses61113.5.3 Transfer direction specification61113.5.4 Acknowledge (ACK)61213.5.5 Stop condition61313.5.6 Wait61413.5.7 Canceling wait61613.5.8 Interrupt request (INTIICA0) generation timing and wait control61713.5.9 Address match detection method61813.5.10 Error detection61813.5.11 Extension code61813.5.12 Arbitration61913.5.13 Wakeup function62113.5.14 Communication reservation62413.5.15 Cautions62813.5.16 Communication operations62913.5.17 Timing of I2C interrupt request (INTIICA0) occurrence63613.6 Timing Charts657CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR67214.1 Functions of Multiplier and Divider/Multiply-Accumulator67214.2 Configuration of Multiplier and Divider/Multiply-Accumulator67214.2.1 Multiplication/division data register A (MDAH, MDAL)67414.2.2 Multiplication/division data register B (MDBL, MDBH)67514.2.3 Multiplication/division data register C (MDCL, MDCH)67614.3 Register Controlling Multiplier and Divider/Multiply-Accumulator67814.3.1 Multiplication/division control register (MDUC)67814.4 Operations of Multiplier and Divider/Multiply-Accumulator68014.4.1 Multiplication (unsigned) operation68014.4.2 Multiplication (signed) operation68114.4.3 Multiply-accumulation (unsigned) operation68214.4.4 Multiply-accumulation (signed) operation68414.4.5 Division operation686CHAPTER 15 DMA CONTROLLER68815.1 Functions of DMA Controller68815.2 Configuration of DMA Controller68915.2.1 DMA SFR address register n (DSAn)68915.2.2 DMA RAM address register n (DRAn)69015.2.3 DMA byte count register n (DBCn)69115.3 Registers Controlling DMA Controller69215.3.1 DMA mode control register n (DMCn)69215.3.2 DMA operation control register n (DRCn)69415.4 Operation of DMA Controller69515.4.1 Operation procedure69515.4.2 Transfer mode69615.4.3 Termination of DMA transfer69615.5 Example of Setting of DMA Controller69715.5.1 CSI consecutive transmission69715.5.2 Consecutive capturing of A/D conversion results69915.5.3 UART consecutive reception + ACK transmission70115.5.4 Holding DMA transfer pending by DWAITn bit70215.5.5 Forced termination by software70315.6 Cautions on Using DMA Controller705CHAPTER 16 INTERRUPT FUNCTIONS70816.1 Interrupt Function Types70816.2 Interrupt Sources and Configuration70816.3 Registers Controlling Interrupt Functions71416.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)71816.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)71916.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H)72116.3.4 External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge enable registers (EGN0, EGN1)72316.3.5 Program status word (PSW)72516.4 Interrupt Servicing Operations72616.4.1 Maskable interrupt request acknowledgment72616.4.2 Software interrupt request acknowledgment72916.4.3 Multiple interrupt servicing72916.4.4 Interrupt request hold733CHAPTER 17 KEY INTERRUPT FUNCTION73417.1 Functions of Key Interrupt73417.2 Configuration of Key Interrupt73517.3 Register Controlling Key Interrupt73717.3.1 Key return control register (KRCTL)73717.3.2 Key return mode registers 0, 1 (KRM0, KRM1)73817.3.3 Key return flag register (KRF)73917.3.4 Port mode registers 0 to 2, 7, 12, 15 (PM0 to PM2, PM7, PM12, PM15)74017.3.5 Peripheral I/O redirection register (PIOR)74117.4 Key Interrupt Operation74217.4.1 When not using the key interrupt flag (KRMD = 0)74217.4.2 When using the key interrupt flag (KRMD = 1)743CHAPTER 18 STANDBY FUNCTION74618.1 Standby Function74618.2 Registers Controlling Standby Function74718.3 Standby Function Operation74718.3.1 HALT mode74718.3.2 STOP mode75218.3.3 SNOOZE mode757CHAPTER 19 RESET FUNCTION76019.1 Timing of Reset Operation76219.2 States of Operation During Reset Periods76419.3 Register for Confirming Reset Source76619.3.1 Reset control flag register (RESF)766CHAPTER 20 POWER-ON-RESET CIRCUIT76920.1 Functions of Power-on-reset Circuit76920.2 Configuration of Power-on-reset Circuit77020.3 Operation of Power-on-reset Circuit770CHAPTER 21 VOLTAGE DETECTOR77421.1 Functions of Voltage Detector77421.2 Configuration of Voltage Detector77521.3 Registers Controlling Voltage Detector77521.3.1 Voltage detection register (LVIM)77621.3.2 Voltage detection level register (LVIS)77721.4 Operation of Voltage Detector78021.4.1 When used as reset mode78021.4.2 When used as interrupt mode78221.4.3 When used as interrupt & reset mode78421.5 Cautions for Voltage Detector790CHAPTER 22 SAFETY FUNCTIONS79222.1 Overview of Safety Functions79222.2 Registers Used by Safety Functions79322.3 Operation of Safety Functions79322.3.1 Flash memory CRC operation function (high-speed CRC)79322.3.2 CRC operation function (general-purpose CRC)79622.3.3 RAM parity error detection function79822.3.4 RAM guard function80022.3.5 SFR guard function80122.3.6 Invalid memory access detection function80222.3.7 Frequency detection function80422.3.8 A/D test function806CHAPTER 23 REGULATOR81123.1 Regulator Overview811CHAPTER 24 OPTION BYTE81224.1 Functions of Option Bytes81224.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H)81224.1.2 On-chip debug option byte (000C3H/ 010C3H)81324.2 Format of User Option Byte81424.3 Format of On-chip Debug Option Byte81824.4 Setting of Option Byte819CHAPTER 25 FLASH MEMORY82025.1 Serial Programming Using Flash Memory Programmer82225.1.1 Programming environment82425.1.2 Communication mode82425.2 Serial Programming Using External Device (that Incorporates UART)82525.2.1 Programming environment82525.2.2 Communication mode82625.3 Connection of Pins on Board82725.3.1 P40/TOOL0 pin82725.3.2 RESET pin82725.3.3 Port pins82825.3.4 REGC pin82825.3.5 X1 and X2 pins82825.3.6 Power supply82825.4 Serial Programming Method82925.4.1 Serial programming procedure82925.4.2 Flash memory programming mode83025.4.3 Selecting communication mode83225.4.4 Communication commands83225.5 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value)83425.6 Self-Programming83525.6.1 Self-programming procedure83625.6.2 Boot swap function83725.6.3 Flash shield window function83925.7 Security Settings84025.8 Data Flash84225.8.1 Data flash overview84225.8.2 Register controlling data flash memory84225.8.3 Procedure for accessing data flash memory843CHAPTER 26 ON-CHIP DEBUG FUNCTION84426.1 Connecting E1 On-Chip Debugging Emulator84426.2 On-Chip Debug Security ID84526.3 Securing of User Resources845CHAPTER 27 BCD CORRECTION CIRCUIT84727.1 BCD Correction Circuit Function84727.2 Registers Used by BCD Correction Circuit84727.2.1 BCD correction result register (BCDADJ)84727.3 BCD Correction Circuit Operation848CHAPTER 28 INSTRUCTION SET85028.1 Conventions Used in Operation List85028.1.1 Operand identifiers and specification methods85028.1.2 Description of operation column85128.1.3 Description of flag operation column85228.1.4 PREFIX instruction85228.2 Operation List853CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = -40 to +85 degree)87029.1 Absolute Maximum Ratings87129.2 Oscillator Characteristics87329.2.1 X1, XT1 oscillator characteristics87329.2.2 On-chip oscillator characteristics87329.3 DC Characteristics87429.3.1 Pin characteristics87429.3.2 Supply current characteristics87929.4 AC Characteristics88529.5 Peripheral Functions Characteristics89029.5.1 Serial array unit89029.5.2 Serial interface IICA91329.6 Analog Characteristics91629.6.1 A/D converter characteristics91629.6.2 Temperature sensor, internal reference voltage output characteristics92129.6.3 POR circuit characteristics92129.6.4 LVD circuit characteristics92229.6.5 Supply voltage rise slope characteristics92329.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics92429.8 Flash Memory Programming Characteristics92429.9 Dedicated Flash Memory Programmer Communication (UART)92429.10 Timing Specs for Switching Flash Memory Programming Modes925CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105 degree)92630.1 Absolute Maximum Ratings92730.2 Oscillator Characteristics92930.2.1 X1, XT1 oscillator characteristics92930.2.2 On-chip oscillator characteristics92930.3 DC Characteristics93030.3.1 Pin characteristics93030.3.2 Supply current characteristics93530.4 AC Characteristics94130.5 Peripheral Functions Characteristics94530.5.1 Serial array unit94530.5.2 Serial interface IICA96330.6 Analog Characteristics96430.6.1 A/D converter characteristics96430.6.2 Temperature sensor, internal reference voltage output characteristics96830.6.3 POR circuit characteristics96830.6.4 LVD circuit characteristics96930.6.5 Supply voltage rise slope characteristics96930.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics97030.8 Flash Memory Programming Characteristics97030.9 Dedicated Flash Memory Programmer Communication (UART)97030.10 Timing Specs for Switching Flash Memory Programming Modes971CHAPTER 31 PACKAGE DRAWINGS97231.1 25-pin Products97231.2 32-pin Products97331.3 48-pin Products97431.4 64-pin Products976APPENDIX A REVISION HISTORY978A.1 Major Revisions in This Edition978A.2 Revision History of Preceding Editions989Colophon1002Address List1003Back Cover1004Size: 9.13 MBPages: 1004Language: EnglishOpen manual