Renesas rl78 User Manuals

Table of Contents

• COVER

  1
• Notice

  2
• NOTES FOR CMOS DEVICES

  3
• How to Use This Manual

  4
• CONTENTS

  7
• CHAPTER 1 OUTLINE

  21
  • 1.1 Features

    21
  • 1.2 List of Part Numbers

    24
  • 1.3 Pin Configuration (Top View)

    26
    • 1.3.1 25-pin products

      26
    • 1.3.2 32-pin products

      27
    • 1.3.3 48-pin products

      28
    • 1.3.4 64-pin products

      30
  • 1.4 Pin Identification

    32
  • 1.5 Block Diagram

    33
    • 1.5.1 25-pin products

      33
    • 1.5.2 32-pin products

      34
    • 1.5.3 48-pin products

      35
    • 1.5.4 64-pin products

      36
  • 1.6 Outline of Functions

    37
• CHAPTER 2 PIN FUNCTIONS

  39
  • 2.1 Port Function

    39
    • 2.1.1 25-pin products

      40
    • 2.1.2 32-pin products

      42
    • 2.1.3 48-pin products

      44
    • 2.1.4 64-pin products

      46
  • 2.2 Functions Other than Port Pins

    49
    • 2.2.1 With functions for each product

      49
    • 2.2.2 Explanation of function

      53
  • 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

    55
  • 2.4 Block Diagrams of Pins

    56
• CHAPTER 3 CPU ARCHITECTURE

  67
  • 3.1 Memory Space

    67
    • 3.1.1 Internal program memory space

      74
    • 3.1.2 Mirror area

      77
    • 3.1.3 Internal data memory space

      79
    • 3.1.4 Special function register (SFR) area

      80
    • 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area

      80
    • 3.1.6 Data memory addressing

      81
  • 3.2 Processor Registers

    82
    • 3.2.1 Control registers

      82
    • 3.2.2 General-purpose registers

      84
    • 3.2.3 ES and CS registers

      85
    • 3.2.4 Special function registers (SFRs)

      86
    • 3.2.5 Extended special function registers (2nd SFRs)

      92
  • 3.3 Instruction Address Addressing

    99
    • 3.3.1 Relative addressing

      99
    • 3.3.2 Immediate addressing

      99
    • 3.3.3 Table indirect addressing

      100
    • 3.3.4 Register direct addressing

      101
  • 3.4 Addressing for Processing Data Addresses

    102
    • 3.4.1 Implied addressing

      102
    • 3.4.2 Register addressing

      102
    • 3.4.3 Direct addressing

      103
    • 3.4.4 Short direct addressing

      104
    • 3.4.5 SFR addressing

      105
    • 3.4.6 Register indirect addressing

      106
    • 3.4.7 Based addressing

      107
    • 3.4.8 Based indexed addressing

      111
    • 3.4.9 Stack addressing

      112
• CHAPTER 4 PORT FUNCTIONS

  116
  • 4.1 Port Functions

    116
  • 4.2 Port Configuration

    117
    • 4.2.1 Port 0

      118
    • 4.2.2 Port 1

      118
    • 4.2.3 Port 2

      119
    • 4.2.4 Port 3

      119
    • 4.2.5 Port 4

      120
    • 4.2.6 Port 5

      120
    • 4.2.7 Port 6

      120
    • 4.2.8 Port 7

      121
    • 4.2.9 Port 12

      121
    • 4.2.10 Port 13

      121
    • 4.2.11 Port 14

      122
    • 4.2.12 Port 15

      122
  • 4.3 Registers Controlling Port Function

    123
    • 4.3.1 Port mode registers (PMxx)

      125
    • 4.3.2 Port registers (Pxx)

      126
    • 4.3.3 Pull-up resistor option registers (PUxx)

      127
    • 4.3.4 Port input mode registers (PIMxx)

      128
    • 4.3.5 Port output mode registers (POMxx)

      129
    • 4.3.6 Port mode control registers (PMCxx)

      130
    • 4.3.7 A/D port configuration register (ADPC)

      131
    • 4.3.8 Peripheral I/O redirection register (PIOR)

      132
    • 4.3.9 Global digital input disable register (GDIDIS)

      133
    • 4.3.10 Global analog input disable register (GAIDIS)

      134
  • 4.4 Port Function Operations

    135
    • 4.4.1 Writing to I/O port

      135
    • 4.4.2 Reading from I/O port

      135
    • 4.4.3 Operations on I/O port

      135
    • 4.4.4 Handling different potential (1.8 V or 2.5 V) by using EVDD ≤ VDD

      136
    • 4.4.5 Handling different potential (1.8 V or 2.5 V) by using I/O buffers

      136
  • 4.5 Register Settings When Using Alternate Function

    138
    • 4.5.1 Basic concept when using alternate function

      138
    • 4.5.2 Register settings for alternate function whose output function is not used

      139
    • 4.5.3 Register setting examples for used port and alternate functions

      140
  • 4.6 Cautions When Using Port Function

    157
    • 4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn)

      157
    • 4.6.2 Notes on specifying the pin settings

      158
• CHAPTER 5 CLOCK GENERATOR

  159
  • 5.1 Functions of Clock Generator

    159
  • 5.2 Configuration of Clock Generator

    161
  • 5.3 Registers Controlling Clock Generator

    163
    • 5.3.1 Clock operation mode control register (CMC)

      163
    • 5.3.2 System clock control register (CKC)

      166
    • 5.3.3 Clock operation status control register (CSC)

      167
    • 5.3.4 Oscillation stabilization time counter status register (OSTC)

      168
    • 5.3.5 Oscillation stabilization time select register (OSTS)

      170
    • 5.3.6 Peripheral enable register 0 (PER0)

      172
    • 5.3.7 Subsystem clock supply mode control register (OSMC)

      175
    • 5.3.8 High-speed on-chip oscillator frequency select register (HOCODIV)

      176
    • 5.3.9 High-speed on-chip oscillator trimming register (HIOTRM)

      177
  • 5.4 System Clock Oscillator

    178
    • 5.4.1 X1 oscillator

      178
    • 5.4.2 XT1 oscillator

      178
    • 5.4.3 High-speed on-chip oscillator

      182
    • 5.4.4 Low-speed on-chip oscillator

      182
  • 5.5 Clock Generator Operation

    183
  • 5.6 Controlling Clock

    185
    • 5.6.1 Example of setting high-speed on-chip oscillator

      185
    • 5.6.2 Example of setting X1 oscillation clock

      186
    • 5.6.3 Example of setting XT1 oscillation clock

      187
    • 5.6.4 CPU clock status transition diagram

      188
    • 5.6.5 Condition before changing CPU clock and processing after changing CPU clock

      194
    • 5.6.6 Time required for switchover of CPU clock and system clock

      196
    • 5.6.7 Conditions before clock oscillation is stopped

      197
  • 5.7 Resonator and Oscillator Constants

    198
• CHAPTER 6 TIMER ARRAY UNIT

  202
  • 6.1 Functions of Timer Array Unit

    204
    • 6.1.1 Independent channel operation function

      204
    • 6.1.2 Simultaneous channel operation function

      205
    • 6.1.3 8-bit timer operation function (channels 1 and 3 only)

      206
    • 6.1.4 LIN-bus supporting function (channel 7 of unit 0 only)

      207
  • 6.2 Configuration of Timer Array Unit

    208
    • 6.2.1 Timer count register mn (TCRmn)

      213
    • 6.2.2 Timer data register mn (TDRmn)

      215
  • 6.3 Registers Controlling Timer Array Unit

    216
    • 6.3.1 Peripheral enable register 0 (PER0)

      217
    • 6.3.2 Timer clock select register m (TPSm)

      218
    • 6.3.3 Timer mode register mn (TMRmn)

      221
    • 6.3.4 Timer status register mn (TSRmn)

      226
    • 6.3.5 Timer channel enable status register m (TEm)

      227
    • 6.3.6 Timer channel start register m (TSm)

      228
    • 6.3.7 Timer channel stop register m (TTm)

      229
    • 6.3.8 Timer input select register 0 (TIS0)

      230
    • 6.3.9 Timer output enable register m (TOEm)

      231
    • 6.3.10 Timer output register m (TOm)

      232
    • 6.3.11 Timer output level register m (TOLm)

      233
    • 6.3.12 Timer output mode register m (TOMm)

      234
    • 6.3.13 Input switch control register (ISC)

      235
    • 6.3.14 Noise filter enable register 1 (NFEN1)

      236
    • 6.3.15 Registers controlling port functions of pins to be used for timer I/O

      238
  • 6.4 Basic Rules of Timer Array Unit

    239
    • 6.4.1 Basic rules of simultaneous channel operation function

      239
    • 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only)

      241
  • 6.5 Operation of Counter

    242
    • 6.5.1 Count clock (fTCLK)

      242
    • 6.5.2 Start timing of counter

      244
    • 6.5.3 Operation of counter

      245
  • 6.6 Channel Output (TOmn Pin) Control

    250
    • 6.6.1 TOmn pin output circuit configuration

      250
    • 6.6.2 TOmn pin output setting

      251
    • 6.6.3 Cautions on channel output operation

      252
    • 6.6.4 Collective manipulation of TOmn bit

      257
    • 6.6.5 Timer interrupt and TOmn pin output at operation start

      258
  • 6.7 Timer Input (TImn) Control

    259
    • 6.7.1 TImn pin input circuit configuration

      259
    • 6.7.2 Noise filter

      259
    • 6.7.3 Cautions on channel input

      260
  • 6.8 Independent Channel Operation Function of Timer Array Unit

    261
    • 6.8.1 Operation as interval timer/square wave output

      261
    • 6.8.2 Operation as external event counter

      267
    • 6.8.3 Operation as frequency divider (channel 0 of unit 0 only)

      272
    • 6.8.4 Operation as input pulse interval measurement

      276
    • 6.8.5 Operation as input signal high-/low-level width measurement

      280
    • 6.8.6 Operation as delay counter

      284
  • 6.9 Simultaneous Channel Operation Function of Timer Array Unit

    289
    • 6.9.1 Operation as one-shot pulse output function

      289
    • 6.9.2 Operation as PWM function

      296
    • 6.9.3 Operation as multiple PWM output function

      303
  • 6.10 Cautions When Using Timer Array Unit

    311
    • 6.10.1 Cautions when using timer output

      311
• CHAPTER 7 REAL-TIME CLOCK

  312
  • 7.1 Functions of Real-time Clock

    312
  • 7.2 Configuration of Real-time Clock

    313
  • 7.3 Registers Controlling Real-time Clock

    315
    • 7.3.1 Peripheral enable register 0 (PER0)

      316
    • 7.3.2 Subsystem clock supply mode control register (OSMC)

      317
    • 7.3.3 Real-time clock control register 0 (RTCC0)

      318
    • 7.3.4 Real-time clock control register 1 (RTCC1)

      319
    • 7.3.5 Second count register (SEC)

      321
    • 7.3.6 Minute count register (MIN)

      321
    • 7.3.7 Hour count register (HOUR)

      322
    • 7.3.8 Day count register (DAY)

      324
    • 7.3.9 Week count register (WEEK)

      325
    • 7.3.10 Month count register (MONTH)

      326
    • 7.3.11 Year count register (YEAR)

      326
    • 7.3.12 Watch error correction register (SUBCUD)

      327
    • 7.3.13 Alarm minute register (ALARMWM)

      328
    • 7.3.14 Alarm hour register (ALARMWH)

      328
    • 7.3.15 Alarm week register (ALARMWW)

      328
    • 7.3.16 Port mode register 3 (PM3)

      329
    • 7.3.17 Port register 3 (P3)

      329
  • 7.4 Real-time Clock Operation

    330
    • 7.4.1 Starting operation of real-time clock

      330
    • 7.4.2 Shifting to HALT/STOP mode after starting operation

      331
    • 7.4.3 Reading/writing real-time clock

      332
    • 7.4.4 Setting alarm of real-time clock

      334
    • 7.4.5 1 Hz output of real-time clock

      335
    • 7.4.6 Example of watch error correction of real-time clock

      336
• CHAPTER 8 12-BIT INTERVAL TIMER

  341
  • 8.1 Functions of 12-bit Interval Timer

    341
  • 8.2 Configuration of 12-bit Interval Timer

    341
  • 8.3 Registers Controlling 12-bit Interval Timer

    342
    • 8.3.1 Peripheral enable register 0 (PER0)

      342
    • 8.3.2 Subsystem clock supply mode control register (OSMC)

      343
    • 8.3.3 Interval timer control register (ITMC)

      344
  • 8.4 12-bit Interval Timer Operation

    345
    • 8.4.1 12-bit interval timer operation timing

      345
    • 8.4.2 Starting counter operation after returning from HALT or STOP mode and then shifting to HALT or STOP mode again

      346
• CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER

  347
  • 9.1 Functions of Clock Output/Buzzer Output Controller

    347
  • 9.2 Configuration of Clock Output/Buzzer Output Controller

    349
  • 9.3 Registers Controlling Clock Output/Buzzer Output Controller

    349
    • 9.3.1 Clock output select registers n (CKSn)

      349
    • 9.3.2 Registers controlling port functions of pins to be used for clock or buzzer output

      351
  • 9.4 Operations of Clock Output/Buzzer Output Controller

    352
    • 9.4.1 Operation as output pin

      352
  • 9.5 Cautions of Clock Output/Buzzer Output Controller

    352
• CHAPTER 10 WATCHDOG TIMER

  353
  • 10.1 Functions of Watchdog Timer

    353
  • 10.2 Configuration of Watchdog Timer

    354
  • 10.3 Register Controlling Watchdog Timer

    355
    • 10.3.1 Watchdog timer enable register (WDTE)

      355
  • 10.4 Operation of Watchdog Timer

    356
    • 10.4.1 Controlling operation of watchdog timer

      356
    • 10.4.2 Setting overflow time of watchdog timer

      357
    • 10.4.3 Setting window open period of watchdog timer

      358
    • 10.4.4 Setting watchdog timer interval interrupt

      359
• CHAPTER 11 A/D CONVERTER

  360
  • 11.1 Function of A/D Converter

    360
  • 11.2 Configuration of A/D Converter

    363
  • 11.3 Registers Used in A/D Converter

    365
    • 11.3.1 Peripheral enable register 0 (PER0)

      366
    • 11.3.2 A/D converter mode register 0 (ADM0)

      367
    • 11.3.3 A/D converter mode register 1 (ADM1)

      379
    • 11.3.4 A/D converter mode register 2 (ADM2)

      380
    • 11.3.5 12-bit A/D conversion result register (ADCR)

      382
    • 11.3.6 8-bit A/D conversion result register (ADCRH)

      383
    • 11.3.7 Analog input channel specification register (ADS)

      384
    • 11.3.8 Conversion result comparison upper limit setting register (ADUL)

      386
    • 11.3.9 Conversion result comparison lower limit setting register (ADLL)

      386
    • 11.3.10 A/D test register (ADTES)

      387
    • 11.3.11 Registers controlling port function of analog input pins

      388
  • 11.4 A/D Converter Conversion Operations

    389
  • 11.5 Input Voltage and Conversion Results

    391
  • 11.6 A/D Converter Operation Modes

    392
    • 11.6.1 Software trigger mode (select mode, sequential conversion mode)

      392
    • 11.6.2 Software trigger mode (select mode, one-shot conversion mode)

      393
    • 11.6.3 Software trigger mode (scan mode, sequential conversion mode)

      394
    • 11.6.4 Software trigger mode (scan mode, one-shot conversion mode)

      395
    • 11.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode)

      396
    • 11.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode)

      397
    • 11.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode)

      398
    • 11.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode)

      399
    • 11.6.9 Hardware trigger wait mode (select mode, sequential conversion mode)

      400
    • 11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)

      401
    • 11.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode)

      402
    • 11.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode)

      403
  • 11.7 A/D Converter Setup Flowchart

    404
    • 11.7.1 Setting up software trigger mode

      405
    • 11.7.2 Setting up hardware trigger no-wait mode

      406
    • 11.7.3 Setting up hardware trigger wait mode

      407
    • 11.7.4 Setup when temperature sensor output voltage/internal reference voltage is selected (example for software trigger mode and one-shot conversion mode)

      408
    • 11.7.5 Setting up test mode

      409
  • 11.8 SNOOZE Mode Function

    410
  • 11.9 How to Read A/D Converter Characteristics Table

    414
  • 11.10 Cautions for A/D Converter

    416
• CHAPTER 12 SERIAL ARRAY UNIT

  420
  • 12.1 Functions of Serial Array Unit

    421
    • 12.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21)

      421
    • 12.1.2 UART (UART0 to UART2)

      422
    • 12.1.3 Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)

      423
  • 12.2 Configuration of Serial Array Unit

    424
    • 12.2.1 Shift register

      427
    • 12.2.2 Lower 8/9 bits of the serial data register mn (SDRmn)

      427
  • 12.3 Registers Controlling Serial Array Unit

    429
    • 12.3.1 Peripheral enable register 0 (PER0)

      430
    • 12.3.2 Serial clock select register m (SPSm)

      431
    • 12.3.3 Serial mode register mn (SMRmn)

      432
    • 12.3.4 Serial communication operation setting register mn (SCRmn)

      433
    • 12.3.5 Higher 7 bits of the serial data register mn (SDRmn)

      436
    • 12.3.6 Serial flag clear trigger register mn (SIRmn)

      438
    • 12.3.7 Serial status register mn (SSRmn)

      439
    • 12.3.8 Serial channel start register m (SSm)

      441
    • 12.3.9 Serial channel stop register m (STm)

      442
    • 12.3.10 Serial channel enable status register m (SEm)

      443
    • 12.3.11 Serial output enable register m (SOEm)

      444
    • 12.3.12 Serial output register m (SOm)

      445
    • 12.3.13 Serial output level register m (SOLm)

      446
    • 12.3.14 Serial standby control register 0 (SSC0)

      448
    • 12.3.15 Input switch control register (ISC)

      449
    • 12.3.16 Noise filter enable register 0 (NFEN0)

      450
    • 12.3.17 Registers controlling port functions of serial input/output pins

      451
  • 12.4 Operation Stop Mode

    452
    • 12.4.1 Stopping the operation by units

      452
    • 12.4.2 Stopping the operation by channels

      453
  • 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) Communication

    454
    • 12.5.1 Master transmission

      457
    • 12.5.2 Master reception

      467
    • 12.5.3 Master transmission/reception

      477
    • 12.5.4 Slave transmission

      487
    • 12.5.5 Slave reception

      497
    • 12.5.6 Slave transmission/reception

      505
    • 12.5.7 SNOOZE mode function

      515
    • 12.5.8 Calculating transfer clock frequency

      519
    • 12.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) communication

      521
  • 12.6 Operation of UART (UART0 to UART2) Communication

    522
    • 12.6.1 UART transmission

      525
    • 12.6.2 UART reception

      535
    • 12.6.3 SNOOZE mode function

      542
    • 12.6.4 Calculating baud rate

      550
    • 12.6.5 Procedure for processing errors that occurred during UART (UART0 to UART2) communication

      554
  • 12.7 LIN Communication Operation

    555
    • 12.7.1 LIN transmission

      555
    • 12.7.2 LIN reception

      558
  • 12.8 Operation of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) Communication

    564
    • 12.8.1 Address field transmission

      567
    • 12.8.2 Data transmission

      573
    • 12.8.3 Data reception

      577
    • 12.8.4 Stop condition generation

      582
    • 12.8.5 Calculating transfer rate

      583
    • 12.8.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication

      585
• CHAPTER 13 SERIAL INTERFACE IICA

  586
  • 13.1 Functions of Serial Interface IICA

    586
  • 13.2 Configuration of Serial Interface IICA

    589
  • 13.3 Registers Controlling Serial Interface IICA

    592
    • 13.3.1 Peripheral enable register 0 (PER0)

      592
    • 13.3.2 IICA control register 00 (IICCTL00)

      593
    • 13.3.3 IICA status register 0 (IICS0)

      598
    • 13.3.4 IICA flag register 0 (IICF0)

      601
    • 13.3.5 IICA control register 01 (IICCTL01)

      603
    • 13.3.6 IICA low-level width setting register 0 (IICWL0)

      605
    • 13.3.7 IICA high-level width setting register 0 (IICWH0)

      605
    • 13.3.8 Port mode register 6 (PM6)

      606
  • 13.4 I2C Bus Mode Functions

    607
    • 13.4.1 Pin configuration

      607
    • 13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers

      608
  • 13.5 I2C Bus Definitions and Control Methods

    610
    • 13.5.1 Start conditions

      610
    • 13.5.2 Addresses

      611
    • 13.5.3 Transfer direction specification

      611
    • 13.5.4 Acknowledge (ACK)

      612
    • 13.5.5 Stop condition

      613
    • 13.5.6 Wait

      614
    • 13.5.7 Canceling wait

      616
    • 13.5.8 Interrupt request (INTIICA0) generation timing and wait control

      617
    • 13.5.9 Address match detection method

      618
    • 13.5.10 Error detection

      618
    • 13.5.11 Extension code

      618
    • 13.5.12 Arbitration

      619
    • 13.5.13 Wakeup function

      621
    • 13.5.14 Communication reservation

      624
    • 13.5.15 Cautions

      628
    • 13.5.16 Communication operations

      629
    • 13.5.17 Timing of I2C interrupt request (INTIICA0) occurrence

      636
  • 13.6 Timing Charts

    657
• CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR

  672
  • 14.1 Functions of Multiplier and Divider/Multiply-Accumulator

    672
  • 14.2 Configuration of Multiplier and Divider/Multiply-Accumulator

    672
    • 14.2.1 Multiplication/division data register A (MDAH, MDAL)

      674
    • 14.2.2 Multiplication/division data register B (MDBL, MDBH)

      675
    • 14.2.3 Multiplication/division data register C (MDCL, MDCH)

      676
  • 14.3 Register Controlling Multiplier and Divider/Multiply-Accumulator

    678
    • 14.3.1 Multiplication/division control register (MDUC)

      678
  • 14.4 Operations of Multiplier and Divider/Multiply-Accumulator

    680
    • 14.4.1 Multiplication (unsigned) operation

      680
    • 14.4.2 Multiplication (signed) operation

      681
    • 14.4.3 Multiply-accumulation (unsigned) operation

      682
    • 14.4.4 Multiply-accumulation (signed) operation

      684
    • 14.4.5 Division operation

      686
• CHAPTER 15 DMA CONTROLLER

  688
  • 15.1 Functions of DMA Controller

    688
  • 15.2 Configuration of DMA Controller

    689
    • 15.2.1 DMA SFR address register n (DSAn)

      689
    • 15.2.2 DMA RAM address register n (DRAn)

      690
    • 15.2.3 DMA byte count register n (DBCn)

      691
  • 15.3 Registers Controlling DMA Controller

    692
    • 15.3.1 DMA mode control register n (DMCn)

      692
    • 15.3.2 DMA operation control register n (DRCn)

      694
  • 15.4 Operation of DMA Controller

    695
    • 15.4.1 Operation procedure

      695
    • 15.4.2 Transfer mode

      696
    • 15.4.3 Termination of DMA transfer

      696
  • 15.5 Example of Setting of DMA Controller

    697
    • 15.5.1 CSI consecutive transmission

      697
    • 15.5.2 Consecutive capturing of A/D conversion results

      699
    • 15.5.3 UART consecutive reception + ACK transmission

      701
    • 15.5.4 Holding DMA transfer pending by DWAITn bit

      702
    • 15.5.5 Forced termination by software

      703
  • 15.6 Cautions on Using DMA Controller

    705
• CHAPTER 16 INTERRUPT FUNCTIONS

  708
  • 16.1 Interrupt Function Types

    708
  • 16.2 Interrupt Sources and Configuration

    708
  • 16.3 Registers Controlling Interrupt Functions

    714
    • 16.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)

      718
    • 16.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)

      719
    • 16.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H)

      721
    • 16.3.4 External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge enable registers (EGN0, EGN1)

      723
    • 16.3.5 Program status word (PSW)

      725
  • 16.4 Interrupt Servicing Operations

    726
    • 16.4.1 Maskable interrupt request acknowledgment

      726
    • 16.4.2 Software interrupt request acknowledgment

      729
    • 16.4.3 Multiple interrupt servicing

      729
    • 16.4.4 Interrupt request hold

      733
• CHAPTER 17 KEY INTERRUPT FUNCTION

  734
  • 17.1 Functions of Key Interrupt

    734
  • 17.2 Configuration of Key Interrupt

    735
  • 17.3 Register Controlling Key Interrupt

    737
    • 17.3.1 Key return control register (KRCTL)

      737
    • 17.3.2 Key return mode registers 0, 1 (KRM0, KRM1)

      738
    • 17.3.3 Key return flag register (KRF)

      739
    • 17.3.4 Port mode registers 0 to 2, 7, 12, 15 (PM0 to PM2, PM7, PM12, PM15)

      740
    • 17.3.5 Peripheral I/O redirection register (PIOR)

      741
  • 17.4 Key Interrupt Operation

    742
    • 17.4.1 When not using the key interrupt flag (KRMD = 0)

      742
    • 17.4.2 When using the key interrupt flag (KRMD = 1)

      743
• CHAPTER 18 STANDBY FUNCTION

  746
  • 18.1 Standby Function

    746
  • 18.2 Registers Controlling Standby Function

    747
  • 18.3 Standby Function Operation

    747
    • 18.3.1 HALT mode

      747
    • 18.3.2 STOP mode

      752
    • 18.3.3 SNOOZE mode

      757
• CHAPTER 19 RESET FUNCTION

  760
  • 19.1 Timing of Reset Operation

    762
  • 19.2 States of Operation During Reset Periods

    764
  • 19.3 Register for Confirming Reset Source

    766
    • 19.3.1 Reset control flag register (RESF)

      766
• CHAPTER 20 POWER-ON-RESET CIRCUIT

  769
  • 20.1 Functions of Power-on-reset Circuit

    769
  • 20.2 Configuration of Power-on-reset Circuit

    770
  • 20.3 Operation of Power-on-reset Circuit

    770
• CHAPTER 21 VOLTAGE DETECTOR

  774
  • 21.1 Functions of Voltage Detector

    774
  • 21.2 Configuration of Voltage Detector

    775
  • 21.3 Registers Controlling Voltage Detector

    775
    • 21.3.1 Voltage detection register (LVIM)

      776
    • 21.3.2 Voltage detection level register (LVIS)

      777
  • 21.4 Operation of Voltage Detector

    780
    • 21.4.1 When used as reset mode

      780
    • 21.4.2 When used as interrupt mode

      782
    • 21.4.3 When used as interrupt & reset mode

      784
  • 21.5 Cautions for Voltage Detector

    790
• CHAPTER 22 SAFETY FUNCTIONS

  792
  • 22.1 Overview of Safety Functions

    792
  • 22.2 Registers Used by Safety Functions

    793
  • 22.3 Operation of Safety Functions

    793
    • 22.3.1 Flash memory CRC operation function (high-speed CRC)

      793
    • 22.3.2 CRC operation function (general-purpose CRC)

      796
    • 22.3.3 RAM parity error detection function

      798
    • 22.3.4 RAM guard function

      800
    • 22.3.5 SFR guard function

      801
    • 22.3.6 Invalid memory access detection function

      802
    • 22.3.7 Frequency detection function

      804
    • 22.3.8 A/D test function

      806
• CHAPTER 23 REGULATOR

  811
  • 23.1 Regulator Overview

    811
• CHAPTER 24 OPTION BYTE

  812
  • 24.1 Functions of Option Bytes

    812
    • 24.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H)

      812
    • 24.1.2 On-chip debug option byte (000C3H/ 010C3H)

      813
  • 24.2 Format of User Option Byte

    814
  • 24.3 Format of On-chip Debug Option Byte

    818
  • 24.4 Setting of Option Byte

    819
• CHAPTER 25 FLASH MEMORY

  820
  • 25.1 Serial Programming Using Flash Memory Programmer

    822
    • 25.1.1 Programming environment

      824
    • 25.1.2 Communication mode

      824
  • 25.2 Serial Programming Using External Device (that Incorporates UART)

    825
    • 25.2.1 Programming environment

      825
    • 25.2.2 Communication mode

      826
  • 25.3 Connection of Pins on Board

    827
    • 25.3.1 P40/TOOL0 pin

      827
    • 25.3.2 RESET pin

      827
    • 25.3.3 Port pins

      828
    • 25.3.4 REGC pin

      828
    • 25.3.5 X1 and X2 pins

      828
    • 25.3.6 Power supply

      828
  • 25.4 Serial Programming Method

    829
    • 25.4.1 Serial programming procedure

      829
    • 25.4.2 Flash memory programming mode

      830
    • 25.4.3 Selecting communication mode

      832
    • 25.4.4 Communication commands

      832
  • 25.5 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value)

    834
  • 25.6 Self-Programming

    835
    • 25.6.1 Self-programming procedure

      836
    • 25.6.2 Boot swap function

      837
    • 25.6.3 Flash shield window function

      839
  • 25.7 Security Settings

    840
  • 25.8 Data Flash

    842
    • 25.8.1 Data flash overview

      842
    • 25.8.2 Register controlling data flash memory

      842
    • 25.8.3 Procedure for accessing data flash memory

      843
• CHAPTER 26 ON-CHIP DEBUG FUNCTION

  844
  • 26.1 Connecting E1 On-Chip Debugging Emulator

    844
  • 26.2 On-Chip Debug Security ID

    845
  • 26.3 Securing of User Resources

    845
• CHAPTER 27 BCD CORRECTION CIRCUIT

  847
  • 27.1 BCD Correction Circuit Function

    847
  • 27.2 Registers Used by BCD Correction Circuit

    847
    • 27.2.1 BCD correction result register (BCDADJ)

      847
  • 27.3 BCD Correction Circuit Operation

    848
• CHAPTER 28 INSTRUCTION SET

  850
  • 28.1 Conventions Used in Operation List

    850
    • 28.1.1 Operand identifiers and specification methods

      850
    • 28.1.2 Description of operation column

      851
    • 28.1.3 Description of flag operation column

      852
    • 28.1.4 PREFIX instruction

      852
  • 28.2 Operation List

    853
• CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = -40 to +85 degree)

  870
  • 29.1 Absolute Maximum Ratings

    871
  • 29.2 Oscillator Characteristics

    873
    • 29.2.1 X1, XT1 oscillator characteristics

      873
    • 29.2.2 On-chip oscillator characteristics

      873
  • 29.3 DC Characteristics

    874
    • 29.3.1 Pin characteristics

      874
    • 29.3.2 Supply current characteristics

      879
  • 29.4 AC Characteristics

    885
  • 29.5 Peripheral Functions Characteristics

    890
    • 29.5.1 Serial array unit

      890
    • 29.5.2 Serial interface IICA

      913
  • 29.6 Analog Characteristics

    916
    • 29.6.1 A/D converter characteristics

      916
    • 29.6.2 Temperature sensor, internal reference voltage output characteristics

      921
    • 29.6.3 POR circuit characteristics

      921
    • 29.6.4 LVD circuit characteristics

      922
    • 29.6.5 Supply voltage rise slope characteristics

      923
  • 29.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics

    924
  • 29.8 Flash Memory Programming Characteristics

    924
  • 29.9 Dedicated Flash Memory Programmer Communication (UART)

    924
  • 29.10 Timing Specs for Switching Flash Memory Programming Modes

    925
• CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105 degree)

  926
  • 30.1 Absolute Maximum Ratings

    927
  • 30.2 Oscillator Characteristics

    929
    • 30.2.1 X1, XT1 oscillator characteristics

      929
    • 30.2.2 On-chip oscillator characteristics

      929
  • 30.3 DC Characteristics

    930
    • 30.3.1 Pin characteristics

      930
    • 30.3.2 Supply current characteristics

      935
  • 30.4 AC Characteristics

    941
  • 30.5 Peripheral Functions Characteristics

    945
    • 30.5.1 Serial array unit

      945
    • 30.5.2 Serial interface IICA

      963
  • 30.6 Analog Characteristics

    964
    • 30.6.1 A/D converter characteristics

      964
    • 30.6.2 Temperature sensor, internal reference voltage output characteristics

      968
    • 30.6.3 POR circuit characteristics

      968
    • 30.6.4 LVD circuit characteristics

      969
    • 30.6.5 Supply voltage rise slope characteristics

      969
  • 30.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics

    970
  • 30.8 Flash Memory Programming Characteristics

    970
  • 30.9 Dedicated Flash Memory Programmer Communication (UART)

    970
  • 30.10 Timing Specs for Switching Flash Memory Programming Modes

    971
• CHAPTER 31 PACKAGE DRAWINGS

  972
  • 31.1 25-pin Products

    972
  • 31.2 32-pin Products

    973
  • 31.3 48-pin Products

    974
  • 31.4 64-pin Products

    976
• APPENDIX A REVISION HISTORY

  978
  • A.1 Major Revisions in This Edition

    978
  • A.2 Revision History of Preceding Editions

    989
• Colophon

  1002
• Address List

  1003
• Back Cover

  1004